KR101720264B1

KR101720264B1 - Method of manufacturing printed circuit board

Info

Publication number: KR101720264B1
Application number: KR1020150125203A
Authority: KR
Inventors: 이민우; 고영주
Original assignee: 대덕전자 주식회사
Priority date: 2015-09-04
Filing date: 2015-09-04
Publication date: 2017-04-03
Also published as: KR20170029035A

Abstract

According to the present invention, a first copper layer is formed on the surface of a first insulating layer or embedded in a first insulating layer by an ETS method in accordance with a predetermined circuit pattern, and then a first copper layer is formed on a first copper layer, And a copper plating layer is formed to define a cavity region. Then, the second insulating layer and the second copper foil are laminated, and the second copper foil is etched according to a predetermined circuit pattern so that the surface of the second insulating layer corresponding to the cavity area is opened. Then, when the cavity is drilled to form a cavity, and then the upper second insulating layer is drilled with a drill to form holes, an alkali etching solution is sprayed through the hole to penetrate the lower copper plating layer through the hole, The cavity is formed by etching the plating layer. At this time, the first copper foil under the cavity is protected from the attack of the etching solution by the alkali etch resist film, and the first copper under the cavity is soldered to the chip terminal at the time of chip mounting.

Description

[0001] METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board manufacturing method including a printed circuit board (PCB), particularly a cavity, and more particularly, to a method of manufacturing a cavity for mounting a semiconductor chip or other components.

Recently, portable electronic products have become popular, so that it is required to reduce the size of electronic component parts and to concentrate system integration technology. In order to meet such demands, an ETS (Embedded Trace) technique for embedding a circuit and a cavity-type substrate manufacturing technique for embedding and assembling parts in a substrate are important in addition to a thin plate circuit board manufacturing technique and a fine pattern circuit forming technique .

Embedded PCB, which embeds passive devices or active devices in the PCB manufacturing process, has the advantage of increasing the degree of freedom of wiring design around the parts. However, compatibility problems with PCB raw materials, Technically difficult.

In the case of a cavity PCB for positioning and assembling components in a space within a PCB, the degree of freedom in circuit design may be somewhat reduced. However, the manufacturing cost is less risky than the embedded PCB manufacturing method, have.

In particular, recently, with the recent development of electronic devices mentioned above, semiconductor or parts are inserted and assembled into a cavity of a semiconductor package substrate to thin the final thickness of the component, thereby reducing the circuit length and increasing the signal transmission speed, It is required to develop a cavity type substrate manufacturing method capable of improving the degree of integration of a circuit and improving the degree of circuit integration. Various methods have been introduced by the cavity substrate manufacturing method. 1 to 4 are views showing a conventional method of manufacturing a cavity-type substrate according to the related art.

1 is a diagram showing a laser drilling method according to the prior art (US patent application US 2015/0090688), in which a space to form a cavity in a substrate is ablated by a laser. In the laser drilling method of FIG. 1, the laser ablation processing time is long, the depth of the cavity space is limited, and the productivity is low depending on the size of the cavity space to be manufactured. In addition, a metal that is not damaged by the laser beam is required on the bottom surface, and a copper circuit or other material must be used to make a desired depth, and a circuit can not be formed on the bottom surface.

FIG. 2 is a view showing a fill-cut method according to the prior art (PCT International Patent Publication No. WO 2011/099820 A2), in which a release film such as a polyimide tape, a double-sided tape or a release ink is coated Then, the laser is cut and peeled off to make the cavity. However, this method requires accurate positioning of the release film, requires a lot of repetitive automatic or manual work, has a limitation on the thickness of the release film, may cause jamming during lamination, Damage may occur.

3 is a diagram showing a mechanical routing method according to the prior art (US 7,665,206 B2), in which a cavity is machined using a mechanical router. This method poses the risk that the cavity thickness depth control must be very precise and may cause mechanical damage to the bottom circuit or other lower layers.

FIG. 4 is a view showing a prepreg window working and bonding method according to the prior art, in which a prepreg prepreg prepared by punching an area in which a cavity is to be formed is attached, And it is difficult to apply it to a package substrate which requires a fine positional matching due to contraction / expansion of a material. Also, the resin flow of the bonding material prepreg must be managed at all times. When the layer including the cavity in the laminated structure includes two or more bonding materials, the matching degree of each bonding layer affects the shape of the final cavity.

1. PCT International Patent Publication No. WO 2011/099820 A2. 2. U.S. Patent Application Publication 2008/0117608 A1. 3. United States Patent Application US 2015/0090688. 4. U.S. Pat. No. 7,665,206 B2.

A first object of the present invention is to provide a method for manufacturing a cavity in which a semiconductor chip or a component can be mounted on an outer layer, and a circuit board to which the semiconductor chip or the component can be mounted.

A second object of the present invention is to provide a cavity manufacturing method and a circuit board to which the method is applied in addition to the first object.

A third object of the present invention is to provide a cavity manufacturing method and a circuit board to which a circuit can be formed, in which a circuit can be formed on a lower surface as well as a processing time is shortened and a lower surface is not damaged .

A fourth object of the present invention is to provide a cavity fabrication method and a circuit board using the cavity fabrication method which can easily perform cavity processing with a four-layer thickness (about 200 mu m) in addition to the first, second, and third objects.

Since the cavity is formed by a chemical method by penetrating the etching solution into the hole drilled with the drill, the etching time is shortened, the lower surface is not damaged, and the circuit can be formed on the lower surface .

Since the cavity manufacturing method according to the present invention can form a circuit on the floor, design freedom is increased and design freedom with respect to the cavity height is increased. The present invention further enables various finish processing after the final finish processing. Furthermore, the present invention has the advantage of enabling the present invention to be implemented with existing facilities and drugs without designing new facilities or using drugs. It is possible to form the cavity without preprocessing the prepreg or reinforcement reinforced with the glass fiber, and there is an advantage in favor of cavity and circuit matching.

FIGS. 1 to 4 schematically illustrate various cavity fabrication techniques according to the prior art,
5A to 5O are views showing a cavity manufacturing method according to the first embodiment of the present invention.
6A to 6C are views showing a cavity manufacturing method according to a second embodiment of the present invention.
7 is a view showing a cavity manufacturing method according to a third embodiment of the present invention.
8A to 8E are views schematically showing a process sequence of an ETS method applied in accordance with a third embodiment of the present invention.

The present invention relates to a method of manufacturing a circuit board, comprising the steps of: (a) forming a first copper foil to which a pattern is transferred; (b) forming a first mask exposing a portion of the first copper transferred with the pattern and covering the remainder; (c) forming an alkali etch resist on the first copper foil whose surface is not covered with the first mask, and then peeling off the first mask; (d) forming a seed layer on the front surface for electroplating, and forming a second mask on the seed layer, onto which a predetermined pattern defining a cavity area is transferred; (e) electroplating to form a copper plating layer on the exposed seed layer; (f) peeling off the second mask and performing flash etching to remove the exposed seed layer; (g) laminating a second insulating layer and a second copper foil and heating and pressing them to form a laminate; (h) selectively etching the second copper foil to transfer the circuit pattern, selectively removing the second copper foil such that the surface of the second insulating layer corresponding to the cavity area is opened; (i) a step of forming a protective layer by covering a part of the second copper foil on which the circuit pattern is transferred with a solder resist, and performing a finishing treatment on the exposed second copper foil; (j) drilling the second insulating layer whose surface is exposed, forming a cavity to be formed, and drilling holes in the second insulating layer to puncture the hole into which the alkali etching solution penetrates; (k) spraying an alkaline etching solution and causing the alkaline etching solution to permeate through the hole, thereby etching the copper plating layer under the second insulating layer with the alkaline etching solution; And (l) conducting a pickling and washing process to remove residues such as an epoxy resin, a copper plating layer, and the like, thereby forming a cavity.

The present invention relates to a method of manufacturing a circuit board, comprising the steps of: (a) forming a first copper foil to which a pattern is transferred; (b) forming a first mask exposing a portion of the first copper transferred with the pattern and covering the remainder; (c) forming an alkali etch resist on the first copper foil whose surface is not covered with the first mask, and then peeling off the first mask; (d) forming a seed layer on the front surface for electroplating, and forming a second mask on the seed layer, onto which a predetermined pattern defining a cavity area is transferred; (e) electroplating to form a copper plating layer on the exposed seed layer; (f) peeling off the second mask and performing flash etching to remove the exposed seed layer; (g) laminating a second insulating layer and a second copper foil and heating and pressing them to form a laminate; (h) selectively etching the second copper foil to transfer the circuit pattern, selectively removing the second copper foil such that the surface of the second insulating layer corresponding to the cavity area is opened; (i) forming a protective layer by coating a solder resist on a part of the second copper foil on which the circuit pattern is transferred; (j) covering the third mask so as to protect the copper foils on the surface including the second copper and open only the surface of the second insulating layer corresponding to the cavity area; (k) drilling a second insulating layer having a surface exposed, forming a cavity to be formed, and drilling holes in the second insulating layer to perforate a hole through which the alkali etching solution penetrates; (1) spraying an alkaline etching solution and causing the alkaline etching solution to penetrate through the hole, thereby etching the copper plating layer under the second insulating layer with an alkaline etching solution; (m) forming a cavity by removing residues such as an epoxy resin and a copper plating layer through a pickling and washing process; And (n) peeling the third mask and subjecting the copper foil having the exposed surface, including the second copper foil, to a finishing treatment.

Hereinafter, with reference to FIGS. 5, 6, 7 and 8, a cavity manufacturing method according to the present invention and a circuit board technology using the same will be described in detail.

5A to 5O are views showing a cavity manufacturing method according to the first embodiment of the present invention. Referring to FIG. 5A, a copper foil 20 is formed by transferring a predetermined circuit pattern to both surfaces of an insulating layer 10. [

As a preferred embodiment of the present invention, a copper clad laminate (CCL) can be used, and a copper circuit can be formed on both sides of a substrate by applying various subtractive processes or additive processes have.

Techniques relating to circuit formation of a fine pattern can be found in reference to Korean Patent No. 109,538 (Korean Patent No. 1,436,827; Korean Patent No. 1,077,774) filed by the present applicant. The insulating layer 10 may be made of resin, epoxy resin, or fiber reinforced prepreg, or the like.

At this time, a copper foil pattern (ETS) having a shape buried in the insulating layer 10 can be formed on one surface or both surfaces of the insulating layer 10, and the cavity method using the ETS pattern can be formed by a method shown in Figs. 8A to 8E The third embodiment of the invention will be described later.

Referring to FIG. 5B, a first plating resist 30 is formed on the copper foil 20 onto which the pattern is transferred. As a preferred embodiment of the first plating resist 30 according to the present invention, a dry film (D / F), ink, LPR or the like is coated and a series of image processes such as photography, development, So that a predetermined pattern can be transferred by pattern transfer.

Referring to FIG. 5C, an alkali etch resist 40 film is formed on the exposed copper foil 20 with the first plating resist 30 covered. Alkali etch resist protects copper by attack of alkaline etching solution. It is used for ENIG (Electroless Nickel Immersion Gold), ENEPIG (Electroless Nickel / Electroless Palladium Replacement Gold Plating; Electroless Nickel Electroless Palladium Immersion Gold), Sn (tin), and SnPb (tin lead).

5D, the first plating resist 30 is stripped and electroless copper plating is performed to form an electroless plated layer 50 on the entire surface of the substrate on which the surface is exposed. Next, referring to FIG. 5E, the second plating resist 60 is formed again. As a preferred embodiment of the second plating resist 30 according to the present invention, a predetermined pattern is transferred by coating a dry film, ink, or LPR and proceeding a series of image processes such as photography, development, etching, etc. And make them.

Referring to FIG. 5F, the copper plating layer 70 is formed by performing electroplating and electroplating with the electroless copper plating layer 50 as a seed layer. Note that the copper plating layer 70 region formed here corresponds to the cavity region to be produced in the subsequent process. Referring to FIG. 5G, the second plating resist 60 is stripped off.

Referring to FIG. 5H, soft etching (flash etching) is performed to remove the seed layer, that is, the electroless plated layer 50 remaining on the substrate surface. Referring to FIG. 5I, the insulating layer 80 and the copper foil 90 are laminated and laminated by heating and pressing. As a preferred embodiment of the present invention, resin coated copper (RCC) can be used. As another embodiment of the present invention, another circuit layer may be laminated and formed as an outer layer.

Referring to FIG. 5J, the circuit pattern can be transferred by selectively etching the copper foil 90 of the outer layer. At this time, it is preferable to open the copper foil 90 on the surface so that the surface of the insulating layer 80 corresponding to the area of the copper plating layer 70 corresponding to the cavity area is exposed.

Referring to FIG. 5K, a solder resist 100 for protecting the copper foil 90 in the outer layer is printed on the surface of the outer layer and applied. Referring to FIG. 51, a finish treatment film 110 is coated on a copper foil whose surface is exposed (for example, pad or bump for wafer bonding or solder bonding). As the finish processing according to the present invention, ENEPIG, ENIG, EAG, Soft Au, or the like can be implemented.

Subsequently, outer contour processing is performed to fabricate the cavity. Referring to FIG. 5M, laser routing or mechanical routing is performed on the region where the cavity is to be formed, and holes 120 are drilled through the drill to allow the alkali etching solution to permeate. The present invention differs from the prior art in that the entire area for forming the cavity is not subjected to laser ablation or cutting with a router but the holes are drilled to allow the alkali etching solution to permeate have.

Referring to FIG. 5N, when an ammonia-based alkali etching solution, for example, an alkaline cupric chloride solution or an ammonium copper composite ion etching solution is sprayed, the etching solution seeps into the hole 120 to melt the copper plating layer 70 I will. At this time, copper (Cu) coated with the alkali etch resist film (40, 110) is protected from the attack of the alkali etching solution.

The cavity 150 is obtained by removing the residues such as an epoxy resin that has filled the cavity through the pickling and washing process. 5O, the semiconductor chip 200 is mounted in the cavity 150, the wire bonding is performed to the outer surface of the finned pad 210, and the pad 220 is finely processed on the bottom surface of the cavity 150 Solder joint is possible.

6A to 6C are views showing a cavity manufacturing method according to a second embodiment of the present invention. In the second embodiment of the present invention, after the solder resist printing process of FIGS. 5A to 5K for explaining the first embodiment of the present invention is carried out, a mask is formed for the second-type finish processing, An example in which a two-kind finish treatment is performed is illustrated.

That is, it is understood that the process of FIG. 6A is performed after proceeding the processes of FIGS. 5A to 5K. Referring to FIG. 6A, a dry film is coated and a pattern is transferred to form a mask 130. FIG. In a preferred embodiment of the present invention, the upper surface cavity of the substrate is opened at the site to be fabricated, and the entire lower surface is masked with a mask.

Referring to FIG. 6B, laser processing or mechanical routing is performed on the opening area where the cavity is to be formed in the state of covering the mask 130, and holes 120 are drilled through a laser drill or a mechanical drill to form an alkali etching solution So that it can permeate. The present invention differs from the prior art in that the entire area for forming the cavities is not laser ablated or cut by a router but holes 120 are drilled to allow the alkali etching solution to permeate have.

Referring to FIG. 6C, when an ammonia-based alkali etching solution, for example, copper chloride is sprayed, the etching solution seeps into the hole 120 to dissolve the copper plating layer 70. At this time, copper (Cu) coated with the alkali etch resist film 40 and copper (Cu) covered with the mask 130 are protected from attack of the alkali etching solution.

Subsequently, the mask 130 made of a dry film is peeled off, and pickling and washing steps are carried out, so that all the residue is removed and the cavity 150 is formed. Referring to FIG. 6C, when the OSP process is performed on the lower surface copper foil of the substrate, the OSP coating 260 is formed. That is, in the second embodiment of the present invention, the one-side copper foil of the substrate is subjected to the gold-plating finish treatment and the opposite-side copper foil is subjected to the OSP finish treatment.

7 is a view showing a cavity manufacturing method according to a third embodiment of the present invention. Referring to FIG. 7, the insulating layer 10 is etched to form a cavity 150, and the cavity bottom pattern 20 is an embedded trace pattern of a buried type.

A method for producing the ETS pattern is described in detail in the specification of the present applicant's prior patent application (Korean Patent No. 1,063,519; Korean Patent No. 1,082,778), so that the method of manufacturing the ETS copper foil pattern can be understood. The ETS copper-clad circuit has a feature of embedding the copper foil in the insulating layer, and has an advantage in that the interval between the patterns, that is, the pitch can be reduced as compared with the conventional method.

8A to 8E are views schematically showing the ETS method. 8A, a detachable core 100 having a thick copper foil 300b and a base copper foil 300c coated thereon as an adhesive is formed on a core 300a serving as a support as a starting material do. That is, it is understood that a thick copper foil (also referred to as a carrier copper foil) 300b and a base copper foil 300c are temporarily adhered with an adhesive and peeled and separated from each other by applying a slight physical force.

(Not shown) is coated on the digitizable core 300, and a series of image operations such as photographing, developing and etching are performed to transfer a predetermined circuit pattern onto the dry film to produce a first plating mask (not shown) do. When copper plating is performed in a state in which the first plating mask is coated, a copper foil circuit is formed of the first copper plating layer 310 on the base copper foil 300c as shown in Fig. 8A.

Referring to FIG. 8B, the second insulating layer 320 and the second copper foil 330 are laminated and laminated by heating and pressing. At this time, a prepreg (PPG) can be used as a preferred embodiment of the second insulating layer 320.

Next, a dry film (not shown) is coated, a series of image operations such as photographing, developing, etching, and the like are performed to transfer a predetermined circuit pattern onto the dry film to produce a second plating mask (not shown). When copper plating is performed in a state in which the second plating mask is coated, a copper foil circuit is formed of the second copper plating layer 340 on the second copper foil 330 as shown in Fig. 8C.

Then strip the Diatable Core. That is, the base copper foil 300c and the carrier copper foil 300b are separated and peeled off. Then, as shown in Fig. 8D, the base copper foil 300c and the second copper foil 330 are partially exposed on the surface. 8E, a base copper foil 300c having a surface exposed by flash etching and a second copper foil 140 not covered with the second copper plating layer 150 are etched and removed.

Referring to FIG. 8E, a copper foil circuit embedded in the insulating layer is obtained on the lower surface of the second insulating layer 320. FIG. After the ETS circuit shown in FIG. 8E is obtained, the cavity manufacturing method according to the present invention is proceeded as it is according to FIGS. 5A to 5P to obtain the substrate of FIG.

The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

Claims

A method of manufacturing a circuit board,
(a) forming a first copper transferred pattern;
(b) forming a first mask exposing a portion of the first copper transferred with the pattern and covering the remainder;
(c) forming an alkali etch resist on the first copper foil whose surface is not covered with the first mask, and then peeling off the first mask;
(d) forming a seed layer on the front surface for electroplating, and forming a second mask on the seed layer, onto which a predetermined pattern defining a cavity area is transferred;
(e) electroplating to form a copper plating layer on the exposed seed layer;
(f) peeling off the second mask and performing flash etching to remove the exposed seed layer;
(g) laminating a second insulating layer and a second copper foil and heating and pressing them to form a laminate;
(h) selectively etching the second copper foil to transfer the circuit pattern, selectively removing the second copper foil such that the surface of the second insulating layer corresponding to the cavity area is opened;
(i) a step of forming a protective layer by covering a part of the second copper foil on which the circuit pattern is transferred with a solder resist, and performing a finishing treatment on the exposed second copper foil;
(j) drilling the second insulating layer whose surface is exposed, forming a cavity to be formed, and drilling holes in the second insulating layer to puncture the hole into which the alkali etching solution penetrates;
(k) spraying an alkali etchant to cause the alkali etchant to penetrate through the holes, thereby etching the copper-plated layer under the second insulating layer with an alkaline etchant; And
(l) forming a cavity by removing the residue of the second insulating layer generated during the boring process in the step (j) and the copper plating residue generated during the etching process in the step (k) through the pickling and washing process,
&Lt; / RTI >

A method of manufacturing a circuit board,
(a) forming a first copper transferred pattern;
(b) forming a first mask exposing a portion of the first copper transferred with the pattern and covering the remainder;
(c) forming an alkali etch resist on the first copper foil whose surface is not covered with the first mask, and then peeling off the first mask;
(d) forming a seed layer on the front surface for electroplating, and forming a second mask on the seed layer, onto which a predetermined pattern defining a cavity area is transferred;
(e) electroplating to form a copper plating layer on the exposed seed layer;
(f) peeling off the second mask and performing flash etching to remove the exposed seed layer;
(g) laminating a second insulating layer and a second copper foil and heating and pressing them to form a laminate;
(h) selectively etching the second copper foil to transfer the circuit pattern, selectively removing the second copper foil such that the surface of the second insulating layer corresponding to the cavity area is opened;
(i) forming a protective layer by coating a solder resist on a part of the second copper foil on which the circuit pattern is transferred;
(j) covering the third mask so as to protect the copper foils on the surface including the second copper and open only the surface of the second insulating layer corresponding to the cavity area;
(k) drilling a second insulating layer having a surface exposed, forming a cavity to be formed, and drilling holes in the second insulating layer to perforate a hole through which the alkali etching solution penetrates;
(1) spraying an alkaline etching solution and allowing the alkaline etching solution to penetrate through the hole, thereby etching the copper plating layer under the second insulating layer with an alkaline etching solution;
(m) forming a cavity by removing the residue of the second insulating layer generated during the boring process in the step (k) and the copper plating residue generated during the etching process in the step (l) by conducting the pickling and washing process; And
(n) peeling the third mask, and performing a finish treatment on the copper foil whose surface is exposed, including the second copper foil
&Lt; / RTI >

The method according to any one of claims 1 to 5, wherein the first copper foil of step (a) is formed on a surface of the first insulating layer.

The circuit board according to any one of claims 1 to 3, wherein the first copper layer of the step (a) is exposed and the remaining three surfaces are embedded in the first insulating layer. Gt;

The method of claim 1 or 2, wherein the alkali etch resist of step (c) acts to protect copper by attack of an alkali etching solution, and ENIG (electroless nickel substituted gold plating; (Electroless Nickel Immersion Gold), ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), Sn (tin), and SnPb (tin lead).