KR101694857B1 - Apparatus and method for processing time synchronization packet - Google Patents
Apparatus and method for processing time synchronization packet Download PDFInfo
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- KR101694857B1 KR101694857B1 KR1020150069830A KR20150069830A KR101694857B1 KR 101694857 B1 KR101694857 B1 KR 101694857B1 KR 1020150069830 A KR1020150069830 A KR 1020150069830A KR 20150069830 A KR20150069830 A KR 20150069830A KR 101694857 B1 KR101694857 B1 KR 101694857B1
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
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Abstract
A method and apparatus for processing a time synchronized packet are provided. The apparatus for processing a time synchronization packet according to various embodiments of the present invention includes a processor for performing time synchronization and a time synchronization packet in a received packet and extracting time information used for time synchronization in the confirmed time synchronization packet And a time synchronization packet processing module for delivering the extracted time information to the processor and discarding the time synchronization packet.
Description
The present invention relates to a method and apparatus for processing a time synchronization packet. And more particularly, to a method and apparatus for processing a time synchronization packet to minimize the burden on a processor performing time synchronization.
A device that receives time information received from a time synchronization source such as GPS (Global Positioning System) and transmits GPS time information through a packet network such as Ethernet is referred to as a master device, and a packet network such as Ethernet A device to perform time synchronization based on GPS may be referred to as a time synchronization device (for example, a slave device).
Network time protocol (NTP) and Precision Time Protocol (PTP) are typical methods for implementing time synchronization through a packet network. Generally, the method of implementing the time synchronization through the packet network is implemented by software.
In addition, the time synchronization apparatus can perform time synchronization at the time of the master apparatus by calculating the start time and the arrival time of a packet transmitting and receiving its own time difference with the master apparatus. This time difference calculation is more accurate, and for high precision time synchronization, the time stamping method for packets used for time synchronization must be minimized in variability. For this purpose, a method of processing time stamping in hardware is used.
Although there is a method of transmitting / receiving packets more frequently between the time synchronization device and the master device for high-precision time synchronization, a large load is required for generation and transmission / reception of the packets. In recent years, the time synchronization and the general user packet are processed by the same processor in a small terminal device. In order to perform high-precision time synchronization in such a device, there is a problem that the burden of time synchronization is increased.
According to various embodiments of the present invention, an apparatus for processing a time synchronization packet includes a processor for performing time synchronization and a time synchronization packet in a received packet, And a time synchronization packet processing module for delivering the extracted time information to the processor and discarding the time synchronization packet.
According to various embodiments of the present invention, a method of processing a time synchronization packet includes the steps of confirming a time synchronization packet in a received packet, extracting time information used for time synchronization in the confirmed time synchronization packet, And transferring the extracted time information to a processor that performs the time synchronization packet transmission and discarding the time synchronization packet.
According to various embodiments of the present invention, an apparatus for processing a time synchronization packet includes: a processor that performs time synchronization; and a processor that acquires time information from the processor, generates a time synchronization packet using the obtained time information, And a time synchronization packet processing module for time-stamping and transmitting the generated time synchronization packet.
According to various embodiments of the present invention, a time synchronization packet processing method includes: acquiring time information from a processor performing time synchronization; generating a time synchronization packet using the obtained time information; And transmitting the synchronous packet by time stamping.
The time synchronization apparatus according to various embodiments of the present invention may be configured such that a time synchronization packet that places a heavy burden on the processor for time synchronization is processed by the generation and reception of the time synchronization packet through a separate hardware module, The burden can be reduced. In addition, time synchronization can be performed more precisely by processing the time synchronization packet through a separate hardware module.
1 is a block diagram of a time synchronization apparatus according to a comparative example.
2 is a block diagram of a time synchronization device in accordance with various embodiments of the present invention.
3 is a view for explaining a time synchronization packet according to various embodiments of the present invention.
4 is a flow diagram of a method for processing received data by a time synchronization device in accordance with various embodiments of the present invention.
5 is a flowchart of a method of processing a time synchronous packet by the time synchronizing apparatus according to various embodiments of the present invention.
6 is a flowchart of a method of extracting time information according to whether a time synchronization packet is validated by a time synchronization apparatus according to various embodiments of the present invention.
Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings. It should be understood, however, that this invention is not intended to be limited to the particular embodiments described herein but includes various modifications, equivalents, and / or alternatives of the embodiments of this document . In connection with the description of the drawings, like reference numerals may be used for similar components.
In this document, the expressions "having," " having, "" comprising," or &Quot;, and does not exclude the presence of additional features.
In this document, the expressions "A or B," "at least one of A or / and B," or "one or more of A and / or B," etc. may include all possible combinations of the listed items . For example, "A or B," "at least one of A and B," or "at least one of A or B" includes (1) at least one A, (2) Or (3) at least one A and at least one B all together.
As used herein, the terms "first," "second," "first," or "second," and the like may denote various components, regardless of their order and / or importance, But is used to distinguish it from other components and does not limit the components. For example, the first user equipment and the second user equipment may represent different user equipment, regardless of order or importance. For example, without departing from the scope of the rights described in this document, the first component can be named as the second component, and similarly the second component can also be named as the first component.
(Or functionally or communicatively) coupled with / to "another component (eg, a second component), or a component (eg, a second component) Quot; connected to ", it is to be understood that any such element may be directly connected to the other element or may be connected through another element (e.g., a third element). On the other hand, when it is mentioned that a component (e.g., a first component) is "directly connected" or "directly connected" to another component (e.g., a second component) It can be understood that there is no other component (e.g., a third component) between other components.
As used herein, the phrase " configured to " (or set) to be "configured according to circumstances may include, for example, having the capacity to, To be designed to, "" adapted to, "" made to, "or" capable of ". The term " configured to (or set up) "may not necessarily mean" specifically designed to "in hardware. Instead, in some situations, the expression "configured to" may mean that the device can "do " with other devices or components. For example, a processor configured (or configured) to perform the phrases "A, B, and C" may be implemented by executing one or more software programs stored in a memory device or a dedicated processor (e.g., an embedded processor) , And a generic-purpose processor (e.g., a CPU or an application processor) capable of performing the corresponding operations.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the other embodiments. The singular expressions may include plural expressions unless the context clearly dictates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art. The general predefined terms used in this document may be interpreted in the same or similar sense as the contextual meanings of the related art and, unless expressly defined in this document, include ideally or excessively formal meanings . In some cases, even the terms defined in this document can not be construed as excluding the embodiments of this document.
Hereinafter, referring to the accompanying drawings, an apparatus according to various embodiments will be described. In this document, the term user may refer to a person or device using the device (e.g., an artificial intelligence electronic device).
1 is a block diagram of a time synchronization apparatus according to a comparative example.
A device that receives disarmed information from a time synchronization source such as GPS and transmits GPS time information through a packet network is referred to as a master device and a device that performs time synchronization based on GPS through a packet network is referred to as a time synchronization device Slave device).
The
The
Here, the time synchronization packet may be a packet used in the time synchronization process between the
In order to more precisely calculate the time difference by the
Further, in order to keep the time synchronization between the
As described above, in the recent time synchronization, the generation of the time synchronization packet used for the time synchronization is generated and processed by the software executed by the
However, since the level of time synchronization required in recent years is increased, the number of times of sampling of the time synchronization packet used for time synchronization is rapidly increased. In addition, in the case of the
2 is a block diagram of a time synchronization device in accordance with various embodiments of the present invention.
The
The
The time synchronization packet processing module 220 according to various embodiments of the present invention may be hardware logic configured separately from the processor performing time synchronization. The time synchronization packet processing module 220 may be hardware logic configured by hardware-based logic such as the
The time synchronization packet processing module 220 may be added between the
In addition, since the time synchronization packet is processed or generated through the time synchronization packet processing module 220, which is a hardware logic separately configured from the
The time synchronization packet processing module 220 according to various embodiments of the present invention can confirm the time synchronization packet in the received packet received through the
The time synchronization packet processing module 220 according to various embodiments of the present invention can check the time synchronization packet by checking whether a packet matching the format of the preset time synchronization packet among the received packets exists. The format of the preset time synchronization packet may be set based on a standard related to the time synchronization packet.
The time synchronization packet processing module 220 according to various embodiments of the present invention extracts time information used for time synchronization with the master device in the confirmed time synchronization packet and performs time synchronization with the extracted time information Lt; / RTI > processor. The time information may be information that the master device acquires from the main time source such as GPS and transmits through the time synchronization packet.
The time synchronization packet processing module 220 according to various embodiments of the present invention can discard the time synchronization packet from which the time information is extracted. In this manner, the time synchronization packet processing module 220 transmits only the time information for performing time synchronization with the master device to the
The time synchronization packet processing module 220 according to various embodiments of the present invention can further extract transmission time information of the time synchronization packet by time stamping the time synchronization packet. For this purpose, the time synchronization packet processing module 220 may perform the functions of the
The time difference between the
In addition, the time synchronization packet processing module 220 may perform time stamping to more accurately calculate the time difference. As described above, in order to calculate the time difference more accurately, the variability of the time stamping should be minimized, and the variability of the time stamping may be minimized when the time stamping is processed in hardware. Therefore, the time stamping can be minimized by performing time stamping on the time synchronization packet in the time synchronization packet processing module 220 configured with hardware logic.
According to various embodiments of the present invention, the time synchronization packet processing module 220 can check the validity of the confirmed time synchronization packet based on the format of the preset time synchronization packet. As described above, the format of the preset time synchronization packet can be set based on the standard related to the time synchronization packet. The time synchronization
When the validity of the time synchronization packet is confirmed, the time synchronization packet processing module 220 can extract the time information from the validated time synchronization packet. The time synchronization packet processing module 220 may first check validity before extracting the time information.
According to various embodiments of the present invention, the time synchronization packet processing module 220 obtains time information and generation information for the time synchronization packet from the
The time synchronization packet processing module 220 may periodically generate the time synchronization packet. In addition, the packet processing module 220 may acquire time information and the like from the
The time synchronization packet processing module 220 may time-stamp the generated time synchronization packet and transmit the time synchronization packet to the master device through the
As described above, in the
3 is a view for explaining a time synchronization packet according to various embodiments of the present invention.
3, a description will be given of a method in which a time synchronization packet used for time synchronization is transmitted and received between a master device and a time synchronization device.
Referring to FIG. 3 (a), a sync packet may be generated in the master device and transmitted to the time synchronization device. The master device may periodically transmit the sync packet to the time synchronization device. Further, the master device can time-stamp the time at which the sync packet is transmitted, and transmit the time packet by including it in the sync packet.
Also, referring to FIG. 3 (b), the master device may further generate a follow-up packet. The master device may further generate the follow-up packet and transmit the start sync packet including the start time information to the time synchronization device.
The sync packet and the follow-up packet may be generated by the master device, and the master device may include hardware logic for processing and generating a time synchronization packet, such as the time synchronization packet processing module 220 described with reference to FIG. 2 . Accordingly, the master device can generate the sync packet and the follow-up packet in hardware, and transmit the sync packet and the follow-up packet to the time synchronization device. The information required to generate the time synchronization packet, such as the sync packet generation period, the MAC address of the time synchronization device, and the IP address of the time synchronization device, It may be provided as hardware logic for processing the time synchronization packet of the master device.
When receiving the sync packet, the time synchronization device time stamps the arrival time of the sync packet in the time synchronization packet processing module 220, which is a hardware logic, and transmits the transmission time information and the arrival time information included in the sync packet And transmit it to the
Referring to FIG. 3 (c), the delay_request packet may be a packet periodically generated by the time synchronization device and transmitted to the master device. Accordingly, when the time synchronization packet processing module 220 of the time synchronization device changes during initialization or operation of the device, the time synchronization packet processing module 220 periodically transmits the delay request packet to the time synchronization packet processing module 220, A request packet can be generated. The time synchronization device may transmit the generated delay_request packet to the master device and store the transmission time of the delay_request packet.
When receiving the delay_request packet, the master device timestamps the arrival time of the delay_request packet. When the delay_request packet is determined to be valid by checking the validity of the delay_request packet, Delay-response packet. The contents of the Delay_Response packet may utilize the information of the Delay_request packet, and the Delay_Response packet may be discarded thereafter. In addition, the master device may include the arrival time information of the delay_request packet in the delay_response packet and forward it to the time synchronization device.
Upon receiving the delay_receipt packet, the time synchronization device checks whether the delay_receive packet is a delay_received packet received in response to the delay_receive packet transmitted by itself, through validation of the delay_receive packet Can be distinguished. The time synchronization packet processing module 220 of the time synchronizing apparatus checks whether the delay_receipt_packet transmission time information and the delay_reception packet included in the delay_reception packet included in the delay_reception packet, Can be extracted. The time synchronization packet processing module 220 may transmit the extracted time information to the
Referring to FIG. 3 (d), the master device can periodically transmit announcement packets to the time synchronization device. Accordingly, the announcement packet may also be periodically generated in the hardware logic for processing and generating the time synchronous packet of the master device, and information for generating the announcement packet may be obtained from the processor of the master device .
Referring to FIG. 3 (e), a request packet and a response packet are used in the time synchronization of the NTP scheme, and both the transmission time information and the arrival time information are timestamped for the two packets. The NTP time synchronization device generates a request packet in the time synchronization packet processing module of the NTP time synchronization device at the time of inputting at the time of device initialization, and transmits the request packet including the departure time information of the request packet to the NTP server.
The NTP server stores arrival time information of the request packet and includes arrival time information of the request packet when generating a response packet. The NTP server also includes transmission time information in the request packet in the response packet. The NTP server may transmit the response packet transmission time information to the NTP time synchronization device in the response packet.
When receiving the response packet, the NTP time synchronization device time stamps the arrival time information of the response packet, and if the response packet is determined as a valid packet through the validation check, Time information of the response packet to the processor of the NPT time synchronization apparatus. The processor calculates the time difference with the NTP server using the acquired time information and performs time synchronization with the NTP server by correcting the time of the time difference.
4 is a flow diagram of a method for processing received data by a time synchronization device in accordance with various embodiments of the present invention.
In
In
In
In
In
5 is a flowchart of a method of processing a time synchronous packet by the time synchronizing apparatus according to various embodiments of the present invention.
In
In
In
As described with reference to FIGS. 4 and 5, the time synchronization packet processing module, which is hardware logic separately configured from the processor, processes and generates a time synchronization packet used for time synchronization so that the processor processes and generates the time synchronization packet It can alleviate the burden. Further, by processing and generating the time synchronizing packet through the time synchronization packet processing module which is a hardware logic, variability in the time synchronizing packet processing and generation is minimized, and the time synchronizing packet processing and generation can be performed more precisely . Accordingly, even if the time synchronization packet is more frequently exchanged between the master device and the time synchronization device for high-precision time synchronization, the processing load for performing the time synchronization in the master device and the processor of the time synchronization device does not increase .
6 is a flowchart of a method of extracting time information according to whether a time synchronization packet is validated by a time synchronization apparatus according to various embodiments of the present invention.
In
In
Each of the components described in this document may be composed of one or more components, and the name of the component may be changed according to the type of the device. In various embodiments, an apparatus may comprise at least one of the elements described herein, and some elements may be omitted or further include additional elements. In addition, some of the components of the apparatus according to various embodiments may be combined to constitute one entity, so that the functions of the corresponding components before being combined can be performed in the same manner.
As used in this document, the term "module" may refer to a unit comprising, for example, one or a combination of two or more of hardware, software or firmware. A "module" may be interchangeably used with terms such as, for example, unit, logic, logical block, component, or circuit. A "module" may be a minimum unit or a portion of an integrally constructed component. A "module" may be a minimum unit or a portion thereof that performs one or more functions. "Modules" may be implemented either mechanically or electronically. For example, a "module" may be an application-specific integrated circuit (ASIC) chip, field-programmable gate arrays (FPGAs) or programmable-logic devices And may include at least one.
At least a portion of a device (e.g., modules or functions thereof) or a method (e.g., operations) according to various embodiments may include, for example, computer-readable storage media in the form of program modules, As shown in FIG. When the instruction is executed by a processor (e.g., processor 120), the one or more processors may perform a function corresponding to the instruction. The computer readable storage medium may be, for example,
The computer readable recording medium may be a hard disk, a floppy disk, a magnetic media (e.g., a magnetic tape), an optical media (e.g., a compact disc read only memory (CD-ROM) digital versatile discs, magneto-optical media such as floptical disks, hardware devices such as read only memory (ROM), random access memory (RAM) Etc. The program instructions may also include machine language code such as those produced by a compiler, as well as high-level language code that may be executed by a computer using an interpreter, etc. The above- May be configured to operate as one or more software modules to perform the operations of the embodiment, and vice versa.
Modules or program modules according to various embodiments may include at least one or more of the elements described above, some of which may be omitted, or may further include additional other elements. Operations performed by modules, program modules, or other components in accordance with various embodiments may be performed in a sequential, parallel, iterative, or heuristic manner. Also, some operations may be performed in a different order, omitted, or other operations may be added. And the embodiments disclosed in this document are presented for the purpose of explanation and understanding of the disclosed technology and do not limit the scope of the technology described in this document. Accordingly, the scope of this document should be interpreted to include all modifications based on the technical idea of this document or various other embodiments.
Claims (20)
A communication module for receiving a packet from the master device;
A processor for performing time synchronization with the master device; And
When the time synchronization packet is confirmed in the packet received through the communication module, extracts time information used for time synchronization in the confirmed time synchronization packet, delivers the extracted time information to the processor, A time synchronous packet processing module for discarding the extracted time synchronous packet and for transmitting the confirmed general packet to the processor when a general packet excluding the time synchronous packet is confirmed in a packet received through the communication module;
/ RTI >
Wherein the time synchronization packet processing module is separate hardware separate from the processor.
The time synchronization packet includes:
An at least one of an announce packet, a sync packet, a follow-up packet delay request (Delay_Request), and a delay_response packet (Delay_Response packet).
Wherein the time synchronization packet processing module comprises:
And further extracts transmission time information of the time synchronization packet by time stamping the time synchronization packet.
Wherein the time synchronization packet processing module comprises:
And further transfers the transmission time information.
Wherein the time synchronization packet processing module comprises:
And confirms the validity of the confirmed time synchronization packet based on the format of the preset time synchronization packet.
Wherein the time synchronization packet processing module comprises:
And extracts the time information from the time synchronization packet in which the validity is confirmed when validity of the time synchronization packet is confirmed.
Wherein the time synchronization packet processing module comprises:
Acquires time information and generation information for the time synchronization packet from the processor, and generates a time synchronization packet using the time information and the generation information obtained.
Wherein the time synchronization packet processing module comprises:
Time-stamping the generated time-synchronized packet, and transmitting the generated time-synchronized packet.
Receiving a packet from a master device;
Extracting time information used for time synchronization in the confirmed time synchronization packet when the time synchronization packet is confirmed in the packet received from the master device in the time synchronization packet processing module of the slave device;
Transferring the extracted time information to the processor that performs time synchronization with the master device of the slave device in the time synchronization packet processing module;
Discarding the time synchronization packet from which the time information is extracted in the time synchronization packet processing module; And
When the general packet excluding the time synchronization packet is confirmed in the packet received from the master device in the time synchronization packet processing module,
/ RTI >
Wherein the time synchronization packet processing module is separate hardware separate from the processor.
The time synchronization packet includes:
Wherein the at least one packet includes at least one of an announce packet, a sync packet, a follow_up packet delay_request (Delay_Request), and a delay_response packet (Delay_Response).
The operation of extracting the time information includes:
And time-stamping the time-synchronized packet to further extract transmission time information of the time-synchronized packet.
The operation of transmitting the time information includes:
And further transfers the transmission time information.
An operation of confirming the validity of the confirmed time synchronization packet based on the format of the preset time synchronization packet
Further comprising the steps of:
The operation of extracting the time information includes:
And when the validity of the time synchronization packet is confirmed, extracts the time information from the time synchronization packet in which the validity is confirmed.
Acquiring time information from the processor and generation information on the time synchronization packet; And
An operation of generating a time synchronization packet using the acquired time information and generation information
Further comprising the steps of:
Time-stamping and transmitting the generated time synchronization packet
Further comprising the steps of:
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| JP2011250264A (en) * | 2010-05-28 | 2011-12-08 | Nec Access Technica Ltd | Discarded packet monitoring device, discarded packet monitoring method, and discarded packet monitoring program |
| JP2013106329A (en) * | 2011-11-16 | 2013-05-30 | Fujitsu Ltd | Communication apparatus |
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| JP5579331B2 (en) * | 2011-11-22 | 2014-08-27 | 三菱電機株式会社 | Communication device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2011250264A (en) * | 2010-05-28 | 2011-12-08 | Nec Access Technica Ltd | Discarded packet monitoring device, discarded packet monitoring method, and discarded packet monitoring program |
| JP2013106329A (en) * | 2011-11-16 | 2013-05-30 | Fujitsu Ltd | Communication apparatus |
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