KR101688080B1 - Semiconductor package - Google Patents

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Publication number
KR101688080B1
KR101688080B1 KR1020150127484A KR20150127484A KR101688080B1 KR 101688080 B1 KR101688080 B1 KR 101688080B1 KR 1020150127484 A KR1020150127484 A KR 1020150127484A KR 20150127484 A KR20150127484 A KR 20150127484A KR 101688080 B1 KR101688080 B1 KR 101688080B1
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KR
South Korea
Prior art keywords
passivation film
bonding pad
wire
pad
wire bonding
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KR1020150127484A
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Korean (ko)
Inventor
한이슬
김경태
김병진
유지연
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020150127484A priority Critical patent/KR101688080B1/en
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Publication of KR101688080B1 publication Critical patent/KR101688080B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a semiconductor package which newly improves a structure of a wire bonding pad to which a conductive wire is bonded to easily prevent a bonding pad from rising or separating by a wire bonding force by a capillary. The semiconductor package comprises: a first passivation film formed on a surface of a semiconductor chip excluding a bonding pad; a redistribution line plated from the bonding pad of the semiconductor chip to a desired position of the first passivation film; a second passivation film deposited on a surface of the first passivation film excluding the other end of the redistribution line; and a wire bonding pad which is metal-bound while enclosing a surface and a circumferential surface of the other end of the redistribution line, and forms a plane identical to a surface of the second passivation film or is plated to a height higher than or equal to the surface of the second passivation film.

Description

[0001] SEMICONDUCTOR PACKAGE [0002]

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package which is improved in structure of a bonding pad to which a conductive wire is bonded, and can easily prevent the bonding pad from being lifted or peeled off by a wire bonding force by a capillary To a semiconductor package.

Chip scale packaging technology for packaging each chip at a wafer level and manufacturing it close to the size of the chip is being applied in accordance with the demand for high integration of the semiconductor package and shortening of the light weight.

As an example of the chip scale package, a fan-in package in which an input / output terminal such as a solder ball for electric signal transmission is electrically connected in an area of each chip, and a separate interposer, And a fan-out package that extends the conductive line to the extended portion and fuses the input / output terminal to the extended portion.

The wafer level semiconductor package of the chip scale has a circuit integration process for forming a transistor or the like on a semiconductor chip in a wafer state and a passivation film on the surface for protecting the semiconductor chip from the outside And a step of forming a redistribution layer (RDL), which is a conductive metal wiring line, and the like.

Hereinafter, the structure and manufacturing process of a conventional chip scale package will be described with reference to FIGS. 4 and 5.

First, a semiconductor chip 10 in a wafer state is provided. A designed circuit is integrated in the semiconductor chip 10, and a bonding pad 12 is formed at a portion of the circuit which becomes an electrical input / output path.

A die passivation 14 for protecting integrated circuits is formed on the surface of the semiconductor chip 10 other than the bonding pads 12. A first passivation layer 14 is formed on the die passivation layer 14, A film 16 is formed.

A plurality of metal pads formed in the semiconductor chip 10 in a predetermined arrangement, that is, the bonding pads 12, may be a metal wiring line for receiving a voltage for operating a circuit element integrated in the semiconductor chip, 18 (RDL: redistribution layer) is exposed to the outside so as to be conductively connected.

Next, a process of forming a rewiring line 18 from the bonding pad 12 of the semiconductor chip 10 to a desired position of the first passivation film 16 is performed.

The process of forming the redistribution line 18 includes the steps of forming a seed layer for plating over the top surfaces of the first passivation film and the bonding pad, Exposure and development are performed to expose a region where a bonding pad and a rewiring line of the semiconductor chip are to be formed and a process of electroplating to form a rewiring line in a region where rewiring is to be formed .

Subsequently, a first passivation film 24 is formed on the surfaces of the first passivation film 16 and the rewiring lines 18, and the second passivation film 24 is formed on the surface of the first passivation film 16 and the re- Thereby preventing foreign matter or the like from penetrating into the rewiring lines 18 and preventing a short circuit between the rewiring lines 18 adjacent to each other.

At this time, the other end of the rewiring line 18 is exposed to the outside without being wrapped by the second passivation film 24 so that the wire bonding pad, which is an electrode terminal made of a metal, is plated.

Next, a wire bonding pad 26, which is an electrode terminal made of a metal, is formed at the other end of the rewiring line 18 by a plating process.

More specifically, the wire bonding pad 26 is provided with a connection pad 26a which is electroplatically plated at the other end of the rewiring line 18 and a connection pad 26b which is electrically connected to the side wall of the second passivation film 24 from the connection pad 26a. And a wire connecting pad 26b extending to an upper surface position around the side wall and plated, and wire bonding by a capillary is substantially performed on the wire connecting pad 26b.

Therefore, for electrical connection between the wire connecting pad 26b of the wire bonding pad 26 and the second semiconductor chip 28 stacked on the second passivation film 24 or another adjacent chip or substrate, Bonding is performed.

For example, a capillary, which is a wire bonding mechanism, is bonded to the bonding pad of the second semiconductor chip 28 by first bonding one end of the conductive wire 29 (also referred to as ball bonding) The capillary conducts secondary bonding (also referred to as stitch bonding) of the other end of the conductive wire 29 to the wire connecting pad 26b of the wire bonding pad 26b.

The semiconductor chip 10 and the second semiconductor chip 28 are electrically connected to each other through the conductive wire 29 and the wire bonding pad 26 via the rewiring line 18.

However, the following problems occur in the conventional chip scale package manufacturing process.

The connection pads 26a of the wire bonding pads 26 are plated on the rewiring lines 18 to form a strong metal connection to each other while the wire connection pads 26b to which the actual wire bonding is performed are made of metal And the second passivation film 24 in contact with the wire connection pad 26b is of an insulating resin type.

5, in the state where the bonding force between the wire connecting pad 26b and the second passivation film 24 is distant, the capillary is bonded to the wire connecting pad 26b by the conductive wire 29 There is a problem that the repulsive force of the wire connecting pad 26 is added to cause the wire connecting pad 26b to be lifted or peeled off from the second passivation film 24. [

As a result, when the wire connecting pad 26b is lifted or peeled off from the second passivation film 24, a failure such as breakage of the conductive wire 29 bonded to the wire connecting pad 26b occurs.

Korea Registered Patent Registration No. 10-0799878 (Jan. 24, 2008)

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a wire bonding pad in which the structure of a wire bonding pad to which a conductive wire is bonded is newly improved, And it is an object of the present invention to provide a semiconductor package that can easily prevent the phenomenon of peeling.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a first passivation film formed on a surface of a semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; A wire bonding pad which is metal-bonded while being wrapped around the other end surface and the peripheral surface of the rewiring line and plated to a height equal to or higher than the surface of the second passivation film; And a semiconductor package.

Preferably, the other end of the rewiring line is formed in the shape of a rectangular plate to secure the bonding area of the conductive wire, and the other end surface and the peripheral surface of the rewiring line are surrounded by the wire bonding pad, .

In addition, the wire bonding pad is plated with a Ni / Al material that facilitates metal bonding with rewiring.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a first passivation film formed on a surface of a semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; And a wire bonding pad composed of a connection pad plated on the other end surface of the rewiring line and a wire connection pad extending from the contact pad to the surface of the second passivation film, And a lock end is formed at the bottom of the wire connection pad to be locked in the lock groove and plated.

Preferably, the locking groove is formed in a place where a mask is formed on the first passivation film and then a mask is removed after the second passivation film is formed.

The locking end is inserted and plated in the locking groove during the plating process of the wire bonding pad.

Through the above-mentioned means for solving the problems, the present invention provides the following effects.

According to the present invention, during the manufacturing process of the chip scale package, the structure of the wire bonding pad, which is formed to be conductively stacked on the rewiring line connected to the semiconductor chip, is improved to a structure of rewiring and metal bonding, It is possible to easily prevent the phenomenon that the wire bonding pad is lifted or peeled off even when the wire bonding force by the capillary acts in the wire bonding process of connecting the bonding pad to the second semiconductor chip or another substrate by a conductive wire .

1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention,
2 is a plan view and a side view showing a wire bonding pad structure according to the first embodiment of the present invention,
3 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention,
4 is a cross-sectional view of a conventional semiconductor package,
5 is a sectional view showing a problem occurring in a conventional semiconductor package;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

FIG. 1 is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention, and FIG. 2 is a plan view and a side view illustrating a wire bonding pad structure according to a first embodiment of the present invention.

First, a die passivation 14 for protecting an integrated circuit is formed on the surface of the semiconductor chip 10 in the wafer state except for the bonding pad 12, and on the die passivation 14, The first passivation film 16 is formed.

A plurality of metal pads formed in the semiconductor chip 10 in a predetermined arrangement, that is, the bonding pads 12, may be a metal wiring line for receiving a voltage for operating a circuit element integrated in the semiconductor chip, 18 are exposed to the outside so as to be conductively connected.

Next, a conventional plating process for forming a rewiring line 18 from the bonding pad 12 of the semiconductor chip 10 to a desired position of the first passivation film 16 is performed.

Next, a second passivation film 24 is formed on the surfaces of the first passivation film 16 and the rewiring lines 18, and this second passivation film 24 is formed on the surface of the first passivation film 16 and the rewiring lines 18, Foreign matter or the like is prevented from penetrating into the rewiring line 18, and at the same time, the rewiring line 18 is insulatedly wrapped to prevent electrical shorting between the rewiring lines.

At this time, the other end of the rewiring line 18 is exposed to the outside without being wrapped by the second passivation film 24 so as to be plated with a wire bonding pad, which is an electrode terminal made of metal, And is formed in the shape of a rectangular plate having a larger area than the width of the rewiring line in order to secure a wire bonding space by the pillars.

Next, a wire bonding pad 26 is laminated at the other end of the rewiring line 18 by a plating process. As can be seen in FIG. 2, the wire bonding area and the capillary wire bonding So that the other end surface of the rewiring line 18 and the circumferential surface of the rewiring line 18 are formed to have a square pad shape.

Particularly, the wire bonding pad 26 formed by surrounding the surface and the circumferential surface of the other end of the rewiring line 18 is plated with a Ni / Al material that is easily metal-bonded to a rewiring line (e.g., copper material) And the other end of the rewiring line 18 and the wire bonding pad 26 are in a state of being firmly coupled by metal bonding.

The wire bonding pad 26 which is plated while covering the other end surface of the rewiring wire 18 and the circumferential surface of the rewiring wire 18 is preferably formed so as not to interfere with the second passivation film 24 during wire bonding, ) Of the surface of the substrate.

The conductive wire 29 is connected between the wire bonding pad 26 and the peripheral second semiconductor chip 28 or the substrate in the state where the wire bonding pad 26 is formed at the other end of the re- The wire bonding force of the capillary is applied to the wire bonding pads 26 (26), since the wire bonding pads 26 are firmly metal-bonded on the surface and the circumferential surface of the re- It is possible to easily prevent the wire bonding pad 26 from being lifted or peeled off.

Second Embodiment

3 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention.

First, a die passivation 14 for protecting an integrated circuit is formed on the surface of the semiconductor chip 10 in the wafer state except for the bonding pad 12, as in the first embodiment described above. On the die passivation 14, A first passivation film 16, which is an insulating film, is formed to form a rewiring line.

A plurality of metal pads formed in the semiconductor chip 10 in a predetermined arrangement, that is, the bonding pads 12, may be a metal wiring line for receiving a voltage for operating a circuit element integrated in the semiconductor chip, 18 are exposed to the outside so as to be conductively connected.

Next, a conventional plating process for forming a rewiring line 18 from the bonding pad 12 of the semiconductor chip 10 to a desired position of the first passivation film 16 is performed.

Next, a second passivation film 24 is formed on the surfaces of the first passivation film 16 and the rewiring lines 18, and this second passivation film 24 is formed on the surface of the first passivation film 16 and the rewiring lines 18, Foreign matter or the like is prevented from penetrating into the rewiring line 18, and at the same time, the rewiring line 18 is insulatedly wrapped to prevent electrical shorting between the rewiring lines.

According to the second embodiment of the present invention, when forming the second passivation film 24, a mask (not shown) is provided on the first passivation film 16 corresponding to the adjacent position of the rewiring line 18 Next, when the second passivation film 24 is formed and the mask is removed successively by using a chemical etching process or the like, the lock groove 30 is formed in the place where the mask is removed.

Next, a wire bonding pad 26 is laminated on the other end of the rewiring line 18 by a plating process. As shown in FIG. 2, the wire bonding pad 26 is electrically connected to a re- And a wire connecting pad 26b extending from the connection pad 26a to the upper surface position through the side wall of the second passivation film 24 and plated Respectively.

At this time, when the wire bonding pad 26 is formed of a Ni / Al material using a plating process, a lock groove (not shown) formed in the second passivation film 24 is formed on the bottom of the wire connection pad 26b, 30 are integrally plated and formed.

Therefore, the connection pad 26a of the wire bonding pad 26 is metal-bonded to the surface of the other end of the rewiring line 18 to maintain a strong bonding state, and the wire connection pad 26b of the wire bonding pad 26, The locking end 32 is locked into the lock groove 30 to maintain a strong coupling state with the second passivation film 24. [

The wire connecting pad 26b of the wire bonding pad 26 and the second semiconductor chip 28 or the periphery of the wire bonding pad 26 may be connected to each other in the state where the wire bonding pad 26 is formed at the other end of the re- The wire bonding pad 26b is in the locked state so that the wire bonding force by the capillary acts on the wire connecting pad 26b even when the wire bonding process for connecting the liver with the conductive wire 29 is performed, The phenomenon that the pad 26b is lifted or peeled off can be easily prevented.

10: Semiconductor chip
12: bonding pad
14: die passivation
16: First passivation film
18: Cultivation line
24: second passivation film
26: wire bonding pad
26a: connection pad
26b: Wire connection pad
28: second semiconductor chip
29: conductive wire
30: Locking groove
32: Locking stage

Claims (6)

delete delete delete A first passivation film formed on a surface of the semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; And a wire bonding pad composed of a connection pad plated on the other end surface of the rewiring line and a wire connection pad extending from the contact pad to a position above the surface of the second passivation film,
A locking groove is formed in the second passivation film, and a locking end is formed at the bottom of the wire connection pad to be locked and inserted in the locking groove,
The locking groove is formed in a place where a mask is formed on the first passivation film and then a mask is removed after the second passivation film is formed,
Wherein the locking end is inserted and plated in the locking groove during the plating process of the wire bonding pad. delete delete
KR1020150127484A 2015-09-09 2015-09-09 Semiconductor package KR101688080B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112614817A (en) * 2019-10-03 2021-04-06 南亚科技股份有限公司 Semiconductor element and method for manufacturing the same

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Publication number Priority date Publication date Assignee Title
KR100799878B1 (en) 2007-03-05 2008-01-30 앰코 테크놀로지 코리아 주식회사 Anchor substrate for increasing ball bonding strength, and method for bonding wire using the same
KR20110079282A (en) * 2009-12-31 2011-07-07 주식회사 동부하이텍 Semiconductor device and method of fabricating the same
US20120056322A1 (en) * 2005-12-27 2012-03-08 Fujitsu Semiconductor Limited Semiconductor device with pads of enhanced moisture blocking ability
KR20130004912A (en) * 2010-03-25 2013-01-14 타나카 덴시 코오교오 카부시키가이샤 High-purity cu bonding wire
KR20130077939A (en) * 2011-12-30 2013-07-10 앰코 테크놀로지 코리아 주식회사 Semiconductor package having one-layer substrate and, fan-out semiconductor package and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120056322A1 (en) * 2005-12-27 2012-03-08 Fujitsu Semiconductor Limited Semiconductor device with pads of enhanced moisture blocking ability
KR100799878B1 (en) 2007-03-05 2008-01-30 앰코 테크놀로지 코리아 주식회사 Anchor substrate for increasing ball bonding strength, and method for bonding wire using the same
KR20110079282A (en) * 2009-12-31 2011-07-07 주식회사 동부하이텍 Semiconductor device and method of fabricating the same
KR20130004912A (en) * 2010-03-25 2013-01-14 타나카 덴시 코오교오 카부시키가이샤 High-purity cu bonding wire
KR20130077939A (en) * 2011-12-30 2013-07-10 앰코 테크놀로지 코리아 주식회사 Semiconductor package having one-layer substrate and, fan-out semiconductor package and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112614817A (en) * 2019-10-03 2021-04-06 南亚科技股份有限公司 Semiconductor element and method for manufacturing the same

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