KR101677674B1 - Current sensor for compensating input offset and output delay of voltage amplifier - Google Patents

Current sensor for compensating input offset and output delay of voltage amplifier Download PDF

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KR101677674B1
KR101677674B1 KR1020150139364A KR20150139364A KR101677674B1 KR 101677674 B1 KR101677674 B1 KR 101677674B1 KR 1020150139364 A KR1020150139364 A KR 1020150139364A KR 20150139364 A KR20150139364 A KR 20150139364A KR 101677674 B1 KR101677674 B1 KR 101677674B1
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South Korea
Prior art keywords
voltage
pmos
terminal
nmos
voltage amplifier
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KR1020150139364A
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Korean (ko)
Inventor
양병도
김병진
윤희라
우기찬
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충북대학교 산학협력단
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/10—Measuring sum, difference or ratio

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Abstract

The present invention relates to a current sensor compensating an input offset and an output delay of a voltage amplifier comprising: an I_zero pulse generator which corresponds to I_zero signals output from a voltage amplifier where both ends of a power switch are connected to input ends and controls the power switch; a comparator which is connected to the both ends of the power switch and measures a delay error of input offset voltage and an output value; and an up-down charge pump which adjusts bias voltage of the voltage amplifier from the output of the comparator, and controls the generating time of the I_zero signals. According to the present invention, the comparator measures the delay error of the input offset and the output value of the voltage amplifier, and the comparator output operates the up-down charge pump to adjust the bias voltage of the voltage amplifier, such that an error of currents measurement can be removed. Therefore, the present invention accurately senses the moment when an inductor current is 0 and turns on/off a power NMOS without delay, thereby improving a power efficiency.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a current sensor that compensates an input offset and an output delay of a voltage amplifier,

The present invention relates to a current sensor, and more particularly, to a current sensor that detects an input offset voltage of a voltage amplifier used in a current sensor and an input offset of a voltage amplifier that eliminates a current measurement error due to an output value delay To a current sensor that compensates for output delay.

The buck converter operates in either Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM) depending on the state of the load current. CCM is not a problem because the inductor current does not go down to '0', but when the inductor current goes down to '0' in DCM, the efficiency decreases due to the reverse current. Therefore, it is important to turn off the power switch (hereinafter referred to as "Power NMOS") by measuring the current accurately with the current sensor so that the buck converter does not fall below '0' .

Conventional current sensors measure the voltage across the power (drain and source) of the Power NMOS using a voltage amplifier. Generally, when designing a buck converter, the power NMOS is designed to be large in size to improve efficiency, so when the power NMOS is turned on,

Figure 112015095832265-pat00001
(Turn on resistance) is small. Therefore, the current flowing in the Power NMOS
Figure 112015095832265-pat00002
The voltage formed across both ends of the power NMOS transistor is small and a delay occurs in the output voltage of the voltage amplifier. Also, the input offset of the voltage amplifier caused by the process difference reduces the accuracy of the current sensor.

As described above, the method of detecting the inductor current of the buck converter to turn off the power NMOS is advantageous in that the accuracy of the turn-off time of the power NMOS is lowered due to the input offset voltage and the output value delay of the voltage amplifier itself, There is a problem of being reduced.

Korean Patent Publication No. 10-2012-0129876 (Published on November 28, 2012)

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems of the prior art, and it is an object of the present invention to provide a voltage amplifier, which receives feedback of a current measurement error caused by input offset and output value delay of a voltage amplifier, It is possible to eliminate the current measurement error due to the input offset voltage of the voltage amplifier used in the current sensor and the output value delay when the buck converter operates in Discontinuous Conduction Mode (DCM). And to compensate the input offset and the output delay of the voltage amplifier.

According to an aspect of the present invention, there is provided a current sensor for compensating for an input offset and an output delay of a voltage amplifier of the present invention, the current sensor compensating for an input offset and an output delay of the voltage amplifier by controlling the power switch in response to an I_zero signal output from a voltage amplifier, An I_zero pulse generator; A comparator connected to both ends of the power switch for measuring an input offset voltage and a delay error of an output value; And an up-down charge pump for adjusting a generation time of the I_zero signal by adjusting a bias voltage of the voltage amplifier from an output of the comparator.

As described above, according to the current sensor which compensates the input offset and the output delay of the voltage amplifier according to the present invention, the input offset of the voltage amplifier and the delay error of the output value are measured by a comparator, By adjusting the bias voltage of the voltage amplifier by operating the pump, current measurement error can be eliminated.

This enables the power efficiency to be improved by accurately sensing the instant when the inductor current becomes '0' and turning off the power NMOS without delay time.

1 to 3 are a circuit diagram and a waveform diagram of a conventional current sensor.
4 is a diagram illustrating an input offset voltage storage technique.
5 is a circuit diagram of a current sensor according to the present invention.
FIG. 6 is a cross-

Figure 112015095832265-pat00003
And an up / down charge pump.
7 is a conceptual diagram for storing the input offset of the comparator of the present invention.
8 to 10 are operation waveform diagrams illustrating a voltage amplifier error of the present invention measured by a comparator.
11 and 12 are operation waveform diagrams of a comparator and an up / down charge pump according to the voltage amplifier error of the present invention.

A current sensor that compensates for an input offset and an output delay of a voltage amplifier of the present invention includes a comparator for measuring an input offset of a voltage amplifier and a delay error of an output value, And an up-down charge pump for regulating the voltage. The input offset present in the comparator is removed using an input offset voltage storage technique. The comparator turns off the Power NMOS to measure the error generated by the voltage amplifier. Then, the output of the comparator, which measures the error of the voltage amplifier, is input to the up / down charge pump to change the bias voltage connected to the output terminal of the up / down charge pump. In this way, an error caused by the input offset of the voltage amplifier and the output value delay is feedbacked to adjust the bias voltage of the voltage amplifier. Therefore, the accuracy of the voltage amplifier can be increased and the power efficiency can be improved.

Hereinafter, a current sensor in which the input offset and the output delay of the voltage amplifier of the present invention are compensated will be described in detail with reference to the accompanying drawings.

First, a current sensor of the present invention will be described after briefly explaining an existing current sensor.

1 to 3 are a circuit diagram and a waveform diagram of a conventional current sensor.

Referring to FIG. 1, in the DCM (Discontinuous Conduction mode) operation of the buck converter,

Figure 112015095832265-pat00004
When turned on, the Power NMOS
Figure 112015095832265-pat00005
Current and resistance
Figure 112015095832265-pat00006
Lt; RTI ID = 0.0 >
Figure 112015095832265-pat00007
Lt; / RTI > Node voltage
Figure 112015095832265-pat00008
And the GNDP voltage become equal, that is, the power NMOS
Figure 112015095832265-pat00009
When the current flowing in the voltage amplifier < RTI ID = 0.0 >
Figure 112015095832265-pat00010
The I_zero signal having an output value of '0' is generated, and a power NMOS
Figure 112015095832265-pat00011
The I_zero signal for turning off the I_zero signal is generated through the I_zero pulse generator.

However, existing current sensors have two problems.

First, as shown in FIG. 2, due to a mismatch caused by the process,

Figure 112015095832265-pat00012
An input offset occurs in the input signal. If an input offset is present in the voltage amplifier,
Figure 112015095832265-pat00013
Value is shifted by an offset to accurately measure the current '0'
Figure 112015095832265-pat00014
Lt; / RTI >

Second, as shown in FIG. 3, the power NMOS

Figure 112015095832265-pat00015
Node voltage
Figure 112015095832265-pat00016
The problem arises when the difference between the value and the GNDP voltage value is small. That is,
Figure 112015095832265-pat00017
The output value of the amplifier is changed
Figure 112015095832265-pat00018
A delay time occurs. Because of this, the I_zero signal is generated late and the Power NMOS
Figure 112015095832265-pat00019
Lt; RTI ID = 0.0 > delayed < / RTI > Therefore, a circuit that can eliminate input offset is needed as well as accurate measurement and fast operation in Power NMOS.

4 is a diagram illustrating an input offset voltage storage technique.

Referring to Figure 4,

Figure 112015095832265-pat00020
And a capacitor connected in series with the input terminal by unity-gain feedback,
Figure 112015095832265-pat00021
,
Figure 112015095832265-pat00022
And the input offset voltage is stored in the input offset voltage.

The operation of this circuit consists of a Sampling mode and an Amplifier mode.

In the sampling mode,

Figure 112015095832265-pat00023
~
Figure 112015095832265-pat00024
Lt; / RTI > is turned on,
Figure 112015095832265-pat00025
Wow
Figure 112015095832265-pat00026
Is turned off. Therefore, the terminals A and B have the same voltage as the ground ('0'), and when an input offset is present while a unit gain feedback loop is formed,
Figure 112015095832265-pat00027
An input offset voltage is applied to the capacitor < RTI ID = 0.0 >
Figure 112015095832265-pat00028
and
Figure 112015095832265-pat00029
/ RTI >

In the amplifier mode,

Figure 112015095832265-pat00030
~
Figure 112015095832265-pat00031
Is turned off,
Figure 112015095832265-pat00032
Wow
Figure 112015095832265-pat00033
When turned on,
Figure 112015095832265-pat00034
Receives the input voltage value, and performs amplification.

5 is a circuit diagram of a current sensor according to the present invention.

5, the current sensor of the present invention includes a voltage amplifier

Figure 112015095832265-pat00035
Error due to input offset voltage and voltage amplifier
Figure 112015095832265-pat00036
Delay from output
Figure 112015095832265-pat00037
For compensation of < RTI ID = 0.0 >
Figure 112015095832265-pat00038
A comparator for measuring an input offset of the output value and a delay error of the output value
Figure 112015095832265-pat00039
And a comparator
Figure 112015095832265-pat00040
Voltage amplifier < RTI ID = 0.0 >
Figure 112015095832265-pat00041
The bias voltage
Figure 112015095832265-pat00042
And an up-down charge pump that adjusts the charge pump.

FIG. 6 is a cross-

Figure 112015095832265-pat00043
And an up / down charge pump.

FIG. 6 is a specific circuit diagram of the red box of FIG. 5,

Figure 112015095832265-pat00044
A source terminal is connected to the voltage V DD , and a control voltage
Figure 112015095832265-pat00045
The PMOS
Figure 112015095832265-pat00046
And PMOS
Figure 112015095832265-pat00047
The source terminal is connected to the drain terminal of the control voltage
Figure 112015095832265-pat00048
The PMOS
Figure 112015095832265-pat00049
And PMOS
Figure 112015095832265-pat00050
The source terminal is connected to the drain terminal of the transistor
Figure 112015095832265-pat00051
Lt; / RTI >
Figure 112015095832265-pat00052
And PMOS
Figure 112015095832265-pat00053
The source terminal is connected to the drain terminal of the transistor
Figure 112015095832265-pat00054
The PMOS
Figure 112015095832265-pat00055
And a PMOS transistor having a source terminal connected to the voltage V DD
Figure 112015095832265-pat00056
And PMOS
Figure 112015095832265-pat00057
The source terminal of which is connected to the drain terminal of the PMOS
Figure 112015095832265-pat00058
And PMOS
Figure 112015095832265-pat00059
The drain terminal of which is connected to the drain terminal of the NMOS
Figure 112015095832265-pat00060
And an NMOS
Figure 112015095832265-pat00061
And a PMOS
Figure 112015095832265-pat00062
The drain terminal of which is connected to the drain terminal of the NMOS
Figure 112015095832265-pat00063
A source terminal connected to the voltage V DD , and a gate terminal connected to the PMOS
Figure 112015095832265-pat00064
And the gate terminal of the PMOS
Figure 112015095832265-pat00065
PMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00066
And PMOS
Figure 112015095832265-pat00067
The source terminal is connected to the drain terminal of the PMOS
Figure 112015095832265-pat00068
And the gate terminal of the PMOS
Figure 112015095832265-pat00069
PMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00070
And PMOS
Figure 112015095832265-pat00071
The drain terminal is connected to the drain terminal of the NMOS
Figure 112015095832265-pat00072
NMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00073
And an NMOS
Figure 112015095832265-pat00074
And a PMOS
Figure 112015095832265-pat00075
The source terminal is grounded and the gate terminal is connected to the NMOS
Figure 112015095832265-pat00076
NMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00077
.

Voltage amplifier

Figure 112015095832265-pat00078
NMOS
Figure 112015095832265-pat00079
And the NMOS
Figure 112015095832265-pat00080
The source terminal of which is connected to the drain terminal and the source terminal of which is grounded
Figure 112015095832265-pat00081
And NMOS
Figure 112015095832265-pat00082
Which is connected to the gate terminal of the capacitor
Figure 112015095832265-pat00083
Respectively.

The up / down charge pump includes NMOS

Figure 112015095832265-pat00084
Lt; RTI ID = 0.0 >
Figure 112015095832265-pat00085
,
Figure 112015095832265-pat00086
A voltage V DD , an applying end and a switch
Figure 112015095832265-pat00087
A current source
Figure 112015095832265-pat00088
And switch
Figure 112015095832265-pat00089
And a current source
Figure 112015095832265-pat00090
Lt; / RTI >

Meanwhile,

Figure 112015095832265-pat00091
Will be described in detail with reference to FIG.

In the current sensor of the present invention configured as described above,

Figure 112015095832265-pat00092
The input offset voltage of PMOS
Figure 112015095832265-pat00093
and
Figure 112015095832265-pat00094
The PMOS is generated due to the mismatch in the process of the PMOS
Figure 112015095832265-pat00095
and
Figure 112015095832265-pat00096
Current
Figure 112015095832265-pat00097
An error is generated as much as the input offset. Accordingly, the voltage amplifier of the current sensor of the present invention is a PMOS
Figure 112015095832265-pat00098
and
Figure 112015095832265-pat00099
To control the current generated by the input offset of
Figure 112015095832265-pat00100
,
Figure 112015095832265-pat00101
,
Figure 112015095832265-pat00102
Is divided by 1: (1-N): N, and NMOS
Figure 112015095832265-pat00103
Lt; / RTI >
Figure 112015095832265-pat00104
To eliminate the current error caused by the input offset.

Comparator

Figure 112015095832265-pat00105
The input offset voltage is stored in the capacitor through the input offset storage technique described with reference to FIG. 4,
Figure 112015095832265-pat00106
It removes its own input offset.

Power NMOS

Figure 112015095832265-pat00107
Lt; RTI ID = 0.0 > EN signal < / RTI >
Figure 112015095832265-pat00108
The node voltage
Figure 112015095832265-pat00109
And GNDP. Node voltage
Figure 112015095832265-pat00110
Is greater than GNDP, the comparator output (DN) is set to '1' to supply the current from the up / down charge pump
Figure 112015095832265-pat00111
.
Figure 112015095832265-pat00112
The current
Figure 112015095832265-pat00113
And the output I_zero of the voltage amplifier is generated quickly.

On the other hand,

Figure 112015095832265-pat00114
Is lower than the GNDP voltage, the comparator outputs the output (DN) as '0'. If DN is '0', the down charge pump operates
Figure 112015095832265-pat00115
.
Figure 112015095832265-pat00116
When the value of
Figure 112015095832265-pat00117
And the output I_zero of the voltage amplifier is generated later.

7 is a conceptual diagram for storing the input offset of the comparator of the present invention.

Referring to FIG. 7,

Figure 112015095832265-pat00118
,
Figure 112015095832265-pat00119
Is connected to ground,
Figure 112015095832265-pat00120
,
Figure 112015095832265-pat00121
Is connected to the output terminal. When the EN signal is input to the comparator, a unit gain feedback loop is formed. If there is an input offset, an output is generated in the comparator,
Figure 112015095832265-pat00122
,
Figure 112015095832265-pat00123
.

8 to 10 are operation waveform diagrams illustrating a voltage amplifier error of the present invention measured by a comparator.

Specifically, Power NMOS

Figure 112015095832265-pat00124
The EN signal causes the comparator < RTI ID = 0.0 >
Figure 112015095832265-pat00125
And Fig.

Referring to Figure 8,

Figure 112015095832265-pat00126
A capacitor connected in series with its input terminal,
Figure 112015095832265-pat00127
,
Figure 112015095832265-pat00128
And a capacitor
Figure 112015095832265-pat00129
Node voltage
Figure 112015095832265-pat00130
Switch
Figure 112015095832265-pat00131
And a capacitor
Figure 112015095832265-pat00132
Switches to which GNDP is applied or grounded
Figure 112015095832265-pat00133
A switch connected to input / output through unity-gain feedback,
Figure 112015095832265-pat00134
And
Figure 112015095832265-pat00135
And a switch
Figure 112015095832265-pat00136
Or switch
Figure 112015095832265-pat00137
And a switch formed between the up / down charge pump
Figure 112015095832265-pat00138
.

Power NMOS

Figure 112015095832265-pat00139
The switch < RTI ID = 0.0 >
Figure 112015095832265-pat00140
and
Figure 112015095832265-pat00141
Power NMOS
Figure 112015095832265-pat00142
It is connected to both ends. The comparator
Figure 112015095832265-pat00143
The node voltage
Figure 112015095832265-pat00144
And the GNDP voltage. Node voltage
Figure 112015095832265-pat00145
Is greater than the GNDP voltage, DN is '1' and the node voltage
Figure 112015095832265-pat00146
Is lower than the GNDP voltage, the DN is output as '0'.

In FIG. 9, when the DN signal '1' is inputted by the up / down charge pump, the up charge pump is turned on,

Figure 112015095832265-pat00147
To
Figure 112015095832265-pat00148
. At this time,
Figure 112015095832265-pat00149
Reference voltage
Figure 112015095832265-pat00150
(
Figure 112015095832265-pat00151
) To increase the voltage.

On the other hand, in FIG. 10, when the DN signal is '0', the down charge pump is turned on

Figure 112015095832265-pat00152
To
Figure 112015095832265-pat00153
To discharge
Figure 112015095832265-pat00154
Lt; / RTI > By adjusting the bias voltage of the voltage amplifier in this way, the error due to the input offset of the voltage amplifier and the error due to the output delay are compensated to improve the accuracy of the output of the voltage amplifier.

11 and 12 are operation waveform diagrams of a comparator and an up / down charge pump according to the voltage amplifier error of the present invention.

11 shows a power NMOS

Figure 112015095832265-pat00155
When this is turned off quickly,
Figure 112015095832265-pat00156
And the operation waveform of the up / down charge pump. Voltage amplifier
Figure 112015095832265-pat00157
Power NMOS by error
Figure 112015095832265-pat00158
Is turned off quickly by the remaining current of the inductor,
Figure 112015095832265-pat00159
Becomes a negative voltage. The comparator
Figure 112015095832265-pat00160
The node voltage < RTI ID = 0.0 >
Figure 112015095832265-pat00161
And GNDP are compared, and the DN signal is output as '0'. The DN signal is input to the up / down charge pump to turn on the down charge pump
Figure 112015095832265-pat00162
-
Figure 112015095832265-pat00163
. Voltage amplifier
Figure 112015095832265-pat00164
By delaying the output signal I_zero of the next period,
Figure 112015095832265-pat00165
Correct the current error by increasing the waveform.

12 shows a power NMOS

Figure 112015095832265-pat00166
When this is turned off slowly,
Figure 112015095832265-pat00167
And the operation waveform of the up / down charge pump. Power NMOS due to voltage amplifier error
Figure 112015095832265-pat00168
Is turned off slowly due to the residual current of the inductor,
Figure 112015095832265-pat00169
Becomes a positive voltage. The comparator
Figure 112015095832265-pat00170
The node voltage < RTI ID = 0.0 >
Figure 112015095832265-pat00171
And GNDP are compared, and the DN signal is outputted as '1'. The DN signal is input to the up / down charge pump to turn the up charge pump on
Figure 112015095832265-pat00172
+
Figure 112015095832265-pat00173
. By generating the output signal I_zero of the voltage amplifier as opposed to when the DN signal is '0'
Figure 112015095832265-pat00174
Reduce the waveform to compensate for the current error.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

Power switch:

Figure 112015095832265-pat00175

Voltage amplifier:
Figure 112015095832265-pat00176

Comparator:
Figure 112015095832265-pat00177

Claims (6)

An I_zero pulse generator for controlling the power switch in response to an I_zero signal output from a voltage amplifier having both ends of a power switch connected to an input terminal;
A comparator connected to both ends of the power switch for measuring an input offset voltage and a delay error of an output value; And
And an up-down charge pump for adjusting a bias voltage of the voltage amplifier from an output of the comparator to adjust a generation timing of the I_zero signal. Compensated current sensor.
The method according to claim 1,
Wherein the comparator compensates for an input offset and an output delay of a voltage amplifier operating when the power switch is turned off.
The method according to claim 1,
The input offset voltage of the comparator
A capacitor connected in series with the input terminal by connecting input / output with unity-gain feedback
Figure 112015095832265-pat00178
,
Figure 112015095832265-pat00179
A current sensor compensating an input offset and an output delay of a voltage amplifier to be removed using a technique of storing an input offset voltage.
The method of claim 3,
The comparator comprising:
A capacitor connected in series with its input terminal
Figure 112015095832265-pat00180
,
Figure 112015095832265-pat00181
;
The capacitor
Figure 112015095832265-pat00182
Node voltage
Figure 112015095832265-pat00183
Switch
Figure 112015095832265-pat00184
And a capacitor
Figure 112015095832265-pat00185
Switches to which GNDP is applied or grounded
Figure 112015095832265-pat00186
;
A switch connected to the input / output by unit gain feedback
Figure 112015095832265-pat00187
And
Figure 112015095832265-pat00188
; And
The switch
Figure 112015095832265-pat00189
Or switch
Figure 112015095832265-pat00190
And a switch formed between the up / down charge pump
Figure 112015095832265-pat00191
And the output offset of the voltage amplifier.
The method according to claim 1,
The up / down charge pump comprises:
The bias voltage is raised by the operation of the up charge pump to generate the I_zero signal quickly and the bias voltage drops due to the operation of the down charge pump so that the input offset and the output delay of the voltage amplifier in which the I_zero signal is generated later Compensated current sensor.
The method according to claim 1,
Wherein the voltage amplifier comprises:
A source terminal is connected to the voltage V DD and a control voltage
Figure 112015095832265-pat00192
The PMOS
Figure 112015095832265-pat00193
and,
PMOS
Figure 112015095832265-pat00194
The source terminal is connected to the drain terminal of the control voltage
Figure 112015095832265-pat00195
The PMOS
Figure 112015095832265-pat00196
Wow,
PMOS
Figure 112015095832265-pat00197
The source terminal is connected to the drain terminal of the transistor
Figure 112015095832265-pat00198
Lt; / RTI >
Figure 112015095832265-pat00199
and,
PMOS
Figure 112015095832265-pat00200
The source terminal is connected to the drain terminal of the transistor
Figure 112015095832265-pat00201
The PMOS
Figure 112015095832265-pat00202
Wow,

A PMOS transistor whose source terminal is connected to the voltage V DD
Figure 112015095832265-pat00203
Wow,
PMOS
Figure 112015095832265-pat00204
The source terminal of which is connected to the drain terminal of the PMOS
Figure 112015095832265-pat00205
and,
PMOS
Figure 112015095832265-pat00206
The drain terminal of which is connected to the drain terminal of the NMOS
Figure 112015095832265-pat00207
and,
NMOS
Figure 112015095832265-pat00208
And a PMOS
Figure 112015095832265-pat00209
The drain terminal of which is connected to the drain terminal of the NMOS
Figure 112015095832265-pat00210
Wow,

The source terminal is connected to the voltage V DD and the gate terminal is connected to the PMOS
Figure 112015095832265-pat00211
And the gate terminal of the PMOS
Figure 112015095832265-pat00212
PMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00213
Wow,
PMOS
Figure 112015095832265-pat00214
The source terminal is connected to the drain terminal of the PMOS
Figure 112015095832265-pat00215
PMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00216
and,
PMOS
Figure 112015095832265-pat00217
The drain terminal is connected to the drain terminal of the NMOS
Figure 112015095832265-pat00218
NMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00219
and,
NMOS
Figure 112015095832265-pat00220
And a PMOS
Figure 112015095832265-pat00221
The source terminal is grounded and the gate terminal is connected to the NMOS
Figure 112015095832265-pat00222
NMOS < RTI ID = 0.0 >
Figure 112015095832265-pat00223
/ RTI >

The voltage amplifier includes an NMOS
Figure 112015095832265-pat00224
And the NMOS
Figure 112015095832265-pat00225
The source terminal of which is connected to the drain terminal and the source terminal of which is grounded
Figure 112015095832265-pat00226
Wow,
NMOS
Figure 112015095832265-pat00227
Which is connected to the gate terminal of the capacitor
Figure 112015095832265-pat00228
A current sensor compensating for the input offset and the output delay of the voltage amplifier.
KR1020150139364A 2015-10-02 2015-10-02 Current sensor for compensating input offset and output delay of voltage amplifier KR101677674B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101871491B1 (en) 2017-03-16 2018-06-27 한양대학교 산학협력단 Amplifier circuit and driving method thereof
KR101996963B1 (en) * 2017-12-29 2019-07-05 충북대학교 산학협력단 Apparatus of Zero Current Sensor Operating at Wide Output Voltages Range
WO2020068226A1 (en) * 2018-09-27 2020-04-02 Intel Corporation Self-tuning zero current detection circuit

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Publication number Priority date Publication date Assignee Title
JP2004096816A (en) * 2002-08-29 2004-03-25 Matsushita Electric Ind Co Ltd Multi-output dc-dc converter
KR20120129876A (en) 2010-02-01 2012-11-28 마이크로칩 테크놀로지 인코포레이티드 Effective current sensing for high voltage switching regulators
KR101350995B1 (en) * 2012-12-18 2014-01-15 충북대학교 산학협력단 Single inductor multiple output boost converter using current control scheme
KR101362474B1 (en) * 2013-03-04 2014-02-14 충북대학교 산학협력단 Cmos subbandgap reference

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Publication number Priority date Publication date Assignee Title
JP2004096816A (en) * 2002-08-29 2004-03-25 Matsushita Electric Ind Co Ltd Multi-output dc-dc converter
KR20120129876A (en) 2010-02-01 2012-11-28 마이크로칩 테크놀로지 인코포레이티드 Effective current sensing for high voltage switching regulators
KR101350995B1 (en) * 2012-12-18 2014-01-15 충북대학교 산학협력단 Single inductor multiple output boost converter using current control scheme
KR101362474B1 (en) * 2013-03-04 2014-02-14 충북대학교 산학협력단 Cmos subbandgap reference

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101871491B1 (en) 2017-03-16 2018-06-27 한양대학교 산학협력단 Amplifier circuit and driving method thereof
KR101996963B1 (en) * 2017-12-29 2019-07-05 충북대학교 산학협력단 Apparatus of Zero Current Sensor Operating at Wide Output Voltages Range
WO2020068226A1 (en) * 2018-09-27 2020-04-02 Intel Corporation Self-tuning zero current detection circuit
US10910946B2 (en) 2018-09-27 2021-02-02 Intel Corporation Self-tuning zero current detection circuit

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