KR101661851B1 - Static random access memory using thermal assisted-magnetic tunnel junction cell and manufacturing method thereof - Google Patents

Static random access memory using thermal assisted-magnetic tunnel junction cell and manufacturing method thereof Download PDF

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Publication number
KR101661851B1
KR101661851B1 KR1020150056457A KR20150056457A KR101661851B1 KR 101661851 B1 KR101661851 B1 KR 101661851B1 KR 1020150056457 A KR1020150056457 A KR 1020150056457A KR 20150056457 A KR20150056457 A KR 20150056457A KR 101661851 B1 KR101661851 B1 KR 101661851B1
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KR
South Korea
Prior art keywords
transistors
sram
mtj cells
bit lines
mtj
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KR1020150056457A
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Korean (ko)
Inventor
송윤흡
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한양대학교 산학협력단
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    • H01L27/11—
    • H01L43/08—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]

Abstract

A static random access memory (SRAM) includes two transistors disposed on one side of a substrate, a word line and a source line formed on the two transistors and connected to the two transistors, Two TA-MTJ cells (Thermal Assisted-Magnetic Tunnel Junction) cells connected to the two transistors, and two TA-MTJ cells formed on the two TA-MTJ cells so as to be orthogonal to the word lines, Lt; RTI ID = 0.0 > MTJ < / RTI >

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an SRAM using a TA-MTJ cell,

The present invention relates to a SRAM (Static Random Access Memory) using a TA-MTJ (Thermal Assisted-Magnetic Tunnel Junction) cell and a manufacturing method thereof, and more particularly to a technique of manufacturing an SRAM including a transistor and a TA- It is about.

The TA-MTJ cell including the hard-pinned layer and the soft pinned layer and the insulating layer formed of the anti-ferromagnetic (AF) material has a Neel temperature (Neel Temperature) applied to the hard pinned layer and the soft pinned layer Data is recorded on the basis of different resistance values corresponding to the changed magnetization state by changing the magnetization directions of the hard pinned layer and the soft pinned layer differently based on the column.

In the TA-MTJ cell, the AF material and the structure for forming each of the hard pinned layer and the soft pinned layer are set to be different from each other, so that the magnetization direction of the Nehl temperature can be changed differently.

When a conventional MTJ cell is designed to have a small size, a very high driving current is required. However, even when the size of the TA-MTJ cell described above is designed to be small, since the MTJ cell requires a relatively low driving current as compared with the conventional MTJ cell, it can be used in a reduced SRAM.

Embodiments of the present invention provide a reduced-size SRAM and a fabrication method thereof by having a structure including two transistors and two TA-MTJ cells.

A static random access memory (SRAM) according to an embodiment of the present invention includes two transistors disposed on one side of a substrate; A word line and a source line formed on the two transistors and connected to the two transistors; Two TA-MTJ (Thermal Assisted-Magnetic Tunnel Junction) cells formed on the two transistors and connected to the two transistors, respectively; And two bit lines formed on top of the two TA-MTJ cells so as to be orthogonal to the word line and connected to the two TA-MTJ cells, respectively.

Each of the two TA-MTJ cells may be generated on top of a drain contact included in each of the two transistors.

The static random access memory (SRAM) may further include a plate line formed between each of the two TA-MTJ cells and a drain contact included in each of the two transistors.

The plate line may be formed in each of the drain contacts included in each of the two transistors, or may be formed to be shared by a drain contact included in each of the two transistors.

The static random access memory (SRAM) includes a plurality of bit lines and a plurality of bit lines, each of the bit lines being connected to each of the two TA-MTJ cells, And an insulating layer disposed on the insulating layer.

The static random access memory (SRAM) may further include two lighting switching lines formed on the two bit lines so as to be parallel to the two bit lines.

The static random access memory (SRAM) may further include an insulation layer disposed between the two lighting switching lines and the two bit lines.

Each of the word line and the source line may be formed to be shared by the two transistors.

The word line may be formed on the gate included in each of the two transistors.

The source line may be formed on the source contact included in each of the two transistors.

A method of fabricating a static random access memory (SRAM) according to an embodiment of the present invention includes: disposing two transistors on one side of a substrate; Forming a word line and a source line on top of the two transistors to be connected to the two transistors; Generating two TA-MTJ (Thermal Assisted-Magnetic Tunnel Junction) cells on top of the two transistors to be connected to each of the two transistors; And forming two bit lines orthogonal to the word line and on top of the two TA-MTJ cells to be connected to each of the two TA-MTJ cells.

The generating of the two TA-MTJ cells may comprise generating the two TA-MTJ cells on top of a drain contact included in each of the two transistors.

Wherein the step of generating the two TA-MTJ cells on top of a drain contact included in each of the two transistors includes forming a first contact between the respective two TA-MTJ cells and a drain contact included in each of the two transistors, And forming the second electrode layer.

The method of fabricating the SRAM may further include forming two lighting switching lines on the two bit lines so as to be parallel to the two bit lines.

Embodiments of the present invention can provide a reduced-size SRAM and a fabrication method thereof by having a structure including two transistors and two TA-MTJ cells.

1 is a circuit diagram showing an SRAM according to an embodiment of the present invention.
2 is a top view illustrating an SRAM according to an embodiment of the present invention.
3 is a side view of an SRAM according to an embodiment of the present invention.
4A to 4E illustrate a method of fabricating an SRAM according to an embodiment of the present invention.
5 is a flowchart illustrating a method of fabricating an SRAM according to an embodiment of the present invention.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. In addition, the same reference numerals shown in the drawings denote the same members.

Also, terminologies used herein are terms used to properly represent preferred embodiments of the present invention, which may vary depending on the user, intent of the operator, or custom in the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

1 is a circuit diagram showing an SRAM according to an embodiment of the present invention.

Referring to FIG. 1, an SRAM according to an embodiment of the present invention includes two transistors 110, a word line and a source line (not shown in the figure) connected to two transistors 110, two TA -MTJ cells 120 - consisting of a hard pinned layer P (Hard), an insulating layer barrier and a soft pinned layer P (Soft) - and two bit lines (not shown in the figure).

An SRAM having such a structure forms a word line and a source line and two bit lines in consideration of two transistors and two TA-MTJ cells, including two transistors and two TA-MTJ cells, Compared with conventional SRAM, its size can be greatly reduced to 40% or less. A detailed description thereof will be given below.

2 is a top view illustrating an SRAM according to an embodiment of the present invention.

2, an SRAM according to an embodiment of the present invention includes two transistors 220 disposed on one side of a substrate 210, a word line 230 and a source line 240, two TA-MTJs Cells 250 and two bit lines 260. [

Each of the two transistors 220 may be formed on one side of the substrate 210 and formed to include a drain contact 221, a gate 222 and a source contact 223.

The word line 230 and the source line 240 are created on top of the two transistors 220 and are connected to the two transistors 220, respectively. Hereinafter, the connection means that the connection is electrically connected.

Specifically, the word line 230 is formed on top of the gate 222 included in each of the two transistors 220, so that it can be shared by the two transistors 220. Similarly, the source line 240 may be formed on top of the source contact 223 included in each of the two transistors 220, thereby being shared by the two transistors 220.

Two TA-MTJ cells 250 are created on top of two transistors 220 and are coupled to two transistors 220, respectively. For example, each of the two TA-MTJ cells 250 can be created on top of the drain contact 221 included in each of the two transistors 220.

At this time, each of the two TA-MTJ cells 250 is not directly generated on the drain contact 221 included in each of the two transistors 220, but is included in each of the two transistors 220 May be formed on the top of the plate line 224 formed on the top of the drain contact 221.

Here, the plate line 224 is illustrated as being formed on the upper portion of the drain contact 221 included in each of the two transistors 220 in the drawing, but is not limited thereto, And may be formed as one long component in the horizontal direction so as to be shared by the drain contacts 221 included in each of the components.

Two bit lines 260 are formed on top of two TA-MTJ cells 250 so as to be orthogonal to the word lines 230 and are connected to two TA-MTJ cells 250, respectively.

At this time, although not shown in the figure, between two bit lines 260 and two TA-MTJ cells 250, each of two bit lines 260 is connected to two TA-MTJ cells 250 The insulating layer may be disposed on the remaining portion except for a portion connected to the gate electrode. Such an insulating layer may be disposed between two write switching lines 270 and two bit lines 260, which will be described later. A detailed description thereof will be described with reference to Fig.

Two lighting switching lines 270 may be formed on top of the two bit lines 260 to be parallel to the two bit lines 260.

The SRAM having such a structure forms the word line 230 and the source line 240 in consideration of the two transistors 220 and the two TA-MTJ cells 250, By forming the two bit lines 260, the size of the SRAM can be greatly reduced compared to the conventional SRAM.

3 is a side view of an SRAM according to an embodiment of the present invention.

Referring to FIG. 3, an SRAM according to an embodiment of the present invention includes two transistors 310, a word line 320 and a source line 330, two TA- MTJ cells 340, and two bit lines 350. [

The SRAM also includes two plate lines 360 formed between the two TA-MTJ cells 340 and the drain contact 311 included in each of the two transistors, and two bit lines 350 parallel to the two bit lines 350 And two lighting switching lines 370 formed on top of the bit lines 350.

Since the source contact 312 and the drain contact 311 included in each of the two transistors 310 can be formed to have the same height as the source contact 312 and the drain contact 311 included in each of the two transistors 310, And the plate line 360 formed on the drain contact 311 included in each of the two transistors may be formed at the same height. Thus, the source line 330 and the plate line 360 can be formed through a single process. A detailed description thereof will be described with reference to FIG.

At this time, since the gate 313 included in each of the two transistors 310 can be formed to have a different height from the source contact 312 and the drain contact 311, The word line 320 formed on the upper portion of the gate 313 included may be formed at a different height from the source line 330 and the plate line 360.

Since the SRAM having such a structure forms two lighting switching lines 370 on top of two bit lines 350, two bit lines 350 in the two lighting switching lines 370, MTJ cells 340 through the two bit lines 350. In this case, the writing operation can be performed in the two TA-MTJ cells 340 through the two bit lines 350. FIG.

Here, an insulating layer 380 may be disposed between the two lighting switching lines 370 and the two bit lines 350, and two bit lines 350 and two TA-MTJ cells The insulating layer 380 may be disposed between the first and second electrodes 340 and 340. At this time the insulating layer 380 disposed between the two bit lines 350 and the two TA-MTJ cells 340 is such that each of the two bit lines 350 is connected to two TA-MTJ cells 340, And may be disposed in other portions except for a portion connected to each of them.

Hereinafter, an SRAM fabrication method according to an embodiment of the present invention described with reference to FIGS. 4A to 4E and 5 is performed by an SRAM fabrication apparatus.

4A to 4E illustrate a method of fabricating an SRAM according to an embodiment of the present invention.

Referring to FIG. 4A, the SRAM fabrication apparatus includes two transistors 420 on one side of a substrate 410. Specifically, the SRAM according to an embodiment of the present invention includes an insulating layer 411 between the drain contact 421, the gate 422, and the source contact 423 included in each of the two transistors 420 The SRAM fabrication apparatus has an insulating layer 411 formed on the substrate 410 and then the drain contact 421, the gate 422 and the source contact 423 of the insulating layer 411 are disposed The gate 422 and the source contact 423 can be formed by etching the region and implanting the metal in the etched region.

4B, the SRAM fabrication apparatus forms a word line 430 and a source line 440 on top of the two transistors 420 so as to be connected to the two transistors 420. At this time, the SRAM fabrication apparatus includes a region 422 in which the word line 430 and the source line 440 are formed (the gate 422 and the source contact 423 included in each of the two transistors 420) And the source line 440 can be formed by implanting a metal into the etched region.

In addition, the SRAM fabrication apparatus may form a plate line 460 on the drain contact 421 included in each of the two transistors 420. Here, since the plate line 460 and the source line 440 are formed at the same height, the metal can be implanted after the corresponding region is etched in one step.

4C, the SRAM fabrication apparatus creates two TA-MTJ cells 450 on top of the two transistors 420 to be coupled with two transistors 420. [ Specifically, the SRAM fabrication apparatus etches a region where two TA-MTJ cells 450 are formed in the insulating layer 411, and then arranges two TA-MTJ cells 450 in the etched region, And may generate TA-MTJ cells 450. At this time, the SRAM fabrication apparatus can generate two TA-MTJ cells 450 on the plate line 460 formed on the drain contact 421 included in each of the two transistors 420.

Referring to FIG. 4D, the SRAM fabrication apparatus includes two bit lines 450a and 450b formed on top of two TA-MTJ cells 450 so as to be orthogonal to the word line 430 and connected to each of the two TA-MTJ cells 450, (470).

4E, the SRAM fabrication apparatus includes an insulating layer 411 disposed on top of two bit lines 470, and two bit lines (not shown) parallel to two bit lines 470 470 may be formed on top of the light switching lines 480.

5 is a flowchart illustrating a method of fabricating an SRAM according to an embodiment of the present invention.

Referring to FIG. 5, an SRAM fabrication apparatus according to an exemplary embodiment of the present invention includes two transistors 510 disposed on one side of a substrate.

Next, the SRAM fabrication apparatus forms a word line and a source line on top of the two transistors to be connected with two transistors (520). Specifically, the SRAM fabrication apparatus can form a word line on top of the gate included in each of the two transistors, and form a source line on top of the source contact included in each of the two transistors.

Here, each of the word line and the source line may be formed to be shared by two transistors.

Next, the SRAM fabrication apparatus generates 5 TA-MTJ (Thermal Assisted-Magnetic Tunnel Junction) cells on top of the two transistors to be connected to each of the two transistors (530). Specifically, the SRAM fabrication apparatus can create two TA-MTJ cells on top of the drain contacts included in each of the two transistors.

At this time, in the process of generating two TA-MTJ cells on the drain contact included in each of the two transistors, the SRAM fabrication apparatus generates the drain contact included in each of the two TA-MTJ cells and the two transistors, A plate line can be formed.

Here, the plate line may be formed to each of the drain contacts included in each of the two transistors, or may be formed to be shared by the drain contacts included in each of the two transistors.

Thereafter, the SRAM fabrication apparatus forms 5 bit lines on top of two TA-MTJ cells so as to be orthogonal to the word lines and connected to each of the two TA-MTJ cells (540). At this time, the SRAM fabrication apparatus arranges the insulating layer between the two bit lines and the two TA-MTJ cells except for a part where each of the two bit lines is connected to each of the two TA-MTJ cells .

In addition, the SRAM fabrication apparatus may form two lighting switching lines on top of two bit lines so as to be parallel to the two bit lines (550). Here, the SRAM fabrication apparatus can arrange an insulating layer between two lighting switching lines and two bit lines.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (14)

Two transistors disposed on one side of the substrate;
A word line and a source line formed on the two transistors and connected to the two transistors;
Two TA-MTJ (Thermal Assisted-Magnetic Tunnel Junction) cells formed on the two transistors and connected to the two transistors, respectively; And
MTJ cells, each of which is formed on top of the two TA-MTJ cells so as to be orthogonal to the word lines,
(Static Random Access Memory). The method according to claim 1,
Each of the two TA-MTJ cells
(SRAM) formed on top of a drain contact included in each of the two transistors. 3. The method of claim 2,
MTJ cells and the drain contact included in each of the two transistors,
(Static Random Access Memory). The method of claim 3,
The plate line
Wherein the drain contact is formed in each of the drain contacts included in each of the two transistors or is formed to be shared by a drain contact included in each of the two transistors. The method according to claim 1,
An insulating layer disposed between the two bit lines and the two TA-MTJ cells,
(Static Random Access Memory). The method according to claim 1,
And two write switching lines formed on the two bit lines so as to be parallel to the two bit lines.
(Static Random Access Memory). The method according to claim 6,
An insulating layer disposed between the two lighting switching lines and the two bit lines,
(Static Random Access Memory). The method according to claim 1,
Each of the word line and the source line
(SRAM) formed to be shared by the two transistors. The method according to claim 1,
The word line
(SRAM) formed on top of a gate included in each of the two transistors. The method according to claim 1,
The source line
(SRAM) formed on top of a source contact included in each of the two transistors. Disposing two transistors on one side of the substrate;
Forming a word line and a source line on top of the two transistors to be connected to the two transistors;
Generating two TA-MTJ (Thermal Assisted-Magnetic Tunnel Junction) cells on top of the two transistors to be connected to each of the two transistors; And
Forming two bit lines on top of the two TA-MTJ cells orthogonal to the word line and connected to each of the two TA-MTJ cells,
(SRAM). 12. The method of claim 11,
The step of generating the two TA-MTJ cells
Generating the two TA-MTJ cells on the drain contact included in each of the two transistors
(SRAM). 13. The method of claim 12,
The step of generating the two TA-MTJ cells on top of the drain contact included in each of the two transistors
Forming a plate line between each of the two TA-MTJ cells and a drain contact included in each of the two transistors
(SRAM) < / RTI > 12. The method of claim 11,
Forming two lighting switching lines on top of the two bit lines so as to be parallel to the two bit lines
(SRAM) < / RTI >
KR1020150056457A 2015-04-22 2015-04-22 Static random access memory using thermal assisted-magnetic tunnel junction cell and manufacturing method thereof KR101661851B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020046037A (en) * 2000-12-12 2002-06-20 박종섭 A method for forming a semiconductor device
KR20030034500A (en) * 2001-10-23 2003-05-09 주식회사 하이닉스반도체 Magnetic random access memory
WO2009063225A1 (en) * 2007-11-16 2009-05-22 Delaval Holding Ab Apparatus and method for positioning a teat cup
US7881098B2 (en) * 2008-08-26 2011-02-01 Seagate Technology Llc Memory with separate read and write paths

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020046037A (en) * 2000-12-12 2002-06-20 박종섭 A method for forming a semiconductor device
KR20030034500A (en) * 2001-10-23 2003-05-09 주식회사 하이닉스반도체 Magnetic random access memory
WO2009063225A1 (en) * 2007-11-16 2009-05-22 Delaval Holding Ab Apparatus and method for positioning a teat cup
US7881098B2 (en) * 2008-08-26 2011-02-01 Seagate Technology Llc Memory with separate read and write paths

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