KR101654135B1 - Resistive memory device and method for operating thereof - Google Patents

Resistive memory device and method for operating thereof Download PDF

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KR101654135B1
KR101654135B1 KR1020150148220A KR20150148220A KR101654135B1 KR 101654135 B1 KR101654135 B1 KR 101654135B1 KR 1020150148220 A KR1020150148220 A KR 1020150148220A KR 20150148220 A KR20150148220 A KR 20150148220A KR 101654135 B1 KR101654135 B1 KR 101654135B1
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South Korea
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voltage
power supply
supply voltage
data line
multiplying
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KR1020150148220A
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Korean (ko)
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신형순
선우경
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이화여자대학교 산학협력단
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits

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Abstract

According to the present invention, a resistive memory device comprises: a memory element having a crossbar array structure; a voltage supply unit supplying voltage to a word line and a bit line of the memory element; and a control unit setting a supply voltage of the voltage supply unit. At this time, the control unit sets to apply 0V of voltage to a word line of a selected cell of the memory element, and sets to apply a first voltage to the rest of word lines, and sets to apply source voltage to a bit line of a selected cell, and sets to apply a second voltage to the rest of bit lines, wherein a sum of the first voltage and the second voltage is same as a sum of the source voltage and the control unit set the value to be different from each other.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a resistive memory device,

The present invention relates to a resistive memory device and a driving method thereof.

Recently, various kinds of resistive memories have been actively studied.

The resistive memory utilizes the phenomenon of switching between two stable states by an external applied voltage. Particularly, studies are being made on a memory of a crossbar structure in which bit lines and word lines are arranged perpendicular to each other, and resistive elements are arranged at the intersections of the bit lines and the word lines.

In this memory structure, a power supply voltage (Vdd) is applied to a bit line of a selected cell, a voltage of 0 V is applied to a word line of a selected cell, and a half power supply voltage is applied to a word line and a bit line of the remaining cells The method is known.

According to such a driving method, a power supply voltage is applied between a word line and a bit line of a selected cell, and a 1/2 power supply voltage or a voltage of 0 V is applied between the word line and the bit line of the remaining cells. Therefore, The high voltage can be controlled to be applied.

However, according to this method, the power consumption by the unselected cells can be increased as much as the 1/2 power supply voltage is applied to the non-selected cells as a whole. In particular, as the array of memory devices becomes larger, such power consumption increases.

Korean Patent Publication No. 10-2013-0139217 (entitled " Write and erase method for resistive memory device ") discloses a method for programming a two-terminal resistive memory device, Applying a bias voltage to the first electrode; Measuring a current flowing through the cell; And stopping the application of the bias voltage when the measured current is greater than or equal to the predetermined value.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a resistive memory device capable of varying a voltage applied to a resistive memory device according to a driving mode of a resistive memory device, The purpose is to provide.

According to a first aspect of the present invention, there is provided a method of driving a resistive memory device including the steps of: (a) setting a voltage of 0V to be applied to a first data line of a selected cell; Setting a first voltage to be applied to the data line; (b) setting a power supply voltage to be applied to a second data line of the selected cell and setting a second voltage to be applied to the remaining second data line; And (c) applying a voltage to each of the first data line and the second data line according to the set voltage. At this time, the sum of the first voltage and the second voltage is equal to the sum of the power supply voltages, the values are different from each other, and the first data line and the second data line are either a word line or a bit line, respectively.

Further, a resistive memory device according to a second aspect of the present invention includes a memory device having a crossbar array structure, a voltage supply unit for supplying a voltage to the first data line and a second data line of the memory device, And a control unit. At this time, the control unit sets the voltage of 0V to be applied to the first data line of the selected cell of the memory device, sets the first voltage to be applied to the remaining first data line, And the second voltage is applied to the remaining second data lines. The sum of the first voltage and the second voltage is equal to the sum of the power supply voltages, the values are different from each other, and the first data line And the second data line are either a word line or a bit line, respectively.

According to the above-mentioned problem solving means of the present invention, by applying the optimum driving voltage in accordance with the driving mode of the resistive memory device, the power consumed in the resistive memory device can be minimized or the stability of operation can be improved.

FIGS. 1A and 1B are views for explaining a structure of a resistive memory and a method of driving a conventional resistive memory according to the present invention.
2 is a diagram illustrating a resistive memory device according to an embodiment of the present invention.
3 is a view for explaining a voltage supplying method for a resistive memory device according to an embodiment of the present invention.
4 is a view for explaining a voltage supply method for a resistive memory device according to an embodiment of the present invention.
5 is a flowchart illustrating a method of driving a resistive memory device according to an embodiment of the present invention.
FIG. 6 shows experimental results of a method of driving a resistive memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

FIGS. 1A and 1B are views for explaining a structure of a resistive memory and a method of driving a conventional resistive memory according to the present invention.

As shown in FIG. 1A, a structure in which a plurality of bit lines (BL 0 , BL 1 ) and word lines (WL 0 , WL 1 ) intersect each other and a resistive element is disposed at an intersection of a bit line and a word line . The resistance state of the resistive element has a high resistance or a low resistance state according to the voltage applied through the bit line and the word line, and data is recorded using such a characteristic. When reading the stored data, a voltage is applied to the resistive element, and the state of the resistive element is confirmed by sensing that the current flowing through the resistive element is different according to the state of the resistive element.

On the other hand, the structure of such a resistive memory is referred to as a crossbar memory structure.

When a resistive memory having such a structure is arranged in an array form, a method of driving the resistive memory will be described.

1B, a power supply voltage Vdd is applied to the bit line of the selected cell 10, a voltage of 0 V is applied to the word line of the selected cell 10, and a word line and a bit line of the remaining cell A driving method of applying 1/2 power supply voltage is known. Hereinafter, this is defined as a 1/2 power supply voltage biasing method.

According to such a driving method, the power source voltage is applied between the word line and the bit line of the selected cell 10, and the 1/2 power source voltage is applied between the word line and the bit line of the remaining cells. Therefore, Can be controlled to be applied. Thus, the program state of the selected cell can be changed.

However, according to this method, as the 1/2 power supply voltage is applied to the non-selected cells 12 and 14, the voltage loss through the voltage drop due to the current through the bit line or the word line of the corresponding cell The probability of occurrence is increased.

2 is a diagram illustrating a resistive memory device according to an embodiment of the present invention.

The resistive memory device 20 includes a resistive memory element 100, a voltage supply 200, and a controller 300.

In the resistive memory element 100, the above-described resistive memory is arranged in an array form.

The voltage supply unit 200 supplies a voltage set to the bit line and the word line of the resistive memory element 100, respectively. The voltage supply unit 200 supplies the power supply voltage Vdd and the voltage of 0V to the bit line and the word line, respectively, or supplies a voltage having a value located therebetween. At this time, the voltage to be supplied to each bit line and the word line is set by the control unit 300. Since the specific configuration of the voltage supply unit 200 uses the configuration of the conventional memory device, a detailed description thereof will be omitted.

The control unit 300 transmits a control signal for setting the voltage supply for driving the resistive memory device 100 to the voltage supply unit 200. [ The controller 300 sets the power supply voltage to be applied between the word line and the bit line of the selected cell and sets a voltage smaller than that between the word line and the bit line of the remaining cell.

For example, the control unit 300 sets a voltage of 0V to be applied to the word line of the selected cell, and sets the first voltage to be applied to the remaining word lines. Further, the power supply voltage is set to be applied to the bit line of the selected cell, and the second voltage is set to be applied to the remaining bit lines. At this time, the sum of the first voltage and the second voltage is set to be the same as the sum of the power supply voltages, but the values are different.

For example, the control unit 300 may set the first voltage by multiplying the power supply voltage by 7/12 or by multiplying the power supply voltage by 2/3. The setting of the second voltage can be determined as shown in Table 1 below.

division The first voltage The second voltage Example 1 7/12 Vdd 5/12 Vdd Example 2 2/3 Vdd 1/3 Vdd

In another embodiment, the controller 300 sets a voltage of 0V to be applied to the bit line of the selected cell and sets the first voltage to be applied to the remaining bit lines. Further, the power supply voltage is set to be applied to the word line of the selected cell, and the second voltage is set to be applied to the remaining word lines. At this time, the sum of the first voltage and the second voltage is set to be the same as the sum of the power supply voltages, but the values are different.

For example, the control unit 300 may set the first voltage by multiplying the power supply voltage by 7/12 or by multiplying the power supply voltage by 2/3. The setting of the second voltage may be determined as shown in Table 2 below.

division The first voltage The second voltage Example 1 7/12 Vdd 5/12 Vdd Example 2 2/3 Vdd 1/3 Vdd

In addition, the controller 300 may vary the first voltage and the second voltage according to the operation mode of the resistive memory device. For example, in the low power mode for minimizing power consumption, the first voltage is set to the power supply voltage multiplied by 7/12. Further, in the case of the safety mode in which the stability of the data recording is emphasized rather than the power consumption is reduced, the first voltage is set to be multiplied by 2/3 of the power supply voltage.

The control unit 300 sets the first voltage multiplied by 2/3 to the power supply voltage in the read mode for reading data from the resistive memory device, and sets the first voltage To the power supply voltage multiplied by 7/12. The background related to the setting of the first voltage will be described later in detail.

3 is a view for explaining a voltage supplying method for a resistive memory device according to an embodiment of the present invention.

3, 0 V is applied to the word line of the selected cell and a power supply voltage Vdd is applied to the bit line of the selected cell so that the voltage difference between the word line and the bit line of the selected cell becomes the power supply voltage do.

Then, a power supply voltage of 2/3 is applied to the remaining word lines, and a power supply voltage of 1/3 is applied to the remaining bit lines, so that a 1/3 power supply voltage is applied between the word lines and the bit lines of the non-selected cells. Hereinafter, this is defined as a 1/3 power supply voltage biasing method.

According to this configuration, since the voltages applied to the non-selected cells 32 and 34 are reduced to 1/3 power supply voltage, the word lines connected to the non-selected cells 32 and 34 and the bit lines connected to the non- Can be minimized. However, because the 1/3 power supply voltage is applied to the non-selected cells 36, power consumption may be caused thereby.

Unlike the drawing, a power supply voltage is applied to a word line of a selected cell, 0V is applied to a bit line of a selected cell, and a voltage difference between a word line and a bit line of the selected cell becomes a power supply voltage .

Likewise, the 1/3 power supply voltage is applied to the remaining word lines and the 2/3 power supply voltage is applied to the remaining bit lines, so that 1/3 power supply voltage is applied between the word lines and the bit lines of the non- Can be changed.

4 is a view for explaining a voltage supply method for a resistive memory device according to an embodiment of the present invention.

4, 0 V is applied to the word line of the selected cell and a power supply voltage Vdd is applied to the bit line of the selected cell so that the voltage difference between the word line and the bit line of the selected cell becomes the power supply voltage do.

Then, the 7/12 power supply voltage is applied to the remaining word lines, and the 5/12 power supply voltage is applied to the remaining bit lines. A 5/12 power supply voltage is applied between the word lines and the bit lines of the non-selected cells 42 and 44 And the 2/12 power supply voltage is applied between the word line and the bit line of the non-selected cells 46. [ Hereinafter, this is defined as a 5/12 power supply voltage biasing method.

According to this configuration, as compared with the configuration of FIG. 3, the voltage applied to the non-selected cells 46 is reduced from the 1/3 power supply voltage to the 2/12 power supply voltage, so that the power consumption can be minimized. In addition, since the voltages applied to the non-selected cells 42 and 44 are reduced to 5/12 power supply voltages, the voltage drop across the word lines and bit lines connected to the unselected cells 42 and 44, respectively, Can be minimized.

That is, compared to the configuration of FIG. 1B, the voltage drop occurring through the word line and the bit line of the selected cell can be minimized, and power consumption caused by non-selected cells can be minimized .

Unlike the drawing, a power supply voltage is applied to a word line of a selected cell, 0V is applied to a bit line of a selected cell, and a voltage difference between a word line and a bit line of the selected cell becomes a power supply voltage .

Likewise, the embodiment may be modified such that the 5/12 power supply voltage is applied to the remaining word lines and the 7/12 power supply voltage is applied to the remaining bit lines.

5 is a flowchart illustrating a method of driving a resistive memory device according to an embodiment of the present invention.

First, a voltage to be applied to a word line and a remaining word line of a selected cell is set (S510), and a voltage to be applied to a bit line and a remaining bit line of the selected cell is set (S520).

In this case, the word line voltage is first set and the bit line voltage is set first. However, this is for simplicity of explanation, the order may be changed, and the bit line voltage and the word line voltage can be set at the same time .

In the present invention, as described above, a power supply voltage which is the maximum voltage is applied between the word line and the bit line of the selected cell, and a voltage smaller than the maximum voltage is applied to the remaining cells.

For example, the power supply voltage is set to be applied to the bit line of the selected cell, and the 0V voltage is applied to the word line of the selected cell. Then, the 1/3 power supply voltage is set to be applied to the remaining bit lines, and the 2/3 power supply voltage is set to be applied to the remaining word lines. According to this configuration, a 1/3 power supply voltage is applied between the bit line and the word line of the remaining cells.

In another embodiment, the 5/12 power supply voltage is set to be applied to the remaining bit lines, and the 7/12 power supply voltage is applied to the remaining word lines. According to this configuration, a 2/12 power supply voltage or a 5/12 power supply voltage is applied between the bit line and the word line in the remaining cells.

The driving voltage is supplied to the resistive memory device in accordance with the voltage set in the preceding steps S510 and S520 (S530).

Such a driving method can also be utilized in a data write operation or a read operation to a resistive memory element.

FIG. 6 shows experimental results of a method of driving a resistive memory device according to an embodiment of the present invention.

Figure 6 (a) shows the rate at which a voltage drop (IR Drop) occurs along a bit line or word line connected to a selected cell.

As can be seen, as the first voltage decreases, the voltage drop increases. Particularly, compared with the 1/2 power source voltage biasing method, the 5/12 power source voltage biasing method or the 1/3 power source voltage It can be confirmed that the voltage drop of the biasing method becomes smaller.

6 (b) shows the power consumption generated in the resistive memory element.

As shown, it can be seen that there is no constant proportional relationship between the first voltage and the power consumption. It can be seen that the power consumption of the 5/12 power supply voltage biasing method among the various biasing methods is the smallest.

Considering both the voltage drop and the power consumption in view of these experimental results, it can be confirmed that the 5/12 power supply voltage biasing method is the most optimal condition.

In view of such characteristics, an appropriate driving voltage is variably applied according to the driving state of the resistive memory element.

That is, when low-power driving is required, the control unit 300 selects the 5/12 power source voltage biasing method.

In the safe mode, it is important to secure a sufficient margin between the voltage state and the reference voltage sensed through each cell during the reading process. To this end, it is necessary to minimize the voltage drop along the bit line or the word line Do. Therefore, when the safe mode is required, the control unit 300 selects the 1/3 power source voltage biasing method.

On the other hand, when looking at the power consumed during the read operation and the write operation, the voltage used in the write operation is larger, so that the power consumed in the write operation is larger. Therefore, the 1/3 power supply voltage biasing method is selected in the read operation and the 5/12 power supply voltage biasing method or 1/2 power supply voltage biasing method is selected in the write operation.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10, 20, 30, 40, 50: unit cell
410: gate line
411: first group gate line
413: second group gate line
420: source line
430: bit line
431: first group bit line
433: second group bit line
440, 445: magnetoresistive memory cell
441, 446: magnetic tunnel junction element
443, 448: switching element
510: gate line
511: first group gate line
513: second group gate line

Claims (10)

A method of driving a resistive memory device,
Setting a voltage of 0V to be applied to the first data line of the selected cell and setting the first voltage to be applied to the remaining first data line;
Setting a power supply voltage to be applied to a second data line of the selected cell and setting a second voltage to be applied to the remaining second data line; And
And applying a voltage to each of the first data line and the second data line according to the setting,
Wherein the sum of the first voltage and the second voltage is the same as the sum of the power supply voltages and the values are different from each other, and the first data line and the second data line are either a word line or a bit line,
Varying the first voltage and the second voltage according to a predetermined operation mode of a memory element of the resistive memory device,
Wherein the first voltage is set to a value obtained by multiplying the power supply voltage by 7/12 when the power supply is in a low power mode and the first voltage is multiplied by 2/3 Is set to a value of the resistance value of the resistive memory device. The method according to claim 1,
The first data line is a word line, the second data line is a bit line,
When the first voltage is set to a value obtained by multiplying the power supply voltage by 7/12, the second voltage is set to a value obtained by multiplying the power supply voltage by 5/12,
Wherein when the first voltage is set to a value obtained by multiplying the power supply voltage by 2/3, the second voltage is set to a value obtained by multiplying the power supply voltage by 1/3. The method according to claim 1,
The first data line is a bit line, the second data line is a word line,
When the first voltage is set to a value obtained by multiplying the power supply voltage by 7/12, the second voltage is set to a value obtained by multiplying the power supply voltage by 5/12,
Wherein when the first voltage is set to a value obtained by multiplying the power supply voltage by 2/3, the second voltage is set to a value obtained by multiplying the power supply voltage by 1/3. In a resistive memory device,
A memory element having a crossbar array structure,
A voltage supply unit for supplying a voltage to the first data line and the second data line of the memory element,
And a control unit for setting a supply voltage of the voltage supply unit,
Wherein the first data line and the second data line are either a word line or a bit line,
Wherein,
Setting a voltage of 0V to be applied to a first data line of a selected cell of the memory device and setting a first voltage to be applied to the remaining first data line, And setting the second voltage to be applied to the remaining second data line; and varying the first voltage and the second voltage according to a predetermined operation mode of the memory device,
Wherein the sum of the first voltage and the second voltage is equal to the sum of the power supply voltages,
Wherein the first voltage is set to a value obtained by multiplying the power supply voltage by 7/12 when the power supply is in a low power mode and the first voltage is multiplied by 2/3 Lt; / RTI > value. 5. The method of claim 4,
The first data line is a word line, the second data line is a bit line,
When the first voltage is set to a value obtained by multiplying the power supply voltage by 7/12, the second voltage is set to a value obtained by multiplying the power supply voltage by 5/12,
Wherein the second voltage is set to a value obtained by multiplying the power supply voltage by 1/3 when the first voltage is set to a value obtained by multiplying the power supply voltage by 2/3. 5. The method of claim 4,
The first data line is a bit line, the second data line is a word line,
When the first voltage is set to a value obtained by multiplying the power supply voltage by 7/12, the second voltage is set to a value obtained by multiplying the power supply voltage by 5/12,
Wherein the second voltage is set to a value obtained by multiplying the power supply voltage by 1/3 when the first voltage is set to a value obtained by multiplying the power supply voltage by 2/3. delete delete 5. The method of claim 4,
The first data line is a word line, the second data line is a bit line,
Wherein,
The first voltage is set to a value obtained by multiplying the power supply voltage by 2/3 in a read mode of the operation mode,
Sets the first voltage to a value obtained by multiplying the power supply voltage by 1/2 or a value obtained by multiplying the power supply voltage by 7/12 in the write mode of the operation mode. 5. The method of claim 4,
The first data line is a bit line, the second data line is a word line,
Wherein,
The first voltage is set to a value obtained by multiplying the power supply voltage by 2/3 in a read mode of the operation mode,
And sets the first voltage to a value obtained by multiplying the power supply voltage by 1/2 or a value obtained by multiplying the power supply voltage by 7/12 when the operation mode is the write mode.
KR1020150148220A 2015-10-23 2015-10-23 Resistive memory device and method for operating thereof KR101654135B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102150003B1 (en) * 2019-07-08 2020-08-31 이화여자대학교 산학협력단 Randum number generator using 3d crossbar memory
US11244721B2 (en) 2019-07-26 2022-02-08 Samsung Electronics Co., Ltd. Memory device for controlling unselected memory cells in accordance with adjacency to selected memory cell, and method for operating the same

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KR20140049108A (en) * 2012-10-12 2014-04-25 삼성전자주식회사 Resistive memory device and thereof operation method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102150003B1 (en) * 2019-07-08 2020-08-31 이화여자대학교 산학협력단 Randum number generator using 3d crossbar memory
US11244721B2 (en) 2019-07-26 2022-02-08 Samsung Electronics Co., Ltd. Memory device for controlling unselected memory cells in accordance with adjacency to selected memory cell, and method for operating the same

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