KR101637186B1 - dicing method for integrated circuit of through silicon via wafer - Google Patents

dicing method for integrated circuit of through silicon via wafer Download PDF

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Publication number
KR101637186B1
KR101637186B1 KR1020140164368A KR20140164368A KR101637186B1 KR 101637186 B1 KR101637186 B1 KR 101637186B1 KR 1020140164368 A KR1020140164368 A KR 1020140164368A KR 20140164368 A KR20140164368 A KR 20140164368A KR 101637186 B1 KR101637186 B1 KR 101637186B1
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South Korea
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wafer
integrated circuit
dividing
via hole
line
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KR1020140164368A
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Korean (ko)
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KR20160061686A (en
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김영권
오지훈
정현학
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주식회사 에스에프에이반도체
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Abstract

The present invention relates to a method of dividing an integrated circuit of a through silicon via wafer in which the efficiency of the integrated circuit dividing step of the through silicon via wafer is improved. The mask including the via hole forming portion and the dividing line forming portion is mounted on the wafer A photo-process step of performing photo-process; A via hole and a dividing line forming step of etching the via hole forming portion and the dividing line forming portion exposed in the photo process step to form a via hole and a dividing line on the wafer; A via hole conductor and a plating step for conducting and plating the inside of the via hole formed by the etching; And dividing the integrated circuit on the wafer along the division line formed by the etching.

Description

[0001] The present invention relates to a method of dividing an integrated circuit of a via-

The present invention relates to a method of dividing an integrated circuit of a through silicon via wafer, and more particularly, to a method of dividing an integrated circuit for dividing an integrated circuit in a via hole etching process for forming a through silicon via on a wafer, And more particularly, to a method of dividing an integrated circuit of a through silicon via wafer in which the efficiency of the integrated circuit dividing step of the silicon via wafer is increased.

The semiconductor device is fabricated through a whole process, that is, a fabrication process and a post-process, that is, an assembly process.

In the semiconductor device manufacturing process, a semiconductor device integrated circuit which has been subjected to a pre-process is subjected to an electrical die sorting (EDS) using a probe, and a semiconductor device determined to be good at this stage is subjected to a post- In the series

The semiconductor chip package is reworked through the packaging process.

On the other hand, a through silicon via (TSV) is recently formed on a wafer.

Therefore, when the through silicon vias of one chip obtained by dividing the integrated circuit of the wafer are brought into contact with the through silicon vias of the other chip, the physical and electrical connections between the chips can be made, .

At this time, in the conventional method of dividing the integrated circuit of the silicon via wafer, the through silicon vias 20 'are formed on the wafer 10' as shown in FIG. 8, . 15. As described in the above, the one integrated circuit on the wafer 10 'and the other integrated circuit in contact therewith were cut with various cutting equipment 50 such as a blade and a laser.

However, the method of dividing the integrated circuit of the conventional through silicon via wafer is a separate process of etching the via hole and the integrated circuit. Therefore, it takes a considerable time to complete the division of the integrated circuit of the through silicon via wafer.

In addition, the conventional method of dividing the integrated circuit of the through silicon via wafer has a problem in that it takes a considerable cost to prepare various kinds of cutting equipment.

In addition, a conventional method of dividing an integrated circuit of a through silicon via wafer involves a considerable physical impact during the cutting process through the cutting equipment, so that there is a problem that a damage such as a crack is generated in the integrated circuit.

In addition, the conventional method of dividing an integrated circuit of a through silicon via wafer has a problem in that the number of integrated circuits obtainable from the wafer suffers a loss because the width of the individual cutting lines by the cutting equipment is large and the loss area is large .

For the above reasons, it is possible to reduce the time and cost required for dividing the integrated circuit of the through silicon via wafer, and to prevent the integrated circuit from being damaged in the process of dividing the integrated circuit of the through silicon via wafer, The present inventors have searched for a method of dividing an integrated circuit of a via silicon wafer that minimizes the loss of the number of circuit acquisitions. However, until now, satisfactory results have not been obtained.

According to another aspect of the present invention, there is provided a method of dividing an integrated circuit of a through silicon via wafer according to the present invention, in which a via hole etching process and an integrated circuit cutting process are separately performed in the method of dividing an integrated circuit of a through silicon via wafer, The present invention is directed to a method of dividing an integrated circuit of a through silicon via wafer, which can solve the problem that it took a considerable time to complete the integrated circuit division of the through-silicon.

The method of dividing an integrated circuit of a through silicon via wafer according to the present invention is a method of dividing an integrated circuit of a through silicon via wafer into a through silicon via wafer that can solve the problem that a considerable cost is required for preparing various cutting equipment The present invention provides a method of dividing an integrated circuit.

In addition, the method for dividing an integrated circuit of a through silicon via wafer according to the present invention can solve the problem that a damage such as a crack is generated in an integrated circuit in a cutting process through a cutting equipment in a conventional method of dividing an integrated circuit of a through silicon via wafer And a method of dividing an integrated circuit of a through silicon via wafer.

The method of dividing an integrated circuit of a through silicon via wafer according to the present invention is a method of dividing an integrated circuit of a conventional through silicon via wafer in a method of dividing an integrated circuit of a through silicon via wafer, The present invention provides a method of dividing an integrated circuit of a through silicon via wafer, which can solve the problem of a loss in the number of integrated circuits.

According to another aspect of the present invention, there is provided a method of dividing an integrated circuit of a silicon via wafer, comprising: performing a photolithography process by mounting a mask including a via hole forming portion and a dividing line forming portion on a wafer; A via hole and a dividing line forming step of etching the via hole forming portion and the dividing line forming portion exposed in the photo process step to form a via hole and a dividing line on the wafer; A via hole conductor and a plating step for conducting and plating the inside of the via hole formed by the etching; And dividing the integrated circuit on the wafer along the division line formed by the etching.

Here, in the photo-process step, the via-hole forming portions are disposed at intervals in the respective contact circuits on the wafer.

The photo-process step is performed such that the division line forming portion is disposed between one integrated circuit on the wafer and another integrated circuit adjacent thereto.

In the forming of the via hole and the dividing line, the etching of the via hole forming portion and the dividing line forming portion may be performed in a wet method or a dry method.

The via hole and the dividing line forming step may be formed in a line shape in which the dividing line extends from one end to the other end on a plane.

The via hole and the dividing line forming step may be formed in a point shape in which the dividing lines are continuous with a plane interval.

And the step of dividing the integrated circuit may include a wafer bottom grinding step of grinding the wafer from the bottom of the wafer to the bottom of the division line.

The step of dividing the integrated circuit may include an etching groove forming step of forming an etching groove extending from the bottom surface of the wafer to the lower end of the dividing line.

The integrated circuit breaking step may include a wafer bottom grinding step of grinding the wafer from the bottom surface of the wafer to the lower end of the dividing line and a dividing line expanding step of expanding the dividing line to both sides.

The step of dividing the integrated circuit may include an etching groove forming step of forming an etching groove extending from the bottom surface of the wafer to the lower end of the dividing line and a dividing line extending step of expanding the dividing line to both sides.

Since the via hole and the dividing line are simultaneously formed on the wafer by the via hole and the dividing line forming step, the method of dividing the integrated circuit of the through silicon via wafer according to the present invention can prevent the process delay due to the separation progress of the via hole formation and the dividing line There is an effect that can be.

In addition, according to the method for dividing an integrated circuit of a through silicon via wafer according to the present invention, since the dividing line is formed by etching, it is not necessary to provide a cutting equipment, and the cost for preparing the cutting equipment can be reduced.

In addition, the method for dividing an integrated circuit of a through silicon via wafer according to the present invention has the effect of preventing damage to a chip by preventing a physical impact due to the use of a cutting equipment because the dividing line is formed by etching.

In addition, the method for dividing an integrated circuit of a through silicon via wafer according to the present invention is characterized in that since the dividing line is formed by etching, the width of the dividing line can be made finer and the chip loss Can be minimized.

1 is a process chart of a method of dividing an integrated circuit according to the present invention.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of forming a via hole and a dividing line in an integrated circuit dividing method.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of dividing an integrated circuit, and more particularly,
4 is an exemplary diagram for explaining the formation of consecutive point shapes of division lines in the method of dividing an integrated circuit according to the present invention.
5 is an exemplary view for explaining the division of an integrated circuit by wafer bottom grinding in the method of dividing an integrated circuit according to the present invention.
6 is an exemplary view for explaining the division of an integrated circuit through the formation of an etch groove on the bottom surface of the wafer in the method for dividing an integrated circuit according to the present invention.
7 is an exemplary diagram for explaining the extension of a dividing line in the method of dividing an integrated circuit according to the present invention.
8 is an exemplary view showing the division of an integrated circuit through a conventional cutting equipment;

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the method for dividing an integrated circuit of a through silicon via wafer according to the present invention includes a photo-process step S1, a via hole and a dividing line forming step S2, a via hole lead and a plating step S3, , And an integrated circuit breaking step S4.

In the photolithography step S1, a mask (not shown in the drawing) including a via hole forming portion and a dividing line forming portion is mounted on the wafer 10 to perform a photolithography process.

In the photolithography step S1, the via hole forming portions are disposed at intervals in each integrated circuit (not shown in the figure) on the wafer 10. [

Since a plurality of through silicon vias 20 are formed in each integrated circuit by arranging the via hole formation sites in the integrated circuits on the wafer 10 in the photo process step S1, chips obtained by dividing the integrated circuit The upper chip and the lower chip can be physically and electrically connected by the contact of the plurality of through silicon vias 20. [

In the photo process step S1, the division line forming portion is disposed between one integrated circuit on the wafer 10 and another integrated circuit adjacent thereto.

In the photolithography step S1, when the division line forming part is disposed between one integrated circuit on the wafer 10 and another integrated circuit adjacent thereto, if the integrated circuit is divided along the division line 30 to be formed later, Can be obtained.

Meanwhile, the photolithography step (S1) is similar to the photolithography in the process of forming a via hole, except that the masking line forming part is further included in the mask, and the detailed description of the photolithography step (S1) is omitted do.

The via hole and the dividing line forming step S2 form a via hole 21 and a dividing line 30 on the wafer 10 by etching the via hole forming part and the dividing line forming part exposed in the photolithography step S1 .

The dividing line 30 formed by the via hole and the dividing line forming step S2 may be in a line shape extending from one end to the other end on a plane or in a point shape continuous with an interval therebetween.

In the meantime, in the via hole and the dividing line forming step S2, the etching may be performed by a wet method or a dry method.

Etching by the wet method or the dry method is a general matter related to the formation of a general via hole, and thus a detailed description thereof will be omitted.

The via hole conductor and the plating step S3 are to conduct the wiring and plating inside the via hole 21 formed by etching.

Since the via hole conductor and the plating step S3 are technologies that are common with respect to the formation of the common via hole, detailed description of the via hole conductor and the plating step S3 will be omitted.

On the other hand, it is needless to say that the upper end of the conductor and the plating portion are planarized.

The upper surface of the conductive line and the plating portion is flattened, so that the upper surface of the wafer 10 can maintain a flat surface.

The integrated circuit breaking step S4 is to break up the integrated circuit along the division line 30 formed by etching.

The integrated circuit dividing step S4 may include a wafer bottom grinding step for grinding the bottom of the wafer 10 to the lower end of the division line 30. [

The dividing line 30 formed in a line shape by the bottom surface of the wafer 10 includes the wafer bottom grinding step in which the integrated circuit dividing step S4 grinds the wafer 10 from the bottom surface to the bottom end of the dividing line 30 Accordingly, the integrated circuit can be divided.

The step of dividing the integrated circuit S4 may include an etching groove forming step of forming the etching groove 40 extending from the bottom surface of the wafer 10 to the lower end of the dividing line 30. [

The integrated circuit dividing step S4 includes an etching groove forming step of forming an etching groove 40 extending from the bottom surface of the wafer 10 to the lower end of the dividing line 30, The integrated circuit can be divided along the line 30.

The integrated circuit dividing step S4 may include a wafer bottom grinding step for grinding the wafer 10 from the bottom face to the bottom end of the dividing line 30 and a dividing line extending step for expanding the dividing line 30 to both sides .

A wafer bottom grinding step in which the integrated circuit dividing step S4 grinds from the bottom surface of the wafer 10 to the lower end of the dividing line 30 and a dividing line extending step in which the dividing line 30 is spread out to both sides, The bottom grinding and dividing line 30 extension allows the integrated circuit to be divided along a dividing line 30 formed in a continuous point shape.

The integrated circuit dividing step S4 includes an etch groove forming step for forming an etch groove 40 extending from a bottom surface of the wafer 10 to a lower end of the dividing line 30 and an etch groove forming step for dividing the dividing line 30, Step < / RTI >

The step of dividing the integrated circuit S4 includes an etching groove forming step of forming an etching groove 40 extending from the bottom surface of the wafer 10 to the lower end of the dividing line 30 and a dividing line expanding step of expanding the dividing line 30 to both sides The integrated circuit can be divided along the division line 30, which is formed in a continuous point shape by the formation of the etch groove 40 and the extension of the division line 30. [

The detailed description of the division of the integrated circuit of the through silicon via wafer 10 through the integrated circuit dividing method according to the present invention is as follows.

First, a mask including a via hole forming region and a dividing line forming region is mounted on the wafer 10, and a photo process is performed.

That is, the photo process step (S1) according to the present invention proceeds.

In the present invention, the via hole forming portions are disposed in the respective integrated circuits on the wafer 10 at intervals, so that a plurality of through silicon vias 20 can be formed in each integrated circuit. Therefore, a chip obtained by dividing the integrated circuit The upper chip and the lower chip can be physically and electrically connected by the contact of the plurality of through silicon vias 20. [

In the present invention, the division line forming portion is disposed between one integrated circuit on the wafer 10 and another integrated circuit adjacent thereto. When the integrated circuit is divided along the division line 30 formed thereby, Chips can be obtained.

Next, as shown in FIG. 2, the via hole 21 and the dividing line 30 are formed on the wafer 10 by etching the via hole forming portion and the dividing line forming portion exposed by the photolithography step S1 do.

That is, a via hole and a dividing line forming step (S2) according to the present invention proceeds.

The via hole 21 and the dividing line 30 are formed on the wafer 10 by etching the via hole forming portion and the dividing line forming portion exposed by the photolithography step S2 so that the via hole 21 and the dividing line 30 are formed on the wafer 10, The integrated circuit on the wafer 10 can be correctly and easily segmented as the integrated circuit on the wafer 10 is divided.

In the present invention, the dividing line 30 may be in the shape of a line extending from one end to the other end, or a point continuous with intervals, as shown in FIG. 3 or FIG.

Next, wiring and plating are performed inside the via hole 21 formed by etching.

That is, the via hole conductor and the plating step (S3) according to the present invention are performed.

The through silicon vias 20 can be formed by conducting and plating in the via holes 21 formed by etching and when the vias 20 of one chip and the vias 20 of the other chip are vertically contacted The contact between the conductive wire and the plating part is made so that the upper and lower chips can be physically and electrically connected to each other.

Next, the integrated circuit is divided along the division line 30 formed by the etching.

That is, the step of dividing the integrated circuit according to the present invention (S4) is performed.

In the present invention, the step of dividing the integrated circuit S4 may include a wafer bottom grinding step of grinding the wafer 10 from the bottom surface of the wafer 10 to the bottom of the dividing line 30. As shown in FIG. 5, The integrated circuit on the wafer 10 can be divided along the division line 30, which is formed in a line shape.

In the present invention, the step of dividing the integrated circuit S4 may include an etching groove forming step of forming the etching groove 40 extending from the bottom surface of the wafer 10 to the lower end of the dividing line 30, The integrated circuit on the wafer 10 is formed along the division line 30 in the form of a line by forming the etching groove 40 leading to the lower end of the division line 30 formed in a line form on the bottom surface of the wafer 10, .

In the present invention, the integrated circuit dividing step S4 includes a wafer bottom grinding step for grinding the wafer 10 from the bottom face to the bottom end of the dividing line 30, and a dividing line extending step for expanding the dividing line 30 to both sides As shown in FIG. 5, after the bottom surface of the wafer 10 is ground to a lower end of a dividing line 30 formed in a continuous point shape with intervals therebetween, The integrated circuit on the wafer 10 can be segmented along the dividing line 30, which is in the form of a continuous, point-like dot, by expanding the segment 30 on both sides, i.e. by tearing the segment 30 on both sides.

In the present invention, the step of dividing the integrated circuit S4 includes an etching groove forming step of forming the etching groove 40 extending from the bottom surface of the wafer 10 to the lower end of the dividing line 30, 6, an etch groove 40 is formed in the bottom of the wafer 10 and extends to the lower end of the dividing line 30, which is formed in a continuous point shape at intervals on the bottom surface of the wafer 10. As shown in FIG. 7, the division line 30 is extended to both sides, that is, the division line 30 is torn on both sides, so that the integrated circuit on the wafer 10 is divided into a dotted line segment Lt; / RTI >

As described above, the method for dividing the integrated circuit of the through silicon via wafer according to the present invention is characterized in that the via hole 21 and the dividing line 30 are simultaneously formed on the wafer 10 by the via hole and the dividing line forming step S2 It is possible to prevent the process delay due to the progress of the formation of the via hole 21 and the formation of the dividing line 30 and to form the dividing line 30 by the etching, The damage of the chip can be prevented and the width of the division line 30 can be made comparatively small, so that the formation of the division line 30 can be prevented It is possible to minimize the loss of the chips that can be obtained from the one wafer 10 due to the wafer.

It is to be understood that both the foregoing general description and the following detailed description are merely exemplary and are not to be construed as limiting the invention as defined by the appended claims and their equivalents. The present invention is within the scope of protection of the present invention.

10, 10 ': wafer 20, 20': through silicon vias
21: via hole 30: branch line
40: etch groove 50: cutting equipment
S1: photo process step S2: via hole and division line formation step
S3: via conductor lead and plating step S4: step of dividing integrated circuit

Claims (10)

A photolithography step of performing a photolithography process by mounting a mask including a via hole forming region and a dividing line forming region on a wafer;
A via hole and a dividing line forming step of etching the via hole forming portion and the dividing line forming portion exposed in the photo process step to form a via hole and a dotted dividing line on the wafer;
A via hole conductor and a plating step for conducting and plating the inside of the via hole formed by the etching; And
And dividing the integrated circuit on the wafer along the dotted line segment formed by the etching,
Wherein the step of dividing the integrated circuit comprises:
A wafer bottom grinding step for grinding the bottom of the wafer to the bottom of the division line; And
Further comprising a division line extension step of expanding the dotted division line to both sides so that the integrated circuit is divided along the dotted division line.
delete The method according to claim 1,
And the via-hole forming portions are disposed at intervals in the respective integrated circuits on the wafer
A method of dividing an integrated circuit of a through silicon via wafer.
The method according to claim 1,
Wherein the division line forming portion is disposed between one integrated circuit on the wafer and another integrated circuit adjacent thereto
A method of dividing an integrated circuit of a through silicon via wafer.
The method according to claim 1, wherein the forming of the via hole and the dividing line comprises:
The etching of the via hole forming portion and the dividing line forming portion is performed in a wet type or a dry type
A method of dividing an integrated circuit of a through silicon via wafer. delete delete delete delete delete
KR1020140164368A 2014-11-24 2014-11-24 dicing method for integrated circuit of through silicon via wafer KR101637186B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100203661A1 (en) 2007-06-29 2010-08-12 Showa Denko K.K. Method for producing light-emitting diode

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4307284B2 (en) * 2004-02-17 2009-08-05 三洋電機株式会社 Manufacturing method of semiconductor device
KR101446288B1 (en) * 2008-03-25 2014-10-01 삼성전자주식회사 Method Of Fabricating Semiconductor Device
KR101712630B1 (en) * 2010-12-20 2017-03-07 삼성전자 주식회사 Method of forming semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100203661A1 (en) 2007-06-29 2010-08-12 Showa Denko K.K. Method for producing light-emitting diode

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