KR101619506B1 - Signal generating device, active cable, and method for signal generating - Google Patents
Signal generating device, active cable, and method for signal generating Download PDFInfo
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- KR101619506B1 KR101619506B1 KR1020150099052A KR20150099052A KR101619506B1 KR 101619506 B1 KR101619506 B1 KR 101619506B1 KR 1020150099052 A KR1020150099052 A KR 1020150099052A KR 20150099052 A KR20150099052 A KR 20150099052A KR 101619506 B1 KR101619506 B1 KR 101619506B1
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- Prior art keywords
- pll circuit
- clock signal
- parameter
- circuit
- cable
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- 238000000034 method Methods 0.000 title claims description 33
- 230000005540 biological transmission Effects 0.000 claims description 31
- 238000005457 optimization Methods 0.000 description 40
- 230000003287 optical effect Effects 0.000 description 18
- 230000008054 signal transmission Effects 0.000 description 15
- 230000006870 function Effects 0.000 description 14
- 238000001514 detection method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000010485 coping Effects 0.000 description 4
- 239000013307 optical fiber Substances 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101100173436 Fusarium pseudograminearum (strain CS3096) FCK1 gene Proteins 0.000 description 1
- 101100150409 Gibberella moniliformis SSN3 gene Proteins 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/077—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
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- Synchronisation In Digital Transmission Systems (AREA)
- Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Studio Devices (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
Abstract
The present signal generating apparatus includes a PLL circuit and a control circuit for controlling the PLL circuit. The PLL circuit is capable of changing the operation band in accordance with the setting change of the parameter. When locked in each operation band, Generates an output clock signal in accordance with the input clock signal, and the control circuit sequentially changes the setting of the parameter until the PLL circuit is locked.
Description
The present invention relates to a signal generating apparatus using a PLL circuit.
2. Description of the Related Art A PLL (Phase Looked Loop) circuit for generating an output clock signal in accordance with an input clock signal is widely used in an apparatus (for example, a transmission apparatus of Patent Document 1) that handles an image signal from an external device.
The PLL circuit as described above is required to be capable of responding to input signals of various external apparatuses (cameras, etc.). On the other hand, it is possible to consider a configuration in which the operating band of the PLL circuit is varied to determine the input (frequency and the like) from the external device to set the operating band of the PLL circuit, but a circuit for determining input from the external device Resulting in an increase in size and cost.
The present invention provides a signal generating apparatus capable of coping with input of various external apparatuses and capable of suppressing size and cost.
The signal generating apparatus according to the present invention includes a PLL circuit and a control circuit for controlling the PLL circuit. The PLL circuit is capable of changing an operation band according to a parameter setting change, The control circuit generates an output clock signal corresponding to an input clock signal to the PLL circuit, and the control circuit sequentially changes the setting of the parameter until the PLL circuit is locked.
In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the setting of the parameters, and the PLL circuit is locked. That is, an output clock signal according to this input clock signal can be obtained in the setting of a parameter suitable for the input clock signal and the operating band from the outside to the PLL circuit. This makes it unnecessary to provide a circuit for judging an input from the outside, and it is possible to realize a signal generating apparatus capable of coping with various inputs from outside, and capable of suppressing size and cost.
1 is a block diagram showing a configuration of a transmission apparatus according to the first embodiment.
2 is a block diagram showing a configuration of a first jitter cleaner.
3 is a table showing a specific example of the parameter.
4 is a flowchart showing optimization processing of the first jitter cleaner according to the first embodiment.
5 is a flowchart showing an optimization process of the first jitter cleaner according to the second embodiment.
6 is a flowchart showing optimization processing of the first jitter cleaner according to the third embodiment.
7 is a flowchart showing another example of the optimization processing of the first jitter cleaner according to the third embodiment.
8 is a block diagram showing a configuration of an active optical cable according to the fourth embodiment.
9 is a flowchart showing the determination as to whether or not the optimization processing according to the fourth embodiment is necessary.
10 is a block diagram showing the configuration of the active optical cable according to the fifth embodiment.
11 is a flowchart showing an optimization process according to the sixth embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to Figs. 1 to 11. Fig.
[Embodiment 1]
1 is a block diagram showing a configuration of a transmission apparatus according to the first embodiment. 1, the
Here, the active cable refers to a cable having an active element (an element that operates by power supplied from the outside). Examples of the active element include a parallel / serial (S) conversion circuit (serializer), a serial / parallel conversion circuit (deserializer), an electric / (O / E) conversion circuit. In the
The
The data signal X is input from the
The
The configuration of the
The first dividing
The first
As described above, the PLL circuit 40 is constituted by a feedback circuit that sets the phase difference (frequency difference) between the clock signal output from the first
If the band of the
On the other hand, the
The switching of the operation band of the PLL circuit 40 is realized by interchanging the division ratios A, B, C, and D written in the
For example, the parameter of the setting number 1 (A = 100, B = 5000, C = 2, D = 50) corresponds to the input clock frequency 19-21 (A = 200, B = 2400, C = 2, D = 12) corresponding to the input clock frequency 22-25 Corresponds to input clock frequency 78-90 (MHz). The input clock signal of 19 to 90 MHz is covered by the parameter of the 11th column in Fig. 3, so that it is possible to cope with the input frequency (20 to 85 MHz) of the camera link standard.
The processing of optimizing the operation band of the PLL circuit 40 of the
The
When the optimization processing is completed, the
When the optimization processing is not completed even if all the parameters up to i = 11 are set, if the clock signal from the
The
1, the
According to the embodiment (1), a circuit for determining the frequency or the like of an input clock signal from a camera or the like, for example, an FPGA (Field Programmable Gate Array) or the like is not required, It is possible to realize a transmission apparatus having a jitter removing function capable of coping with various input clock signals.
On the other hand, a conventional active cable not having a jitter removing function is also provided with a processor that controls the signal conversion circuit and transmits and receives an internal link signal. Therefore, it is possible to realize an active cable (transfer apparatus 1) having a jitter removing function by merely providing a jitter cleaner in a conventional active cable and having the processor have the optimization processing function shown in Fig. As described above, in the embodiment (1), since it is unnecessary to add a component other than the jitter cleaner, it is possible to avoid a significant increase in the size and cost of the active cable (particularly, the connector portion).
In the camera link standard, the frequency (input frequency) of the clock signal from the camera is specified in the range (20 to 85 MHz), and the frequency of the clock signal from the camera can take any value within this range. In addition, there is no restriction on the jitter of the clock signal from the camera. (For a camera with a large jitter of about 1.6%, proper signal transmission may not be possible with a conventional active cable having no jitter removal function.) In this respect, the
[Embodiment 2]
The optimization processing in the first embodiment may be performed as shown in Fig. That is, the
Then, the parameter of the setting number i (see FIG. 3) = 1 is read out (S13), and written to the register 50 (S14). Subsequently, the
According to the second embodiment, when the cameras to be connected are the same, the time required for optimization can be shortened.
[Embodiment 3]
The optimization processing in
The optimization processing in
Then, a parameter of the setting number i (see FIG. 3) = 1 is read out (S33) and it is judged whether the flag is valid or invalid (S34). If it is invalid, the process returns to S33 to read the parameter of the setting number (i + 1) and determine whether the flag is valid or invalid (S34). If it is valid in step S34, the
According to the third embodiment, it is possible to shorten the time required for optimization while suppressing the use of the memory of the
[Embodiment 4]
Fig. 8 shows a configuration example in a case where this transmission apparatus is applied to an optical camera link cable (active optical cable conforming to the camera link standard). 8, the optical
An optical signal transmission path 131 (optical fiber), an internal link
The
Data signals x0 to x3 (parallel signals) are input from the
The
The deserializer 121 generates data signals x0 to x3 and a clock signal CK2 from the optical signal received from the optical
The deserializer 121 is provided with a PLL circuit (not shown) for generating a clock signal CK2 and a lock detection pin LD for outputting a lock state of the PLL circuit. The
The
According to the fourth embodiment, it is possible to optimize the
[Embodiment 5]
Fig. 10 shows another configuration example in the case where this transmission apparatus is applied to an optical camera link cable. 10, the optical
An optical signal transmission line (optical fiber) 131, an internal link
The
The
Data signals x0 to x3 (parallel signals) are input from the
The
The deserializer 121 generates the data signals x0 to x3 and the clock signal ck2 from the optical signal received from the optical
Here, the
On the other hand, in the
According to the fourth embodiment, since the same optimizing process as that on the camera side is not required on the grabber side, the processing speed on the grabber side can be increased.
[Embodiment 6]
In each of the above embodiments, the optimization process is performed for the purpose of jitter removal, but the present invention is not limited to this. For example, when the
3) = 1 from the memory (S1), the
[theorem]
A signal generating apparatus according to the present invention includes a PLL circuit and a control circuit for controlling the PLL circuit. The PLL circuit is capable of changing an operation band according to a setting change of a parameter, and when locked in each operation band, And generates an output clock signal corresponding to an input clock signal to the PLL circuit, and the control circuit sequentially changes the setting of the parameter until the PLL circuit is locked.
In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the setting of the parameters, and the PLL circuit is locked. That is, an output clock signal according to this input clock signal can be obtained in the setting of a parameter suitable for the input clock signal and the operation band from the outside to the PLL circuit.
This makes it possible to realize a signal generating apparatus which can cope with various inputs from the outside, and which can suppress the size and the cost, without a circuit or the like for judging an input from the outside.
In this signal generating apparatus, it is preferable that a frequency band in which the input clock signal is assumed is covered by a plurality of changeable operation bands.
For example, the input clock signal of the camera link standard is 20 to 85 MHz, and this is covered by a plurality of operating bands, so that it is possible to cope with various input clock signals according to the standard.
In this signal generating apparatus, the jitter of the input clock signal may be eliminated from the output clock signal.
Since the PLL circuit has a jitter canceling function by adjusting the circuit characteristics (for example, the relaxation time), the signal generating apparatus having the above-described configuration can be used as a jitter canceling device capable of coping with various input clock signals.
In the present signal generating apparatus, the PLL circuit may include a plurality of frequency dividers, and the parameter may be a combination of division ratios of these frequency divisions.
Thus, by changing the parameter to a combination of division ratios, it is easy to change the operating band of the PLL circuit.
In the present signal generating apparatus, the control circuit may be configured to set in the order of a parameter having a large number of locks in the past.
In this case, the time required for parameter setting can be shortened.
In the present signal generating apparatus, the control circuit may be configured to determine whether or not the setting of each parameter is necessary based on information previously added to each parameter.
By doing so, it is possible to shorten the time required for setting while suppressing the memory use of the control circuit.
The active cable includes a transmitter, a cable, and a receiver connected to the transmitter via the cable, wherein the signal generator is included in at least one of the transmitter and the receiver.
Since various clock signals are input to the active cable, the signal generating apparatus can be suitably used.
In this active cable, the signal generator is included in the transmitter, the receiver includes a PLL circuit different from the PLL circuit of the signal generator, and the lock state of the other PLL circuit included in the receiver is detected by the transmitter And the control circuit of the signal generating apparatus included in the transmitting section may be configured to determine whether or not to set the parameter of the PLL circuit of the signal generating apparatus again based on the notified lock situation.
According to the above configuration, it is possible to set the parameters of the PLL circuit of the transmitting unit to the abnormality of the receiving unit such as the unlocking of the receiving unit.
In this active cable, the transmitter includes the signal generating device, and the receiver includes a PLL circuit which is different from the PLL circuit of the signal generating device and is capable of changing the operation band in accordance with the parameter setting change, The control circuit of the signal generation apparatus notifies the reception section of the parameter locked by the PLL circuit of the signal generation apparatus and sets the other PLL circuit included in the reception section on the basis of the notified parameter It is possible.
According to the above configuration, since setting of the same PLL circuit as that of the transmitting side is not required on the receiving side, the processing speed on the receiving side can be increased.
It is preferable that this active cable conforms to the standard of the camera link (registered trademark) (hereinafter referred to as "camera link standard"). In the camera link specification, the frequency range of the clock signal from the camera is fixed, and the frequency varies depending on the camera. According to the signal generating device of the present active cable, it is possible to cover a range of the input frequency of the camera link standard by a plurality of changeable operation bands, and thus it is possible to cope with various cameras.
In addition, there is no jitter restriction in the camera link specification, and there may be a case where a large jitter is included in the input from the camera. Since the signal generating apparatus of this active cable can have a jitter canceling function, appropriate signal transmission is possible even when a large jitter is contained in the input from the camera.
A signal generating method using a PLL circuit for generating an output clock signal according to an input clock signal when an operation band can be changed according to a parameter setting change and locked in each operation band, And the setting is sequentially changed until the PLL circuit is locked.
In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the setting of the parameters, and the PLL circuit is locked. In other words, an output clock signal according to the input clock signal can be obtained by setting a parameter suitable for the input clock signal from the outside to the PLL circuit and the operation band of the PLL circuit.
This makes it possible to realize a signal generating apparatus which can cope with various inputs from the outside, and which can suppress the size and the cost, without a circuit or the like for judging an input from the outside.
The present invention can be applied to a transmission system using a clock signal (for example, a camera link).
1: Transmission device 2: Transfer source device
3: transfer destination device 10:
11: Transmitter 12: First jitter cleaner
13: first processor (control circuit) 20:
21: receiver 22: second jitter cleaner
23: second processor 40: PLL circuit
Claims (11)
A signal generator is provided in the transmitter,
The signal generating apparatus includes a first PLL circuit and a control circuit for controlling the first PLL circuit,
The first PLL circuit generates an output clock signal corresponding to an input clock signal to the first PLL circuit when the operation band is locked in each operation band,
Wherein the control circuit sequentially changes the setting of the parameter until the first PLL circuit is locked,
A second PLL circuit different from the first PLL circuit is included in the receiving unit,
The lock status of the second PLL circuit is notified to the transmission unit, and the control circuit determines whether or not to set the parameter of the first PLL circuit again based on the notified lock situation.
Wherein a frequency band in which the input clock signal is assumed is covered by a plurality of changeable operation bands.
Wherein the jitter of the input clock signal is eliminated in the output clock signal.
Wherein the first PLL circuit includes a plurality of frequency dividers, and the parameter is a combination of division ratios of these frequency divisions.
Wherein the control circuit sets the control circuit in the order of the number of past lock cycles.
Wherein said control circuit judges whether or not setting of each parameter is necessary based on information added in advance to each parameter.
A signal generator is provided in the transmitter,
The signal generating apparatus includes a first PLL circuit and a control circuit for controlling the first PLL circuit,
The first PLL circuit generates an output clock signal corresponding to an input clock signal to the first PLL circuit when the operation band is locked in each operation band,
Wherein the control circuit sequentially changes the setting of the parameter until the first PLL circuit is locked,
A second PLL circuit capable of changing an operation band according to a setting change of a parameter different from the first PLL circuit is included in the receiving unit,
Wherein the control circuit notifies the receiver of the parameter locked by the first PLL circuit, and sets the second PLL circuit based on the notified parameter.
An active cable used for a camera link standard.
Sequentially changing the setting of the parameter until the first PLL circuit is locked,
Notifies the transmitter of the lock state of the second PLL circuit and determines whether to set the parameter of the first PLL circuit again based on the notified lock situation.
Sequentially changing the setting of the parameter until the first PLL circuit is locked,
Notifies the receiver of the locked parameter of the first PLL circuit, and sets the second PLL circuit based on the notified parameter.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014145239A JP5785643B1 (en) | 2014-07-15 | 2014-07-15 | Active cable and control method of active cable |
JPJP-P-2014-145239 | 2014-07-15 |
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KR20160008973A KR20160008973A (en) | 2016-01-25 |
KR101619506B1 true KR101619506B1 (en) | 2016-05-10 |
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KR1020150099052A KR101619506B1 (en) | 2014-07-15 | 2015-07-13 | Signal generating device, active cable, and method for signal generating |
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JP (1) | JP5785643B1 (en) |
KR (1) | KR101619506B1 (en) |
CN (1) | CN105323469B (en) |
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CN107592511A (en) * | 2017-09-21 | 2018-01-16 | 武汉恒泰通技术有限公司 | A kind of video optical module that can reduce shake |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000138660A (en) * | 1998-10-30 | 2000-05-16 | Nec Corp | Clock phase locked loop circuit |
JP2014082681A (en) * | 2012-10-17 | 2014-05-08 | Fujikura Ltd | Cable with connector and improper connection detection method of cable with connector |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03190336A (en) * | 1989-12-19 | 1991-08-20 | Fujitsu Ltd | Transmission and reception synchronizing circuit system |
JPH08125529A (en) * | 1994-10-20 | 1996-05-17 | Fujitsu General Ltd | Pll circuit |
JPH09101972A (en) * | 1995-10-09 | 1997-04-15 | Fujitsu Ltd | Program retrieval order control system |
JP4003315B2 (en) * | 1998-10-06 | 2007-11-07 | コニカミノルタビジネステクノロジーズ株式会社 | Data transmission / reception system |
JP4625863B2 (en) * | 2006-03-01 | 2011-02-02 | パナソニック株式会社 | Transmitting apparatus and transmitting / receiving apparatus |
JP2010286966A (en) * | 2009-06-10 | 2010-12-24 | Nec Corp | Information reader, information reading method, and program |
JP4898948B1 (en) | 2010-09-10 | 2012-03-21 | 株式会社フジクラ | Data transmission device, data transmission method, and data transmission device control program |
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2014
- 2014-07-15 JP JP2014145239A patent/JP5785643B1/en not_active Expired - Fee Related
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2015
- 2015-07-13 KR KR1020150099052A patent/KR101619506B1/en active IP Right Grant
- 2015-07-14 CN CN201510413251.7A patent/CN105323469B/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000138660A (en) * | 1998-10-30 | 2000-05-16 | Nec Corp | Clock phase locked loop circuit |
JP2014082681A (en) * | 2012-10-17 | 2014-05-08 | Fujikura Ltd | Cable with connector and improper connection detection method of cable with connector |
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Publication number | Publication date |
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CN105323469B (en) | 2017-03-08 |
JP2016021709A (en) | 2016-02-04 |
KR20160008973A (en) | 2016-01-25 |
CN105323469A (en) | 2016-02-10 |
JP5785643B1 (en) | 2015-09-30 |
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