KR101573270B1 - Pillar devices and methods of making thereof - Google Patents
Pillar devices and methods of making thereof Download PDFInfo
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- KR101573270B1 KR101573270B1 KR1020107017757A KR20107017757A KR101573270B1 KR 101573270 B1 KR101573270 B1 KR 101573270B1 KR 1020107017757 A KR1020107017757 A KR 1020107017757A KR 20107017757 A KR20107017757 A KR 20107017757A KR 101573270 B1 KR101573270 B1 KR 101573270B1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
Abstract
A method of manufacturing a semiconductor device, comprising: providing an insulating layer comprising a plurality of openings; forming a first semiconductor layer over the insulating layer and a plurality of openings in the insulating layer; And removing the first portion of the first semiconductor layer such that the second portion of the first conductivity type remains at the lower portion of the plurality of openings in the insulating layer and the upper portion of the plurality of openings in the insulating layer remains unfilled. The method also includes forming a second semiconductor layer over the insulating layer and over the plurality of openings in the insulating layer and removing the first portion of the second semiconductor layer overlying the insulating layer. The second conductive type second portion of the second semiconductor layer is left on top of the plurality of openings in the insulating layer to form a plurality of pillar type diodes in the plurality of openings.
Description
Cross-reference to related patent application
This application claims priority to U.S. Serial Nos. 12 / 007,780 and 12 / 007,781, filed January 15, 2008, both of which are incorporated herein by reference in their entirety .
Technical field
BACKGROUND OF THE
U.S. Patent Application No. 10 / 955,549 (corresponding to U.S. Patent Application Publication No. 2005/0052915 A1), Herner et al., Filed September 29, 2004, which is incorporated herein by reference, discloses a three-dimensional memory array Wherein the data state of the memory cell is stored in the resistive state of the polycrystalline semiconductor material of the pillar type semiconductor junction diode in this three dimensional memory array. A subtractive method is used to fabricate such a filament diode device. The method includes depositing one or more layers of silicon, germanium, or other semiconductor material. The deposited semiconductor layers or layers are then etched to obtain a semiconductor pillar. An SiO 2 layer can be used as a hardmask for pillar etching and then removed. Next, SiO 2 or other gap-filling dielectric material is deposited between the pillars and on top of the pillars. A chemical mechanical polishing (CMP) or etchback step is then performed to planarize the gap filling dielectric with the top surface of the pillar.
A further description of a subtractive pillar manufacturing process is provided in U.S. Patent Application No. 11 / 015,824, entitled " Nonvolatile Memory Cell Containing a Vertical Diode of Reduced Height ", filed December 17, 2004 by Herner et al. See U.S. Patent Application No. 11 / 819,078, filed on June 25, 2006.
However, in the subtractive method, care must be taken to avoid undercutting the pillars at the base of the pillars during the etching step, for small diameter and width pillars. The undercut pillar device tends to fall during subsequent processing. Further, for smaller pillared devices, the height of the semiconductor pillar may be limited by the thin and soft photoresist used as the etch mask, and the oxide gap filling step may be used to reduce the processing challenges when the aspect ratio of the openings between the pillars increases And the CMP process or etch-back of the gap filling layer can remove a considerable thickness of the deposited semiconductor material.
One embodiment of the present invention provides a method of fabricating a semiconductor device comprising the steps of providing an insulating layer comprising a plurality of openings, forming a plurality of openings in a plurality of openings of the insulating layer, To form a layer. The method further includes forming a first semiconductor layer so that the first conductive type second portion of the first semiconductor layer remains on the lower portion of the plurality of openings of the insulating layer and the upper portion of the plurality of openings in the insulating layer remains uncharged. And removing the first portion of the layer. The method also includes forming a second semiconductor layer over the plurality of openings over the insulating layer and the insulating layer, and removing the first portion of the second semiconductor layer overlying the insulating layer. The second conductive type second portion of the second semiconductor layer remains on the upper portion of the plurality of openings in the insulating layer to form a plurality of pillar type diodes in the plurality of openings.
Another embodiment provides a method of fabricating a semiconductor device comprising forming a plurality of tungsten electrodes, nitriding the tungsten electrode to form a tungsten nitride barrier on the plurality of tungsten electrodes, Forming a plurality of semiconductor devices on the tungsten nitride barrier in the plurality of openings in the insulating layer; forming an insulating layer including a plurality of openings so that the insulating layer is exposed in the plurality of openings in the insulating layer;
Another embodiment provides a method of fabricating a semiconductor device comprising forming a plurality of tungsten electrodes, selectively forming a plurality of conductive barriers on an exposed upper surface of the tungsten electrode, Forming an insulating layer including a plurality of openings so that the barrier is exposed in the plurality of openings in the insulating layer; and forming a plurality of semiconductor devices on the conductive barrier in the plurality of openings.
Another embodiment provides a method of fabricating a semiconductor device comprising forming a plurality of lower electrodes on a substrate, forming a plurality of first openings having a first width to expose the lower electrode in the first openings, Forming a first semiconductor region of a first conductivity type in the first opening; forming a sacrificial material in the plurality of first openings on the first semiconductor region; Forming a plurality of second openings in the insulating layer having a second width greater than the first width to expose the first openings, removing the sacrificial material from the first openings through the second openings, Forming an upper electrode in the second opening in the insulating layer such that the upper electrode contacts the second semiconductor region, and forming an upper electrode in the second opening in the insulating layer, First to form a pillar shaped diodes in the first opening.
Another embodiment provides a method of fabricating a pillar device comprising providing an insulating layer having an opening and selectively depositing a germanium or germanium rich silicon germanium semiconductor material into the opening to form a pillar device.
The present invention has the effect of providing a pillar device and a method of manufacturing the device.
Figs. 1A, 1C, and 1E are side cross-sectional views illustrating the steps of forming a pillar apparatus according to the first embodiment of the present invention. Figs. 1B and 1D are cross- FIG.
2A to 2C are side cross-sectional views illustrating steps of forming a pillar apparatus according to a second embodiment of the present invention.
3A to 3E are side cross-sectional views illustrating steps of forming a pillar apparatus according to a third embodiment of the present invention;
Figures 3f-3g are photomicrographs of an exemplary device made according to the third embodiment;
4 is a three-dimensional view of a completed pillar apparatus in accordance with one or more embodiments of the invention.
5A is a plot of etch rate versus polysilicon doping in accordance with the prior art, and FIGS. 5B through 5E are side cross-sectional views illustrating steps of forming a pillar apparatus according to a fourth embodiment of the present invention.
6A to 6G are side cross-sectional views illustrating steps of forming a pillar apparatus according to a fifth embodiment of the present invention.
7A and 7B are side cross-sectional views of an apparatus feature made in accordance with an embodiment of the present invention.
8A to 8D are side cross-sectional views illustrating steps of forming a pillar apparatus according to an embodiment of the present invention.
Figure 8e is a three-dimensional view of a completed pillar apparatus in accordance with one embodiment of the present invention.
9A is a cross-sectional SEM image of a 40 nm thick Ge film deposited by GeH 4 for 10 minutes at 380 ° C and 1 torr on a silicon seed film deposited on TiN by SiH 4 decomposition at 380 ° C and 1 torr for 60 minutes. It is a video. FIG. 9B is a cross-sectional SEM image of the SiO 2 surface after the two-step SiH 4 and GeH 4 CVD processes, which are identical to each other, and no Ge deposition was observed on SiO 2 .
The present inventors have found that for semiconductor pillar devices having at least two regions of different conductivity types, such as diodes, including both p-type and n-type semiconductor regions, when such devices are formed in openings in an insulating layer, It should be noted that special steps have to be carried out to avoid short circuits.
For example, if the conductive barrier layer is simply deposited on the opening and then planarized, then the conductive barrier layer will extend along the side walls of the opening from the bottom of the opening to the top. Thereafter, when a semiconductor diode is deposited in the opening, the conductive barrier layer located along the sidewall of the opening shorts the p-type region of the diode to the n-type region of the diode.
Also, if the semiconductor layer of the diode is formed by a method such as low pressure chemical vapor deposition (LPCVD), then conformal deposition fills the opening from the bottom as well as the bottom. Thus, if the n-type semiconductor is deposited first in the opening, then it is also located along the entire sidewall of the opening or fills the entire opening. When the n-type region is located along the sidewall of the opening and the p-type region is located at the center of the opening, the upper electrode contacts both the p-type and n-type regions. When the n-type region fills the entire opening, there is no place to form a p-type region in the opening to form the diode thereafter.
Embodiments of the present invention provide a way to overcome these problems. In the first embodiment, a barrier layer is selectively formed so as not to short-circuit the diode formed in the opening in the insulating layer on the barrier. In the first embodiment of the first embodiment, the barrier layer may be formed by nitriding the lower tungsten electrode to form a tungsten nitride barrier layer before or after forming the insulating layer. If a tungsten nitride barrier is formed after the formation of the insulating layer, then the barrier layer is formed by nitriding a portion of the tungsten electrode exposed in the opening of the insulating layer. This nitridation step through the opening in the insulating layer is used to selectively form a tungsten nitride barrier layer on the bottom of the opening. In an alternative embodiment of the first embodiment, the barrier layer is formed by nitridation on the electrode prior to formation of the insulating layer.
In the second embodiment, the barrier layer is formed by selective deposition on the lower electrode. In the third embodiment, before forming the opposite conductivity type silicon layer in the space at the opening created by the recess etching, an optional silicon that can be precisely controlled to concave the one conductive type silicon layer at the opening A recess etch is used.
Figures 1 and 2 illustrate a method of fabricating a nitrided barrier layer according to an alternative embodiment of the first embodiment. Figs. 1A and 1B respectively show a side sectional view and a three-dimensional view of a plurality of
Figures 1C and 1D illustrate the step of nitriding the
Although tungsten is described as being used as the electrode (1) material, other materials such as titanium, tungsten silicide or aluminum may also be used. For example, the stability of a tungsten nitride layer formed by nitridation of a tungsten silicide surface is described in U.S. Patent No. 6,133,149, which is incorporated herein by reference in its entirety.
Plasma nitriding nitrides the entire exposed surface of the insulating
As shown in FIG. 1E, a second
A plurality of
Therefore, in the method of Figs. 1A to 1D, a nitriding step for forming the
Then, a plurality of semiconductor devices are formed on the
2A to 2C show an alternative embodiment of the first embodiment in which the insulating
Thus, the nitridation step is performed after forming the plurality of
Fig. 2C shows the formation of the
The advantage of performing nitridation after planarization of the
When the gas required for the plasma deposition reactor is supplied through the piping, plasma nitridation can be performed in the same chamber as the deposition of the insulating
The advantage of performing the nitriding after forming the
The
Both the non-limiting advantages of the nitriding described above (adhesion of the improved insulating
In the second embodiment, the
In an alternative method of the second embodiment, the conductive barrier is formed by selectively plating a barrier metal or a metal alloy on a plurality of tungsten electrodes. The plating may include electroless plating or electrolytic plating, which selectively plated the
The
The method according to the third embodiment of the present invention forms a pillar-like device such as a pillar diode in the
As shown in Fig. 3A, an insulating
The insulating
Next, the insulating
The
As shown in FIG. 3B, the top of the
Any suitable method can be used to remove the
For example, as shown in the micrograph of FIG. 3f, the recess etch step is an optional dry anisotropic etch step. In this step, the
Alternatively, as shown in FIG. 3G, a selective isotropic etch may be used to recess
A
When a p-i-n type diode is formed in the
A dopant of the opposite conductivity type to the conductivity type of the
Alternatively, by the method described in U.S. Application Publication No. 2006/0087005, entitled " Evaporated Semiconductor Structure Minimizing Diffusion of N-type Doping Agent and Method of Making It, " the title of which is hereby incorporated by reference in its entirety Dopant diffusion during subsequent intrinsic silicon deposition is prevented. In this method, an n-type semiconductor layer such as an n-type polysilicon or amorphous silicon layer is covered by a silicon-germanium cover layer having at least 10 atomic percent germanium. The cover layer may be from about 10 to about 20 nm thick, preferably less than about 50 nm thick, with little or no n-type dopant (i.e., the cover layer is preferably a thin intrinsic silicon-germanium layer Do). An intrinsic layer of a diode such as a silicon-germanium layer or a silicon layer with less than 10 atomic percent of germanium is deposited on the cover layer. Alternatively, a selective silicon rich oxide (SRO) layer is formed between the
In an exemplary embodiment, the
4, the
Next, another insulating layer (not shown for the sake of clarity) is deposited between and above the conductor rails 29. The insulating material may be any known electrically insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this insulating material. This insulating layer can be planarized together with the upper surface of the
A pillar device, such as a diode device, may include a one time programmable (OTP) or rewritable nonvolatile memory device. For example, each
In another embodiment, the
The formation of the first memory level has been described. Additional memory levels may be formed over the first memory level to form a monolithic three-dimensional memory array. In some embodiments, the conductors may be shared between memory levels, i.e., the
A monolithic three dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a wafer, without any substrate intervention. The layers forming one memory level are deposited or grown directly on top of existing levels or layers of levels. In contrast, stacked memory is constructed by forming memory levels on separate substrates, such as in Leedy, U. S. Patent No. 5,915, 167 "Three Dimensional Structure Memory ", and bonding these memory levels onto one another. Although the substrates may be thinned or removed from memory levels prior to bonding, such memories are not true monolithic three dimensional memory arrays, since memory levels are initially formed on separate substrates.
The monolithic three dimensional memory array formed on the substrate includes at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or virtually any number of memory levels may be formed on the substrate in such a multilevel array.
In a fourth embodiment of the present invention, alternative etching and doping steps are used to form a pillar-like device, such as
The depth of the high etch rate n-type doping layer can be tailored to the implant dose and energy. One method of optical etch endpoint detection includes monitoring a change in the intensity of a wavelength that is characteristic of a particular reactant or product of an etch reaction. When the etch end point is achieved, a lower density etch reaction product will be present in the plasma, so that the end point can be triggered and the etch can be stopped. Other etch endpoint detection uses a mass spectrometer for monitoring specific species in the exhaust stream from the dry etching reaction, referred to as RGA (residual gas analysis). The mass spectrometer may be located in or near the exhaust conduit of the etch reaction chamber. In this case, the RGA monitors the phosphorus-containing species in the exhaust stream and provides an end point signal or provides a trigger for the drop in this signal.
In the method of the fourth embodiment, the
The
Optical termination point detection can also be used to determine when the
In a fifth embodiment of the present invention, a sacrificial layer is used to form the pillar shaped device. Figures 6A-6G illustrate the steps of the method of the fifth embodiment.
First, a plurality of
6B, a
6C, the patterned photoresist is then patterned into a plurality of second openings 41 (one for clarity) in the insulating
As shown in FIG. 6D, the sacrificial material is selectively removed from the
Then, as shown in FIG. 6E, a second conductive type second semiconductor region is formed in the
The
6G, an upper electrode is formed in the
The pillar-shaped device may be formed using any one or more of the steps described above with respect to any one or more of the first to fifth embodiments. Depending on the process steps used, the finished device may have one or more of the following features shown in Figures 7A and 7B.
7A, the n-
7A, the
When the
Figure 7b shows the inset portion of Figure 7a around the
Another embodiment of the present invention provides a method of manufacturing a pillar device by selectively depositing a germanium or germanium rich silicon germanium pillar into a previously formed opening in an insulating layer to overcome the limitations of the subtractive method used in the prior art. The selective deposition method includes providing an electrically conductive material such as titanium nitride, tungsten, or other conductor exposed to the openings in the insulating layer. A silicon seed layer is then deposited on the titanium nitride. Thereafter, germanium or germanium rich silicon germanium (i.e., SiGe containing at least 50 atomic percent Ge) is selectively deposited on the silicon seed layer in the openings, without any germanium or germanium rich silicon germanium being deposited on the top surface of the insulating layer. Lt; / RTI > This removes the oxide CMP or etchback step used in the subtractive method. Preferably, the silicon seed layer and the germanium or germanium rich silicon germanium pillar are deposited by chemical vapor deposition at low temperatures, such as at temperatures below 440 캜.
Electrically conductive materials, such as titanium nitride, may be provided in the openings by any suitable method. For example, in one embodiment, a layer of titanium nitride is formed over the substrate, and then patterned photolithographically in a pattern. Alternatively, other materials such as titanium tungsten or tungsten nitride may be used instead of titanium nitride. The pattern may include an electrode, such as a rail-shaped electrode. An insulating layer is then formed on the titanium nitride pattern, such as a titanium nitride electrode. Thereafter, an opening is formed in the insulating layer by etching to expose the titanium nitride pattern. In an alternative embodiment, the conductive nitride pattern is selectively formed in the opening in the insulating layer. For example, a titanium nitride or tungsten nitride pattern can be selectively formed in the opening in the insulating layer by nitriding the titanium or tungsten layer exposed at the bottom of the opening.
The pillar device may include a portion of any suitable semiconductor device such as a diode, a transistor, and the like. Preferably the pillar device comprises a diode such as a p-i-n diode. In this embodiment, selectively depositing a germanium or germanium rich silicon germanium semiconductor material into the opening selectively deposits a semiconductor material of a first conductivity type (such as n-type) into the opening to form a pin diode, Selectively depositing an intrinsic germanium or germanium rich silicon germanium semiconductor material and subsequently selectively depositing a germanium or germanium rich germanium semiconductor material of a second conductivity type (such as p-type). Thus, all three regions of the p-i-n diodes are selectively deposited into the openings. Alternatively, in a less preferred embodiment, instead of selectively depositing a second conductivity type semiconductor material, a second semiconductor material such as a p-type dopant into the upper portion of the intrinsic germanium or germanium rich silicon germanium semiconductor material to form a pin diode The diode can be completed by injecting a dopant of a conductive type. Of course, the positions of the p-type and n-type regions can be reversed if necessary. A germanium or germanium rich silicon germanium semiconductor material of the first conductivity type (such as n-type) is selectively deposited into the opening to form a pn type diode, and subsequently a germanium or germanium rich silicon germanium semiconductor material of the second conductivity type Or a germanium-enriched silicon germanium semiconductor material is selectively deposited over the semiconductor material of the first conductivity type to form a diode.
Figures 8A-8D illustrate a preferred method of forming a pillared device using selective deposition.
Referring to FIG. 8A, an apparatus is formed on a
The first electrically
A
Finally, the
Next, referring to FIG. 8B, an insulating
The insulating
8C, a
For example, as illustrated in Figure 9a, the thin Si seed layer is deposited on TiN by flowing 500 sccm of SiH 4 for 60 minutes and at a pressure of 380
In a preferred embodiment, the pillar includes a semiconductor junction diode. The term junction diode is used herein to refer to a semiconductor device having non-ohmic conduction characteristics with two terminal electrodes, which are made of a semiconductor material that is p-type at one electrode and n-type at the other electrode Is used. An example would be an n-type semiconductor material and a p-type semiconductor material, such as a pin diode and a zener diode, in which an intrinsic (undoped) semiconductor material is interposed between the p-type semiconductor material and the n- Gt; np < / RTI > diode.
The bottom highly doped
The
In an exemplary embodiment, the
The pitch and width of the
8D, the
Next, another insulating
In the above description, the
A pillar device, such as a diode device, may include a one time programmable (OTP) or rewritable nonvolatile memory device. For example, each
In another embodiment, the
The formation of the first memory level has been described. Additional memory levels may be formed over the first memory level to form a monolithic three-dimensional memory array. In some embodiments, the conductors may be shared between memory levels, i.e., the
A monolithic three dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a wafer, without any substrate intervention. The layers forming one memory level are deposited or grown directly on top of existing levels or layers of levels. In contrast, a stacked memory is constructed by forming memory levels on separate substrates, such as in Lydy's U. S. Patent No. 5,915, 167 "Three Dimensional Structure Memory ", and bonding these memory levels onto one another. Although the substrates may be thinned or removed from memory levels prior to bonding, such memories are not true monolithic three dimensional memory arrays, since memory levels are initially formed on separate substrates. In contrast to the process described in Reddy, in an embodiment of the present invention, the diode shares a conductive wire or electrode between two adjacent layers. In this structure, the "bottom" diode will "orient" the opposite direction to the diode in the "top" layer (i.e., the layer of the same conductivity type in each diode is in electrical contact with the same wire or electrode located between the diodes) . In this structure, the two diodes can share the wire between them, but still have no read or write disturb problem.
The monolithic three dimensional memory array formed on the substrate includes at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or virtually any number of memory levels may be formed on the substrate in such a multilevel array.
In summary, a method of fabricating a germanium pillar device by selective deposition of Ge or Ge rich SiGe into an etched opening in an insulating layer has been described. By filling the semiconductor pillar openings, some difficulties of the conventional subtractive method are overcome and eight processing steps can be eliminated in a four layer device. For example, a high aspect ratio oxide gap filling between the pillars may be omitted, which allows for the deposition of a simple blanket oxide film with good uniformity. A higher germanium pillar can be made with a depth of 8 microns in the deep opening in the insulating layer. The high diode reduces reverse leakage of the vertical device. In addition, alignment of the various layers becomes easier. All layers can be aligned to the main alignment mark without intermediate open frame etching.
On the basis of the teachings of the present invention, those skilled in the art are expected to be able to easily carry out the present invention. The description of the various embodiments provided herein is believed to provide those of ordinary skill in the art with a broad overview and detailed description of the invention. Although specific support circuits and fabrication steps have not been described in detail, such circuits and protocols are well known and no particular advantage is provided by specific modifications of these steps in the practice of the invention. It is also believed that one skilled in the art can, without undue experimentation, perform the present invention based on the teachings herein.
The foregoing detailed description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended to be illustrative, not limiting. Modifications and variations of the embodiments described herein may be made without departing from the spirit and scope of the invention based on the description provided herein. Only the following claims, including all equivalents, are intended to define the scope of the invention.
Claims (66)
Providing a substrate comprising a conductive material and including a plurality of first conductive electrodes separated from each other by a first insulating layer;
Forming a second insulating layer including a plurality of openings,
The second insulating layer being located on the substrate,
Wherein a first portion of an upper surface of the plurality of first conductive electrodes is physically exposed below the plurality of openings,
And a second portion of the upper surface of the plurality of first conductive electrodes is covered by the second insulating layer
Forming the second insulating layer;
Forming a first semiconductor layer in a plurality of openings on the second insulating layer and the second insulating layer;
Removing a first portion of the first semiconductor layer,
The first conductive type second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the second insulating layer,
The upper portions of the plurality of openings in the second insulating layer remain uncharged
Removing a first portion of the first semiconductor layer,
Forming a second semiconductor layer on top of the plurality of openings on the second insulating layer and the second insulating layer;
Removing the first portion of the second semiconductor layer located above the second insulating layer
Including,
The second conductive type second portion of the second semiconductor layer remains on the upper portion of the plurality of openings in the second insulating layer to form a plurality of pillar type diodes in the plurality of openings,
Each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the conductive material of the plurality of first conductive electrodes,
Wherein each pn junction in the plurality of pillar-shaped diodes is vertically spaced from the plurality of first conductive electrodes by a first conductive type second portion of the first semiconductor layer.
Wherein selectively etching the first semiconductor layer comprises etching a doped portion of the first semiconductor layer until the intrinsic portion of the first semiconductor layer is reached.
Doping the intrinsic portion of the first semiconductor layer with the dopant of the first conductivity type after the selective etching step
≪ / RTI >
Forming the second semiconductor layer including an intrinsic semiconductor material over the second insulating layer and over the plurality of openings;
Planarizing the second semiconductor layer with at least the upper surface of the second insulating layer using chemical mechanical polishing or etchback;
implanting the dopant of the second conductivity type into the upper section of the second portion of the second semiconductor layer to form a pin-
≪ / RTI >
Planarizing the first semiconductor layer with a top surface of the second insulating layer using chemical mechanical polishing or etchback with optical termination point detection,
And after the planarization step, the second portion of the first semiconductor layer remaining in the plurality of openings has a substantially planar top surface, the step of recessing the first semiconductor layer in the plurality of openings in the second insulating layer Selectively anisotropically etching the first semiconductor layer remaining on top of the plurality of openings in the second insulating layer with a level etch front
≪ / RTI >
Planarizing the first semiconductor layer with an upper portion of the second insulating layer using chemical mechanical polishing or etchback with optical termination point detection,
After the planarization step, the second portion of the first semiconductor layer remaining in the plurality of openings has an annular shape with a groove in the center portion so that the second semiconductor layer is recessed in the plurality of openings in the second insulating layer, Selectively etching the first semiconductor layer remaining on the upper portion of the plurality of openings in the insulating layer;
≪ / RTI >
The n-type region of the diode comprising a first vertical junction,
Wherein the p-type region of the diode comprises a second vertical junction,
Wherein the first and second vertical joint lines are not in contact with each other.
Wherein the plurality of first conductive electrodes are tungsten electrodes under the second insulating layer,
And the tungsten electrode is nitrided to form a tungsten nitride barrier exposed in the plurality of openings in the second insulating layer.
Forming a plurality of tungsten electrodes separated from each other by a first insulating layer;
Nitriding the tungsten electrode to form a tungsten nitride barrier on the plurality of tungsten electrodes;
Forming a second insulating layer including a plurality of openings,
The tungsten nitride barrier is exposed to the plurality of openings in the second insulating layer,
A part of the upper surface of the plurality of tungsten electrodes is covered with the second insulating layer
Forming the second insulating layer;
And forming a plurality of pillar-shaped diodes on the tungsten nitride barrier in the plurality of openings in the second insulating layer,
Wherein each of the plurality of pillar type diodes includes a first semiconductor region having a first conductivity type of doping and a second semiconductor region having a second conductivity type of doping,
Each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the plurality of tungsten electrodes,
Wherein each pn junction in the plurality of pillar-shaped diodes is vertically spaced from the plurality of tungsten electrodes by respective first semiconductor regions.
Forming a first semiconductor layer of a first conductivity type on the plurality of openings on the second insulating layer and the second insulating layer;
The second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the second insulating layer to form the first semiconductor region and the upper portion of the plurality of openings in the second insulating layer remains uncharged Removing a first portion of the first semiconductor layer,
Forming a second conductive type second semiconductor layer on the plurality of openings in the second insulating layer;
≪ / RTI >
The forming of the second insulating layer may include forming the second insulating layer on the plurality of tungsten electrodes, and subsequently forming a plurality of openings in the second insulating layer so as to expose the upper surface of the plurality of tungsten electrodes ; And
Wherein the nitriding step is performed after the step of forming the plurality of openings in the second insulating layer so that the upper surface of the plurality of tungsten electrodes is nitrided through the plurality of openings in the second insulating layer.
The plurality of openings in the second insulating layer are partially misaligned with the plurality of tungsten electrodes,
The step of forming the plurality of openings exposes at least a portion of the side wall of the tungsten electrode,
Wherein the nitriding step forms a tungsten nitride barrier on exposed portions of the sidewalls of the plurality of tungsten electrodes and on the upper surface.
The nitriding step is performed prior to the step of forming the second insulating layer,
Wherein forming the second insulating layer comprises forming the second insulating layer on the tungsten nitride barrier and subsequently forming a plurality of openings in the second insulating layer to expose the top surface of the tungsten nitride barrier And forming a gate electrode on the semiconductor substrate.
Forming a plurality of tungsten electrodes separated from each other by a first insulating layer;
Selectively forming a plurality of conductive barriers on the exposed upper surface of the tungsten electrode;
Forming a second insulating layer including a plurality of openings,
The plurality of conductive barriers are exposed to the plurality of openings in the second insulating layer,
A part of the upper surface of the plurality of tungsten electrodes is covered with the second insulating layer
Forming the second insulating layer;
And forming a plurality of pillar-shaped diodes on the conductive barrier in the plurality of openings,
Wherein each of the plurality of pillar type diodes includes a first semiconductor region having a first conductivity type of doping and a second semiconductor region having a second conductivity type of doping,
Each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the plurality of tungsten electrodes,
Wherein each pn junction in the plurality of pillar-shaped diodes is vertically spaced from the plurality of tungsten electrodes by respective first semiconductor regions.
Wherein forming the plurality of pillar type diodes comprises:
Forming a first semiconductor layer of a first conductivity type in a plurality of openings above the second insulating layer and the second insulating layer;
The second portion of the first semiconductor layer remains in the lower portion of the plurality of openings in the second insulating layer and the upper portion of the plurality of openings in the second insulating layer remains unfilled. 1 < / RTI >
Forming a second conductive type second semiconductor layer on the plurality of openings in the second insulating layer;
≪ / RTI >
The forming of the second insulating layer may include forming the second insulating layer on the plurality of tungsten electrodes, and subsequently forming a plurality of tungsten electrodes on the second insulating layer to expose the upper surface of the plurality of tungsten electrodes. And forming an opening,
The step of selectively forming a plurality of conductive barriers such that a plurality of conductive barriers are selectively formed on the upper surface of the plurality of tungsten electrodes through the plurality of openings in the second insulating layer comprises: After the step of forming the semiconductor device.
The plurality of openings in the second insulating layer are partially misaligned with the plurality of tungsten electrodes,
Wherein forming the plurality of openings exposes at least portions of the sidewalls of the tungsten electrode,
Wherein selectively forming the plurality of conductive barriers forms a conductive barrier on the exposed portions of the sidewalls of the plurality of tungsten electrodes and on the top surface thereof.
Wherein the step of selectively forming the plurality of conductive barriers is performed prior to the step of forming the second insulating layer,
Wherein forming the second insulating layer comprises forming the second insulating layer on the plurality of conductive barriers, and subsequently forming the second insulating layer on the second insulating layer to expose the upper surface of the plurality of conductive barriers. And forming an opening of the semiconductor device.
Forming a plurality of lower electrodes separated from each other by a first insulating layer on a substrate,
Forming a second insulating layer including a plurality of first openings having a first width such that the lower electrode is exposed to the first openings;
Forming a first semiconductor region of a first conductivity type in the first opening;
Forming a sacrificial material in the plurality of first openings on the first semiconductor region,
Forming a plurality of second openings in the second insulating layer to expose the sacrificial material, the second openings having a second width greater than the first width;
Removing the sacrificial material from the first opening through the second opening;
Forming a second conductive type second semiconductor region in the first opening,
Wherein the first and second semiconductor regions form a plurality of pillar-shaped diodes in the first opening,
Wherein each of the plurality of pillar-shaped diodes is located on a horizontal plane including an upper surface of the plurality of lower electrodes,
Each pn junction in the plurality of pillar-shaped diodes is vertically separated from the plurality of lower electrodes by respective first semiconductor regions
Forming the second semiconductor region;
And forming an upper electrode in the second opening in the second insulating layer so that the upper electrode contacts the second semiconductor region.
Wherein the forming of the first semiconductor region comprises: forming a first semiconductor layer in the plurality of first openings above the second insulating layer and the second insulating layer; Removing a portion of the first semiconductor layer so as to remain at a lower portion of the first opening and to leave the upper portion of the plurality of first openings unfilled,
Forming a second semiconductor region includes forming a second semiconductor layer on top of the plurality of first openings above the second insulating layer and the second insulating layer and subsequently forming a second semiconductor layer on the second semiconductor region, Removing a portion of the second semiconductor layer located above the second insulating layer so as to remain on top of the plurality of first openings in the insulating layer.
A plurality of first conductive electrodes separated from each other by a first insulating layer;
A second insulating layer overlying the first insulating layer and surrounding the sides of the plurality of pillar-shaped semiconductor diodes; And
And a plurality of second electrodes in contact with the region of the second conductivity type,
Wherein each of the plurality of pillar type semiconductor diodes is located on a horizontal plane including an upper surface of the plurality of first conductive electrodes,
Wherein each pn junction in the plurality of pillar-shaped semiconductor diodes is vertically spaced from the plurality of first conductive electrodes by a respective region of a first conductivity type,
a) the region of the first conductivity type of the diode comprises a first vertical junction line, and the region of the second conductivity type of the diode comprises a second vertical junction line, wherein the first and second junction lines do not contact each other , or
b) the sidewall of the region of the first conductivity type has a taper angle different from the sidewall of the region of the second conductivity type, and the discrete portion is located on the sidewall of the diode.
The region of the first conductivity type has a narrower taper angle than the region of the second conductivity type,
An intrinsic semiconductor region is located between the first and second conductivity type regions,
Wherein the discontinuous portion includes a step on a sidewall of the diode between the intrinsic semiconductor region and the region of the first conductivity type.
a) the region of the first conductivity type of the diode comprises a first vertical junction line, the region of the second conductivity type of the diode comprises a second vertical junction line, the first and second junction lines do not contact each other,
b) the sidewall of the region of the first conductivity type has a taper angle different from the sidewall of the region of the second conductivity type, and the discrete portion is located on the sidewall of the diode.
Tungsten electrode;
A tungsten nitride barrier on said tungsten electrode;
A pillar type diode located on the tungsten nitride barrier; And
And an upper electrode disposed on the pillar type diode,
The pillar type diode comprising a first semiconductor region having a first conductivity type of doping and a second semiconductor region having a second conductivity type of doping,
Wherein the pillar type diode is located on a horizontal plane including an upper surface of the tungsten electrode,
Wherein the pn junction in the pillar-shaped diode is vertically spaced from the tungsten electrode by the first semiconductor region.
Forming a titanium nitride pattern on a plurality of first conductive electrodes separated from each other by a first insulating layer on a substrate;
Forming a second insulating layer on the titanium nitride pattern;
Forming an opening in the second insulating layer to expose the titanium nitride pattern;
Forming a silicon seed layer in an opening portion on the titanium nitride pattern,
Selectively depositing a silicon germanium material containing a first conductivity type of germanium or 50 atomic percent or more germanium on the silicon seed layer at the opening,
Selectively depositing a silicon germanium material containing intrinsic germanium or more than 50 atomic percent germanium on the silicon germanium material containing germanium of the first conductivity type or germanium of at least 50 atomic percent,
implanting a dopant of the second conductivity type into the upper portion of the silicon germanium material containing germanium of the first conductivity type or germanium of greater than 50 atom percent to form a pin diode,
Wherein each of the plurality of the filament diodes is located on a horizontal plane including an upper surface of the plurality of first conductive electrodes,
Wherein each intrinsic semiconductor material portion in the plurality of the pillar diodes is vertically spaced from the plurality of first conductive electrodes by a respective portion of the first conductive type germanium or silicon germanium material portion containing at least 50 atomic percent germanium , A method for manufacturing a pillar diode.
Providing a plurality of first conductive electrodes separated from each other by a first insulating layer;
Forming a second insulating layer having an opening,
Selectively depositing a silicon germanium material containing germanium or at least 50 atomic percent germanium into the opening to form a pillar device surrounded by the second insulating layer,
The pillar device comprising a first semiconductor region having a doping of a first conductivity type and a second semiconductor region overlying the first semiconductor region and having a doping of a second conductivity type,
The pillar device is selected from a pn diode and a pin diode,
Wherein the pillar device is located on a horizontal plane including an upper surface of the plurality of first conductive electrodes,
Wherein the pn junction or intrinsic semiconductor material portion in the pillar device is vertically separated from the plurality of first conductive electrodes by the first semiconductor region.
Forming a titanium nitride, titanium tungsten, or tungsten nitride pattern on the substrate;
Forming a second insulating layer on the titanium nitride, titanium tungsten, or tungsten nitride pattern;
Forming an opening in the second insulating layer to expose the titanium nitride, titanium tungsten, or tungsten nitride pattern
≪ / RTI >
Forming the second insulating layer on the substrate;
Forming an opening in the second insulating layer;
Selectively forming a pattern of titanium nitride, titanium tungsten, or tungsten nitride in the opening
≪ / RTI >
Selectively depositing a silicon germanium material containing intrinsic germanium or greater than 50 atomic percent germanium into the opening in the material of the first conductivity type,
implanting a dopant of the second conductivity type into the upper portion of the silicon germanium material containing intrinsic germanium or greater than 50 atomic percent germanium to form a pin diode
≪ / RTI >
Selectively depositing a silicon germanium material containing intrinsic germanium or more than 50 atomic percent germanium into the opening on the first conductive semiconductor material,
selectively depositing a silicon germanium material containing a germanium of the second conductivity type or greater than 50 atomic percent germanium into the opening on the silicon germanium material containing the intrinsic germanium or the germanium of greater than 50 atomic percent to form a pin diode
≪ / RTI >
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US12/007,781 US7906392B2 (en) | 2008-01-15 | 2008-01-15 | Pillar devices and methods of making thereof |
US12/007,780 US7745312B2 (en) | 2008-01-15 | 2008-01-15 | Selective germanium deposition for pillar devices |
US12/007,780 | 2008-01-15 | ||
US12/007,781 | 2008-01-15 |
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US8097498B2 (en) | 2010-01-25 | 2012-01-17 | Sandisk 3D Llc | Damascene method of making a nonvolatile memory device |
US8879299B2 (en) | 2011-10-17 | 2014-11-04 | Sandisk 3D Llc | Non-volatile memory cell containing an in-cell resistor |
US8710481B2 (en) | 2012-01-23 | 2014-04-29 | Sandisk 3D Llc | Non-volatile memory cell containing a nano-rail electrode |
WO2018159186A1 (en) * | 2017-02-28 | 2018-09-07 | 富士フイルム株式会社 | Semiconductor device, laminate, semiconductor device manufacturing method, and laminate manufacturing method |
US10199434B1 (en) | 2018-02-05 | 2019-02-05 | Sandisk Technologies Llc | Three-dimensional cross rail phase change memory device and method of manufacturing the same |
US10381366B1 (en) | 2018-02-17 | 2019-08-13 | Sandisk Technologies Llc | Air gap three-dimensional cross rail memory device and method of making thereof |
US10468596B2 (en) | 2018-02-21 | 2019-11-05 | Sandisk Technologies Llc | Damascene process for forming three-dimensional cross rail phase change memory devices |
US10580976B2 (en) | 2018-03-19 | 2020-03-03 | Sandisk Technologies Llc | Three-dimensional phase change memory device having a laterally constricted element and method of making the same |
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US5831276A (en) * | 1995-06-07 | 1998-11-03 | Micron Technology, Inc. | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell |
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US7800932B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Memory cell comprising switchable semiconductor memory element with trimmable resistance |
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US7410838B2 (en) * | 2004-04-29 | 2008-08-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fabrication methods for memory cells |
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