KR101570928B1 - Electrostatic Discharge Device of using Lateral Insulated Gate Bipolar Transistor having lower Trigger Voltage - Google Patents
Electrostatic Discharge Device of using Lateral Insulated Gate Bipolar Transistor having lower Trigger Voltage Download PDFInfo
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- KR101570928B1 KR101570928B1 KR1020140039461A KR20140039461A KR101570928B1 KR 101570928 B1 KR101570928 B1 KR 101570928B1 KR 1020140039461 A KR1020140039461 A KR 1020140039461A KR 20140039461 A KR20140039461 A KR 20140039461A KR 101570928 B1 KR101570928 B1 KR 101570928B1
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Abstract
An electrostatic discharge protection device capable of entering a holding area at a low trigger voltage to perform a stable operation is disclosed. A first P-well active region, an N-well active region and a second P-well active region are formed on the deep N-well region. The first P-well active region is electrically connected to the second P-well active region through the wiring. In addition, the spacing distance between the first P-well active region and the N-well active region is greater than the separation distance between the N-well active region and the second P-well active region. Thus, a punch-through phenomenon occurs between the N-well active region and the second P-well active region, and an equivalent circuit of the diode is formed. This allows the electrostatic discharge protectors to enter the holding area quickly even at low trigger voltages.
Description
The present invention relates to electrostatic discharge protection, and more particularly, to an electrostatic discharge protection device having a low trigger voltage based on a lateral insulated gate bipolar transistor having a forward diode region.
An electrostatic discharge protection device is an element that protects a semiconductor circuit in a situation where an undesired high voltage such as static electricity is applied among semiconductor elements. The electrostatic discharge protection device is connected to an input terminal of a semiconductor circuit performing a specific function, and maintains the off state when a voltage or a signal having a normal level is applied. In addition, when a surge voltage is applied, the electrostatic discharge protection device turns on and flows a current corresponding to a voltage applied to the ground or the like. This function performs the function of protecting the semiconductor circuit.
The voltage level at which the electrostatic discharge protection device is turned on and starts operation is referred to as a trigger point. Also, a region where a constant voltage state is maintained in a turned-on state is referred to as a holding region. Therefore, when a high level voltage is applied to the semiconductor element by static electricity or the like, the electrostatic discharge protection element operates in the holding area, and the large current flows to the ground through the electrostatic discharge protection element. Therefore, the internal circuit of the chip in which the semiconductor circuit is implemented is protected from impact by static electricity or the like.
1 is a cross-sectional view illustrating an electrostatic discharge protection device using a lateral insulated gate bipolar transistor (LIGBT) according to a related art.
Referring to FIG. 1, a deep N-
The P-well active region has a P-
The N-well active region has an N-
Further, the
The first P-
If the voltage applied through the anode terminal is below the trigger level, the electrostatic discharge protection device does not start operation. This is because the N +
When the voltage at the anode terminal rises, the depletion region expands between the P-
The electrostatic discharge protector of FIG. 1 described above serves as an important element of the depletion region expansion operation for the deep N-
In addition, the deep N-
Therefore, an electrostatic discharge protection device capable of ensuring a stable holding area with a low trigger level will be required.
SUMMARY OF THE INVENTION The present invention provides an electrostatic discharge protection device capable of performing stable operation even at a low trigger voltage.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a deep N-well region formed on a P-type substrate; A first P-well active region formed on the deep N-well region and interrupting the flow of current when a voltage with a negative trigger voltage is applied to the anode terminal; An N-well active region formed on the deep N-well region and formed at a distance L1 on a side of the first P-well region, the N-well active region being connected to the anode terminal and modeled with a forward diode for a voltage applied; Well region and formed on the side of the N-well region with a spacing distance L2 that is smaller than the spacing distance L1, wherein the pinch-and-well region of the deep N- And a second P-well active region for inducing an OFF phenomenon.
According to the present invention described above, a pinch-off phenomenon occurs between the N-well active region and the second P-well active region. Thus, it is possible to quickly enter the holding region before the pinch-off phenomenon occurs between the first P-well active region and the N-well active region. This means that at low trigger voltages, the electrostatic discharge protectors enter the holding area.
Thus, the semiconductor device can be protected by entering the holding region at a relatively low surge voltage, and stable operation can be ensured.
1 is a cross-sectional view illustrating an electrostatic discharge protection device using a lateral insulated gate bipolar transistor (LIGBT) according to a related art.
2 is a cross-sectional view illustrating an electrostatic discharge protection device according to a preferred embodiment of the present invention.
FIG. 3 is a circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.
4 is another circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.
5 is a graph for explaining the effects of the electrostatic discharge protection device of FIGS. 2 to 4 according to a preferred embodiment of the present invention.
The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.
Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example
2 is a cross-sectional view illustrating an electrostatic discharge protection device according to a preferred embodiment of the present invention.
Referring to FIG. 2, a deep N-
The first P-well
An N-well
A second P-well
An insulating
In addition, the insulating
In addition, when a bias is not applied to the anode terminal, the distance L1 between the first P-
Well
When the anode voltage continues to increase, a phenomenon that only the depletion region appears between the N-
When the current path is formed between the N-well
FIG. 3 is a circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.
Referring to FIG. 3, it is assumed that a voltage difference less than the trigger voltage is applied between the anode terminal and the cathode terminal. Therefore, the punch-through phenomenon does not occur.
The electrostatic discharge protection capacitor is modeled as three transistors Q1, Q2 and Q3 and one diode D.
The emitter terminal of the first transistor Q1 is connected to the cathode terminal, the collector terminal is connected to the second node N2, and the base terminal is connected to the first node N1. The emitter terminal is modeled as a first N +
The collector terminal of the second transistor Q2 is connected to the first node N1, the base terminal is connected to the second node N2, and the emitter terminal is connected to the third node N3 via the resistor R2. And the third node N3 is a model of the third P +
The emitter terminal of the third transistor Q3 is connected to the third node N3 through the resistor R3, the base terminal is connected to the second node N2, and the collector terminal is connected to the fourth node N4. The fourth node N4 is a model of the second P-
Further, the diode D is connected between the fourth node N4 and the first node N1 via the resistor R4. The resistor R 4 is a model of resistance between the second P +
In the above circuit diagram, the cathode terminal is connected to the ground and the voltage is applied to the anode terminal. The applied voltage is set to be less than the trigger voltage. A positive bias is applied between the third node N3 and the second node N2. However, a reverse bias is applied between the second node N2, which is the base terminal of the second transistor Q2, and the first node N1, which is the collector terminal. A reverse bias is also applied between the second node N2, which is the base terminal of the third transistor Q3, and the fourth node N4, which is the collector terminal. Therefore, the second transistor Q2 and the third transistor Q3 maintain the OFF state. Also, even if a bias is applied through the second node N2, the voltage applied to the anode terminal by the first transistor Q1 which is in the reverse bias state is not transmitted to the cathode terminal.
4 is another circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.
Referring to FIG. 4, a circuit diagram modeling the operation of FIG. 2 when the voltage applied to the anode terminal is equal to or greater than the trigger voltage is disclosed.
4, the connection relationship between the first transistor Q1 and the second transistor Q2 is the same as that described in FIG. However, the third transistor Q3 is omitted, and the voltage drop means is shown. That is, between the third P +
When a voltage equal to or higher than the trigger voltage is applied to the anode terminal, a punch-through phenomenon occurs between the N-well
Therefore, when a voltage equal to or higher than the trigger voltage is applied through the anode terminal, the current path through the third node N3, the voltage drop means 200, the diode D, the resistor R4, the first node N1, . Therefore, the applied voltage drops to the holding voltage and the constant voltage state is maintained.
5 is a graph for explaining the effects of the electrostatic discharge protection device of FIGS. 2 to 4 according to a preferred embodiment of the present invention.
5, dotted lines indicate characteristics of the electrostatic discharge protection element having the configuration of FIG. 1, and solid lines show characteristics of the electrostatic discharge protection element having the configuration of FIG. 2 of the present invention.
First, in the configuration of FIG. 1, the punch-through operation occurs in the deep N-
However, in FIG. 2 of the present invention, punch-through occurs between the N-well
Therefore, when the electrostatic discharge protection device enters the holding state, the holding voltage Vh is set, and the holding current Ih is maintained to be increased or decreased according to the applied anode voltage.
Therefore, the electrostatic discharge protection device of the present invention can perform stable operation for a high voltage to which a high surge voltage is applied or a semiconductor device is damaged.
110: deep N-well region 120: first P-well active region
130: N-well active region 140: Second P-well active region
Claims (5)
A first P-well active region formed on the deep N-well region and connected to the cathode terminal to block the flow of current when a voltage of a negative trigger voltage is applied to the anode terminal;
An N-well active region formed on the deep N-well region and formed with a distance L1 on a side of the first P-well active region, the N-well active region being connected to the anode terminal and modeled with a forward diode for a voltage applied; And
Well active region and is formed on the deep N-well region and is opposed to the first P-well active region about the N-well active region, And a second P-well active region electrically coupled to the first P-well active region, the second P-well active region being formed in the second P-well active region and inducing a punch-through phenomenon in the deep N- Discharge protection device.
A first P-well region formed on the deep N-well region and forming a reverse diode with the deep N-well region for a voltage applied to the anode terminal;
A first P + region formed on the first P-well region and connected to the cathode terminal;
A first N + region formed on the first P-well region and connected to the cathode terminal;
And a second P + well region formed on the first P-well region and electrically connected to the second P-well active region to supply a current to the cathode terminal when a level equal to or higher than a trigger voltage is applied to the anode terminal, Wherein the first and second electrodes are electrically connected to each other.
An N-well region formed on the deep N-well region and communicating a voltage coupled to the anode terminal to the deep N-well region; And
And a third P + region formed on the N-well region and forming a forward diode with the N-well region for a voltage applied through the anode terminal.
A second P-well region formed on the deep N-well region and forming a deep N-well region and a reverse diode; And
And a second N + region formed on the second P-well region and electrically connected to the first P-well active region.
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KR101031799B1 (en) * | 2009-05-28 | 2011-04-29 | 주식회사 바우압텍 | Electro-Static Discharge Protection Device |
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KR101031799B1 (en) * | 2009-05-28 | 2011-04-29 | 주식회사 바우압텍 | Electro-Static Discharge Protection Device |
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