KR101523991B1 - Nitride-Based Power Semiconductor Device and Manufacturing Method therefor - Google Patents

Nitride-Based Power Semiconductor Device and Manufacturing Method therefor Download PDF

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KR101523991B1
KR101523991B1 KR1020140025965A KR20140025965A KR101523991B1 KR 101523991 B1 KR101523991 B1 KR 101523991B1 KR 1020140025965 A KR1020140025965 A KR 1020140025965A KR 20140025965 A KR20140025965 A KR 20140025965A KR 101523991 B1 KR101523991 B1 KR 101523991B1
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layer
nitride
substrate
thin film
based thin
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KR1020140025965A
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Korean (ko)
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송근만
김종민
고유민
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(재)한국나노기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

According to an aspect of the present invention, a nitride-based power semiconductor device includes a single crystal substrate; a dielectric layer which is deposited on the substrate and has a pattern to expose part of the substrate; a buffer layer which is deposited on the exposed region of the substrate; and a device layer which includes a 2 dimensional electron gas layer (2DEG layer) which is deposited on the buffer layer and is bonded with different material layers. According to the present invention like this, a heterogeneous semiconductor is vertically grown in a region with a predetermined width and length. Thereby, a device having no defect can be manufactured.

Description

[0001] NITRIDE-BASED POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME [0002]

The present invention relates to a nitride-based power semiconductor device and a manufacturing method therefor, and more particularly, to a nitride-based power semiconductor structure grown in the form of a three-dimensional surface or a rod in order to reduce defects and a manufacturing method therefor.

A high electron mobility transistor (hereinafter referred to as HEMT) uses a two-dimensional electron gas (hereinafter, 2DEG) generated at the interface of a heterojunction structure as a carrier Device. In a heterojunction structure, that is, a structure in which two semiconductor layers having different polarization ratios are bonded, a semiconductor layer having a relatively high polarization ratio may induce a 2DEG in another semiconductor layer bonded thereto. 2DEGs generally have very high electron mobility. Therefore, when 2DEG is used as a channel in a HEMT, it is advantageous in response speed, signal precision, and the like.

The performance / characteristics of semiconductor devices using 2DEG, such as HEMT, are affected by the electron concentration and resistance of 2DEG. The higher the electron concentration of the 2DEG, the more advantageous it is to realize a high output / high performance device with high current density.

The nitride semiconductors, which are typical semiconductors made of HEMT, are fabricated by growing epitaxial films on sapphire or silicon substrates using MOCVD (Metal-Organic Chamical Vapor Deposition). In this case, due to the lattice constant mismatch, many crystal defects are contained in the nitride semiconductor. These defects not only adversely affect the flow of electrons, but also reduce the reliability of the device response, so efforts have been made to reduce defects.

1 is a cross-sectional view showing a defect occurring in a conventional heterojunction device.

When GaN is grown on a silicon substrate and a heterogeneous material such as AlN or InN is grown thereon, a difference in lattice constant occurs between silicon and GaN. Therefore, And a defect occurs.

Korean Patent Laid-Open No. 10-2008-0040709 entitled "Lateral Growth Method for Reducing Defects in Semipolar Nitride Thin Films" discloses a method of inducing overgrowth in the lateral direction to reduce defects.

However, in such a conventional technique, defects still exist because there is a difference in lattice constant even when excessive growth is induced in the lateral direction.

Therefore, it is necessary to fabricate a device with less overlapping lattice constant difference.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a nitride-based power semiconductor device in which a contact area of a heterogeneous material and a substrate is limited so as not to increase a difference in lattice constant, And to provide a manufacturing method therefor.

Further, it is an object of the present invention to provide a nitride-based power semiconductor device in which a 2DEG is generated to rapidly increase a reaction speed and grown in a three-dimensional plane or rod shape, and a manufacturing method therefor.

According to an aspect of the present invention, there is provided a substrate, which is a single crystal substrate; A dielectric layer formed on the substrate and patterned to expose a portion of the substrate; A buffer layer formed on the exposed region of the substrate, and an element layer including a 2DEG layer (2DEG electron layer (2DEG) layer deposited on the buffer layer and having a band gap different from that of the 2DEG layer And a nitride based power semiconductor device.

Here, the exposed region may be smaller than a threshold size at which defects are generated in the process of depositing the buffer layer.

Here, the buffer layer and the element layer may be formed in parallel with the substrate.

Here, the buffer layer is grown higher than the dielectric layer, and the device layer may cover the surface of the buffer layer.

Here, a source, a drain, and a gate electrode may be formed on the surface of the element layer. Here, the buffer layer may have a multi-layer structure to prevent defects generated between the substrate and the buffer layer from growing into an element layer.

Here, the 2DEG layer may be a layer in which a nitride-based thin film layer and a hetero-material layer are bonded.

Here, the nitride-based thin film layer may be AlGaN and the hetero-material layer may be GaN.

Here, the nitride-based thin film layer may be GaN and the dissimilar material layer may be AlInN.

Here, the substrate may be any one of a silicon substrate, a silicon carbide substrate, and an aluminum oxide substrate.

Here, the pattern may be repeatedly formed in a rectangular shape.

Here, the nitride based power semiconductor device may further include a core layer between the substrate and the buffer layer, and the lattice constant of the core layer may have a value between the lattice constant of the substrate and the buffer layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a dielectric layer deposition step of depositing a dielectric layer on a substrate; A patterning step of patterning the dielectric layer to expose a part of the substrate; A nitride-based thin film layer growth step of growing a nitride-based thin film layer on the exposed region of the substrate; The method comprising the steps of: growing a hetero-material layer on the nitride-based thin film layer; and forming a terminal for connecting source, gate and drain terminals to the hetero-material layer. to provide.

Here, the method may further include a buffer layer growth step between the patterning step and the nitride-based thin film layer growth step, wherein the buffer layer growth step grows a buffer layer on the exposed region of the substrate, and in the nitride- A thin film layer may be grown on the buffer layer.

Here, the patterning may use lithography or imprinting.

Here, the nitride-based thin film layer growth step or the hetero-material layer growth step may be implemented using MOCVD (Metal-Organic Chamical Vapor Deposition).

Here, the nitride-based thin film layer may be AlGaN and the hetero-material layer may be GaN.

Here, the nitride-based thin film layer may be GaN and the dissimilar material layer may be AlInN.

Here, the terminal forming step may form the source, gate, and drain terminals using a lithography process.

According to the present invention as described above, the hetero semiconductor is grown on the substrate in a limited region, thereby producing an element in which no defect occurs.

In addition, a plurality of nitride based power semiconductor structures can be fabricated at one time by depositing and patterning a dielectric layer on the substrate.

Also, by connecting electrodes to the surface of the fabricated nitride based power semiconductor device, the entire surface of the nitride based power semiconductor structure can be utilized as a 2DEG layer.

1 is a cross-sectional view of a coupling surface showing a defect occurring in a conventional heterojunction device.
2 is a side view of a nitride-based power semiconductor device according to an embodiment of the present invention.
3 is a cross-sectional view of a nitride-based power semiconductor device according to an embodiment of the present invention.
4 is a cross-sectional view of a parallel nitride based power semiconductor device according to an embodiment of the present invention.
5 is a perspective view of a modular nitride based power semiconductor in accordance with an embodiment of the present invention.
6 and 7 are perspective views of a substrate including a regularly fabricated nitride based power semiconductor according to an embodiment of the present invention.
8 is a flowchart illustrating a method of fabricating a nitride-based power semiconductor device according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a device fabricated during each of the dielectric deposition step and the patterning step.
10 is a cross-sectional view of a nitride-based power semiconductor structure in which a core layer is formed in a semiconductor thin film growth step according to an embodiment of the present invention.
11 is a cross-sectional view of a nitride-based power semiconductor device in which a hetero-material layer is formed in a hetero-material layer growth step according to an embodiment of the present invention.
12 is a perspective view of a nitride based power semiconductor structure with terminals formed in a terminal configuration step according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to designate the same or similar components throughout the drawings. The structure and operation of the present invention shown in the drawings and described by the drawings are described as at least one embodiment, and the technical ideas and the core structure and operation of the present invention are not limited thereby.

When forming a semiconductor by depositing a material having a composition different from that of the substrate on the substrate, many defects occur due to the difference in lattice constant. In order to improve this, a micro-to-nano-sized dielectric layer mask is formed on the substrate using a nano imprint or an electron beam lithography process, and selective growth using MOCVD (Metal-Organic Chamical Vapor Deposition) GaN is grown. Continuously growing AlGaN / GaN heterostructures on the grown GaN can grow a nitride based power semiconductor structure with a high quality 2-DEG layer. The nanostructured GaN can reduce the contact area with the substrate, reduce the concentration of defects due to lattice mismatch, and control the strain present in the heterostructured structure. A nitride-based power semiconductor structure having a high-quality AlGaN / GaN structure can be grown on the entire surface of the substrate. Hereinafter, a structure will be described with reference to FIGS. 1 to 7, and a method and an article manufactured by each step will be described with reference to FIGS. 8 to 12. FIG.

2 is a side view of a nitride-based power semiconductor device according to an embodiment of the present invention.

When the nitride based power semiconductor structure 230 is deposited on the substrate 210 in a planar form as shown in FIG. 1, strain is generated because the lattice constants are different. As the contact area increases, the strain is superimposed, so that defects are generated when the critical dimension is exceeded. In the present invention, a nitride-based power semiconductor structure 230 is formed in the form of a micro or nano-sized sheet or rod having a contact area within a critical dimension, and element layers 330 and 340 are formed on the surface To implement the circuit.

Thus, a dielectric layer or oxide layer (not shown) may be formed on the substrate 210 to prevent deposition of the nitride based power semiconductor structure 230 on the substrate 210 to prevent the junction region of the substrate 210 and the nitride based power semiconductor structure 230 from becoming excessively long, 220 are formed on the substrate 210 and patterned, and the nitride-based power semiconductor structure 230 is formed only on the portion where the substrate 210 is exposed.

The dielectric layer may be an oxide film and SiN layer may be SiO 2.

Thus, according to the present invention, a nitride based power semiconductor device includes a substrate 210, a dielectric or oxide layer 220, a buffer layer 320 and device layers 330 and 340. In this case, the substrate 210 is preferably a single crystal, and a dielectric layer or an oxide layer 220 is deposited on the substrate 210, and a pattern exposing a part of the substrate 210 is formed on the dielectric layer or the oxide layer 220. The buffer layer 320 is deposited on the exposed region of the substrate. Element layers 330 and 340 are deposited on the buffer layer 320 and include a 2DEG layer in which material layers of different band gaps are bonded.

Here, the pattern may be smaller than a threshold size at which defects are generated in the process of depositing the buffer layer 320.

Here, the pattern may be a shape in which a rectangular shape is repeatedly formed.

Here, the buffer layer 320 and the device layers 330 and 340 may be formed in parallel with the substrate 210.

Here, the buffer layer 320 may have a convexly raised structure over the substrate 210. That is, the buffer layer 320 is grown higher than the dielectric layer or the oxide layer 220, and the device layers 330 and 340 may cover the surface of the buffer layer 320.

Here, the element layers 330 and 340 are formed with a source, a drain, and a gate electrode on the surface, and can operate as a transistor. At this time, the source, the drain, and the gate electrode can be realized by a method of depositing a metal on the surface using a lithography process.

Here, the element layers 330 and 340 may be a 2DEG layer (2D electron electron gas layer). That is, the element layers 330 and 340 may include a two-dimensional electron gas layer in which electron gas is accumulated by bonding materials having different band gaps. Here, the 2DEG layer may be a layer in which GaN and AlGaN are bonded or a layer in which GaN and AlInN are bonded.

The buffer layer 320 may have a multi-layer structure to prevent defects occurring between the substrate 210 and the buffer layer 320 from growing into the device layers 330 and 340.

Here, the 2DEG layer may be a layer in which the nitride-based thin film layer 330 and the dissimilar material layer 340 are bonded.

Here, the nitride-based thin film layer 330 may be AlGaN and the hetero-material layer 340 may be GaN.

Here, the nitride-based thin film layer 330 may be GaN and the hetero-material layer 340 may be AlInN.

Here, the substrate 210 may be any substrate 210 capable of growing nitride. The substrate 210 may be a silicon substrate, a silicon carbide substrate, or a sapphire substrate.

3 is a cross-sectional view of a nitride-based power semiconductor device according to an embodiment of the present invention.

When the nitride-based power semiconductor device is in the form of a wall, the upper surface of the wall protrudes over the substrate 210 so that the convex layered structure becomes a multilayer structure.

The nitride-based power semiconductor device in the form of a wall does not form a support when the nitride-based power semiconductor structure is grown on the exposed substrate 210. In other words, when making a pattern on the substrate 210 with a dielectric layer such as SiN or SiO 2 or an oxide layer 220, the nitride-based power semiconductor structure 230 is grown at a low height and on the exposed substrate 210 .

Thus, when grown in a multi-layer structure, the next layer grows to cover the entire surface of the previous layer without interfering with the dielectric layer or oxide layer 220. Thus, both sides of the wall and the top surface are covered with the same layer. The final layer is composed of the device layers 330 and 340, and the electrodes are connected to each other as devices.

Here, the element layers 330 and 340 can be constructed as modules as nitride-based power semiconductor structures of micro or nano size. In other words, if a transistor is implemented as a nitride-based power semiconductor structure, one transistor in which source, drain, and gate terminals are formed can be integrated.

Here, the element layers 330 and 340 may include a 2DEG layer in which materials having different band gaps are bonded. The 2DEG layer may be a layer in which GaN and AlGaN are bonded or a layer in which GaN and AlInN are bonded.

Here, the nitride based power semiconductor structure 230 is formed by a method of depositing on a substrate 210, and the substrate 210 should be an atomic structure capable of depositing a nitride based semiconductor. Specifically, the substrate 210 may be any one of a silicon substrate, a silicon carbide substrate, and a sapphire substrate.

The nitride based power semiconductor device may further include a core layer 310 between the substrate 210 and the buffer layer 320 and a lattice constant of the core layer 310 may be greater than a lattice constant of the substrate 210 and the buffer layer 320. [ Lt; RTI ID = 0.0 > 320 < / RTI > By locating the core layer 310 between the substrate 210 and the element layers 330 and 340, it is possible to induce the equiaxed growth to occur easily and to reduce defects that occur during growth. In other words, since the element layers 330 and 340 differ from the substrate 210 in lattice constant, the nucleation layer 310 is preliminarily deposited on the substrate 210 and the element layers 330 and 340 are formed on the substrate 210, Is deposited on the nucleus layer 310 to increase the fabrication speed and reduce defects. The nuclear layer 310 is deposited with an element whose lattice constant is the value between the lattice constant of the substrate 210 and the lattice constant of the buffer layer 320.

However, even in this case, since the difference between the lattice constants of the nuclear layer 310 and the element layers 330 and 340 is large, defects are likely to be generated. In order to prevent such defects from growing, an element layer such as AlGaN may be added between the core layer 310 and the device layers 330 and 340 to form a buffer layer 320 capable of blocking defects.

4 is a cross-sectional view of a parallel nitride based power semiconductor device according to an embodiment of the present invention.

The parallel nitride based power semiconductor device grows a dielectric layer or oxide layer 220 on both sides with high growth and deposits a nitride based power semiconductor structure therebetween. Since the bilateral side is supported by the dielectric layer or the oxide layer 220, the parallel nitride semiconductor power semiconductor structure is deposited only in a multi-layer structure, but is not grown on both sides. Thus, a layered structure parallel to the substrate 210 is produced.

In the case of a parallel nitride based power semiconductor device, the final layer can also be formed of the device layers 330 and 340.

In the parallel nitride based power semiconductor structure, the element layers 330 and 340 can be formed as modules in the form of micro or nano-sized semiconductor elements. In other words, if a transistor is implemented as a nitride-based power semiconductor structure, one transistor in which source, drain, and gate terminals are formed can be integrated.

In a parallel nitride based power semiconductor device, the device layers 330 and 340 may include a 2DEG layer in which materials having different band gaps are bonded. Here, the 2DEG layer may be a layer in which GaN and AlGaN are bonded or a layer in which GaN and AlInN are bonded.

A parallel nitride based power semiconductor structure may also be fabricated by depositing on a substrate 210, which must be an atomic structure capable of depositing a nitride based semiconductor. Specifically, the substrate 210 may be any one of a silicon substrate, a silicon carbide substrate, and a sapphire substrate.

Since the parallel nitride semiconductor power semiconductor structure has a lattice constant different from that of the substrate 210, the nucleus layer 310 for equiaxial growth is preliminarily deposited on the substrate 210 to form element layers 330 and 340, (310). The nuclear layer 310 is deposited with an element whose lattice constant is the value between the lattice constant of the substrate 210 and the lattice constant of the element layers 330 and 340.

However, even in this case, since there are many differences in lattice constant between the core layer 310 and the element layers 330 and 340, defects are likely to be generated. In order to prevent such defects from growing, a buffer layer 320 may be further provided to prevent defects between the core layer 310 and the device layers 330 and 340. At this time, the buffer layer 320 may be AlGaN.

Whether the nitride-based power semiconductor device shown in FIGS. 3 and 4 is a nitride-based power semiconductor structure or a parallel nitride-based power semiconductor device depends on the height of the dielectric layer or the oxide layer 220. When the height of the dielectric layer or the oxide layer 220 is low, a nitride-based power semiconductor structure may be further grown on the dielectric layer or the oxide layer 220. Therefore, the upper layer of the nitride- . However, when the dielectric layer or the oxide layer 220 is provided on both surfaces, both surfaces of the nitride-based power semiconductor structure are covered, so that a layer parallel to the substrate 210 overlaps only the upper surface of the nitride-based power semiconductor structure.

5 is a perspective view of a modular nitride based power semiconductor in accordance with an embodiment of the present invention.

When a nitride-based power semiconductor structure having a patterned dielectric layer or oxide layer 220 on the substrate 210 and a wall-shaped region in the exposed region of the substrate 210 is implemented, the nitride- And can be used as a transistor. In other words, when the source 520, the drain 530, and the gate 510 are connected to three surfaces including the top surface of the nitride type power semiconductor structure of the wall type and heated to form a doping and ohmic contact, Can be used. In this case, the electrons in the lower part of the gate 510 terminal react to the action of the electric field, and the reaction speed and precision increase because the three surfaces are utilized.

6 and 7 are perspective views of a substrate 210 on which a nitride-based power semiconductor according to an embodiment of the present invention is regularly manufactured.

Referring to FIG. 6, a silicon oxide film is deposited on a sapphire substrate 210, and a nitride-based power semiconductor structure is implemented at a pattern position where there is no silicon oxide film. The nitride-based power semiconductor structure grows simultaneously in the region where the substrate 210 is exposed in accordance with the equiaxial growth, so that a nitride-based power semiconductor structure can be mass-produced.

A nitride-based power semiconductor structure in the form of a wall can be periodically fabricated to make the nitride-based power semiconductor structure module described in FIG. 5 in large quantities. According to the initial pattern shape and growth conditions, not only the nitride based power semiconductor device of FIG. 5 but also a power semiconductor form such as a rod shape as shown in FIG. 7 can be manufactured.

8 is a flowchart illustrating a method of fabricating a nitride-based power semiconductor device according to an embodiment of the present invention.

A dielectric layer or an oxide layer is deposited on the substrate (S810). At this time, the dielectric layer may be SiN, and may be spin coated instead of vapor deposition. An oxide film layer can be deposited instead of the dielectric layer. And may be SiO 2 if it is an oxide film layer. The dielectric layer is preferably an insulator, and the dielectric layer must have a different crystal structure than the nitride-based material so that the nitride-based material can not be deposited on the dielectric layer.

And patterned in the dielectric layer (S820). If the dielectric layer is a photoresist, it may be directly patterned using light. However, if the dielectric layer is an oxide layer, patterning may be performed on the dielectric layer by depositing and etching a photoresist on the top. The patterned shape may be point or line shaped, and the shape of the nitride power semiconductor structure is determined by the thickness of the dielectric, as described with reference to FIGS. The method of etching can be any one, but since the depth of etching is deep, dry etching is more advantageous than wet etching in order to avoid isotropy.

A nitride-based thin film layer is grown (S830). The core layer 310 may be deposited in advance on the substrate 210 so that the nitride based thin film layer 330 may be deposited on the substrate 210. [ In addition, the buffer layer 320 may be further grown to prevent growth of defects in the process of growing the nitride-based thin film layer 330. The GaN layer may be grown as the nitride-based thin film layer 330 on the buffer layer 320.

A nitride-based power semiconductor structure is further grown (S840). A heterogeneous material layer 340 such as AlGaN or AlInN is further grown on the GaN. GaN layer and is hetero-junctioned to form a 2DEG layer.

(S850). The source, drain, and gate terminals are connected to fabricate the transistor as a module. In this case, if an insulator is additionally deposited on the gate attaching region and the gate terminal is connected, a MOS (Metal Oxide Semiconductor) device can be fabricated. After that, electrodes can be connected to each terminal and used as a power semiconductor.

9 is a cross-sectional view of a device fabricated in each sub-step in the dielectric deposition step and the patterning step.

(1) Prepare a substrate. At this time, the substrate 210 is preferably a sapphire substrate, but may also be deposited on silicon or a silicon carbide substrate.

(2) A silicate layer (SiO 2 ) is deposited on the substrate. In the present invention, a method of depositing using MOCVD is taken as an example, but various methods such as an E-beam deposition method can be used. Of course, the dielectric layer or the oxide film layer 220 can be used instead of the silicic acid.

(3) Coating PMMA. PMMA (PolyMethyMethAcrylate; 910) is excellent in strength and corrosion resistance to protect the dielectric during the etching of the photoresist.

(4) A photoresist layer or a resin layer is produced. The photoresist layer 920 can be applied by spin coating onto a flat PMMA layer. Alternatively, when imprinting the pattern by a physical method, the imprint resin layer can be applied.

(5) imprinting. After the photoresist layer 920 is fixed on the PMMA layer 910, it may be photoimaged and etched in a uniform pattern. When an imprinted resin layer is formed instead of the photoresist layer 920, the imprinted resin layer may be physically pressed so that a specific pattern may be formed by heating or photosensitively molding the specific pattern.

(6), (7) PMMA and the silicic acid layer are etched. The PMMA layer 910 and the silicate layer are dry-etched. At this time, if a dielectric layer or an oxide film layer 220 is used instead of the silicate layer, the dielectric layer or the oxide film layer 220 is dry-etched. If the kind of plasma for dry etching is different, the kind of plasma can be changed depending on the kind of layer to be etched. At this time, it is also possible to make a pattern by wet etching, but it is more suitable for the present invention in which dry etching with strong anisotropy than wet etching must be linearly etched to a deep point.

(8) The PMMA layer is removed. The PMMA layer 910 is removed using an acid based solvent and can be easily removed without appreciable damage to the dielectric layer or oxide layer 220, such as silicic acid. At this time, the photoresist layer 920 or the resin layer is removed together.

FIGS. 10, 11, and 12 are cross-sectional views and perspective views of a nitride-based power semiconductor device in a semiconductor thin film growth step, a hetero-material layer growth step, and a terminal configuration step according to an embodiment of the present invention. In the description with reference to FIG. 3, except for the buffer layer 320, which is a subsidiary component in FIG. 3 and FIG. 4, the element layer 330 and 340 including the heterojunction, A nitride-based power semiconductor device is described. However, the configuration described in FIG. 3 and FIG. 4 may be added as necessary. 10, 11, and 12 (a) correspond to FIG. 4, and FIG. 12 (b) corresponds to FIG.

10 is a cross-sectional view of a nitride-based power semiconductor device in which a core layer and a buffer layer are formed in a semiconductor thin film growth step according to an embodiment of the present invention.

When the etching described in FIG. 9 is completed to the extent that the substrate 210 is exposed, the core layer 310 is deposited on the exposed substrate 210. The core layer 310 is deposited with an element having a crystal structure similar to that of the nitride-based power semiconductor structure. Any method can be used if it can grow equally. For example, electroplating is possible if it proceeds slowly. The core layer 310 is preferably an element such as AlN having a lattice constant between the lattice constant of the substrate 210 and the lattice constant of the nitride based power semiconductor structure. The buffer layer 320 may be further grown thereon with Al (Ga) N or GaN.

(a), a core layer 310 is formed on a substrate 210 on which a dielectric layer or an oxide layer 220 with a pattern is formed on both sides. The core layer 310 is filled in the space between the dielectric layer or the oxide layer 220. [ The buffer layer 320 grows sufficiently to fill the space between the dielectric layer or the oxide layer 220.

(b), a core layer 310 is formed on a substrate 210 on which a dielectric layer or an oxide film layer 220 with a low pattern is formed on both sides. Since the space between the dielectric layer and the oxide layer 220 is low, the core layer 310 is filled and the height is uniform throughout. The buffer layer 320 is sufficiently grown on the side 310. Controlling the pressure and the temperature for growing the buffer layer 320 can be controlled so as to grow perpendicularly to the substrate 210.

11 is a cross-sectional view of a nitride-based power semiconductor device in which a nitride-based thin film layer and a hetero-material layer are formed in a semiconductor thin film growth step and a hetero-material layer growth step according to an embodiment of the present invention.

The nitride-based thin film layer 330 is grown on the core layer 310. At this time, the nitride-based thin film layer 330 is grown sufficiently high to prevent defects that may be generated in the bottom from affecting the surface. At this time, the nitride-based thin film layer 330 may be AlGaN.

When the nitride-based thin film layer 330 is AlGaN, the hetero-material layer 340 may be GaN. This combination is a typical way of creating a 2DEG. As in the semiconductor thin film growth step, the hetero-material layer growth step can also be grown using MOCVD (Metal-Organic Chamical Vapor Deposition). Since the 2DEG is generated between the nitride-based thin film layer 330 and the hetero-material layer 340, the hetero-material layer 340 is formed to be thin so that the electric field may affect the inside of the hetero-material layer 340.

(a), a nitride-based thin film layer 330 and a hetero-material layer 340 are formed on a substrate 210 on which a dielectric layer or an oxide film layer 220 with a pattern is formed on both sides. Since the space between the dielectric layer or oxide layer 220 in FIG. 10 is mostly filled with the buffer layer 320, a slight amount of the remaining space can be filled with the nitride-based thin film layer 330 and the heterogeneous material layer 340.

(b), a heterogeneous material layer 340 is formed on a substrate 210 in which a dielectric layer or an oxide film layer 220 having a pattern formed on both sides thereof is formed low. The nitride-based thin film layer 330 and the hetero-material layer 340 are sequentially deposited on the surface of the vertically grown buffer layer 320. The hetero-material layer 340 and the nitride-based thin-film layer 330 may be grown on the upper end of the buffer layer 320 in an equi-axis manner. However, in order to increase the surface area of the hetero-material layer 340, The nitride-based thin film layer 330 and the hetero-material layer 340 can be grown on the entire surface of the nitride-based thin film layer 330.

12 is a perspective view of a nitride based power semiconductor structure with terminals formed in a terminal configuration step according to an embodiment of the present invention.

A source 520, a drain 530, and a gate 510 terminal are required to make the transistor. The source 520, the drain 530, and the gate 510 terminal may be connected to the surface of the nitride-based power semiconductor structure formed in FIG. 11 to make a transistor as a single module. The method of connecting the terminals can be made by using a lithography method. In particular, in the case of (a), it is possible to maximize the effect of the electric field by arranging the terminals on three surfaces.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Modification is possible.

Accordingly, it is intended that the scope of the invention be defined solely by the claims appended hereto, and that all equivalents or equivalent variations thereof fall within the spirit and scope of the invention.

210: substrate 220: dielectric layer or oxide layer
230: nitride-based power semiconductor structure 310: nuclear layer
320: buffer layer 330: nitride-based thin film layer
340: heterogeneous material layer 510: gate
520: source 530: drain
620: photoresist layer 910: PMMA layer

Claims (19)

A substrate that is a single crystal;
A dielectric layer formed on the substrate and patterned to expose a portion of the substrate;
A buffer layer deposited on the exposed region of the substrate; And
An element layer including a 2DEG layer (a 2DEG electron layer (2DEG) layer deposited on the buffer layer and having a band gap of different material layers joined together; ≪ / RTI >
Further comprising a core layer between the substrate and the buffer layer, wherein the lattice constant of the core layer has a value between the lattice constant of the substrate and the buffer layer. The method according to claim 1,
Wherein the exposed region is smaller than a threshold size at which defects are generated in the process of depositing the buffer layer. The method according to claim 1,
Wherein the buffer layer and the device layer are formed in parallel with the substrate. The method according to claim 1,
Wherein the buffer layer is grown higher than the dielectric layer and the device layer covers the surface of the buffer layer. The method according to claim 1,
Wherein a source, a drain, and a gate electrode are formed on the surface of the element layer. The method according to claim 1,
Wherein the buffer layer is formed in a multi-layer structure to prevent defects occurring between the substrate and the buffer layer from growing into the device layer. The method according to claim 1,
Wherein the 2DEG layer is a layer in which a nitride-based thin film layer and a hetero-material layer are bonded to each other. 8. The method of claim 7,
Wherein the nitride-based thin film layer is made of AlGaN and the hetero-material layer is made of GaN. 8. The method of claim 7,
Wherein the nitride-based thin film layer is GaN and the hetero-material layer is AlInN. The method according to claim 1,
Wherein the substrate is one of a silicon substrate, a silicon carbide substrate, and an aluminum oxide substrate. The method according to claim 1,
Wherein the pattern is repeatedly formed in a rectangular shape. delete A dielectric layer deposition step of depositing a dielectric layer on the substrate;
A patterning step of patterning the dielectric layer to expose a part of the substrate;
A nitride-based thin film layer growth step of growing a nitride-based thin film layer on the exposed region of the substrate;
A hetero-material layer growth step of growing a hetero-material layer on the nitride-based thin film layer; And
A terminal forming step of connecting source, gate and drain terminals to the hetero-material layer; , ≪ / RTI &
In the step of growing the nitride-based thin film layer,
The nitride layer is grown after the nucleation layer is previously deposited on the exposed region of the substrate and further the buffer layer is grown and the lattice constant of the core layer has a value between the lattice constants of the substrate and the buffer layer Wherein said nitride-based power semiconductor device is fabricated by the following method. 14. The method of claim 13,
Based thin film layer growth step further comprises a buffer layer growth step between the patterning step and the nitride based thin film layer growth step, wherein the buffer layer growing step grows a buffer layer on the exposed region of the substrate, and in the nitride based thin film layer growing step, And growing the nitride semiconductor layer on the buffer layer. 14. The method of claim 13,
Wherein the patterning is performed using lithography or imprinting. 14. The method of claim 13,
Wherein the nitride-based thin film layer growth step or the hetero-material layer growth step is implemented using MOCVD (Metal-Organic Chamical Vapor Deposition). 14. The method of claim 13,
Wherein the nitride-based thin film layer is AlGaN and the hetero-material layer is GaN. 14. The method of claim 13,
Wherein the nitride-based thin film layer is GaN and the hetero-material layer is AlInN. 14. The method of claim 13,
The terminal configuration step may include:
Wherein the source, gate, and drain terminals are formed using a lithography process.

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100894810B1 (en) * 2007-09-19 2009-04-24 전자부품연구원 High electron mobility transistor and method for manufacturing thereof
KR101159952B1 (en) * 2009-12-31 2012-06-25 경북대학교 산학협력단 Compound semiconductor device having fin structure, and manufacturing method thereof
JP2012164693A (en) * 2011-02-03 2012-08-30 Fujitsu Ltd Compound semiconductor device, and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100894810B1 (en) * 2007-09-19 2009-04-24 전자부품연구원 High electron mobility transistor and method for manufacturing thereof
KR101159952B1 (en) * 2009-12-31 2012-06-25 경북대학교 산학협력단 Compound semiconductor device having fin structure, and manufacturing method thereof
JP2012164693A (en) * 2011-02-03 2012-08-30 Fujitsu Ltd Compound semiconductor device, and method of manufacturing the same

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