KR101489469B1 - Patterned plastic ball grid array packaging - Google Patents

Patterned plastic ball grid array packaging Download PDF

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Publication number
KR101489469B1
KR101489469B1 KR20130133439A KR20130133439A KR101489469B1 KR 101489469 B1 KR101489469 B1 KR 101489469B1 KR 20130133439 A KR20130133439 A KR 20130133439A KR 20130133439 A KR20130133439 A KR 20130133439A KR 101489469 B1 KR101489469 B1 KR 101489469B1
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KR
South Korea
Prior art keywords
substrate
grid array
semiconductor chip
ball grid
deformation preventing
Prior art date
Application number
KR20130133439A
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Korean (ko)
Inventor
김영국
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인하대학교 산학협력단
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Priority to KR20130133439A priority Critical patent/KR101489469B1/en
Application granted granted Critical
Publication of KR101489469B1 publication Critical patent/KR101489469B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to a patterned plastic ball grid array package, and more particularly, to a patterned plastic ball grid array package, in which distribution of strain energy applied to a solder ball in a plastic ball grid array (PBGA) package is dispersed to prevent mechanical damage, And more particularly to a patterned plastic ball grid array package.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a patterned plastic ball grid array package having a semiconductor chip and a molding part for fixing a semiconductor chip on a top surface of a substrate, A deformation preventing portion is formed on an upper surface of the molding portion, and the deformation preventing portion is located at an edge portion of the semiconductor chip.

Description

A patterned plastic ball grid array package

The present invention relates to a patterned plastic ball grid array package, and more particularly, to a patterned plastic ball grid array package, in which distribution of strain energy applied to a solder ball in a plastic ball grid array (PBGA) package is dispersed to prevent mechanical damage, And more particularly to a patterned plastic ball grid array package.

In the semiconductor industry, surface mount packaging technology has been developed to provide lightweight, small, thin structures at low cost. Particularly, since the chip scale package close to the size of the silicon chip has emerged, the importance of the related mounting technology and the post-mounting electrical and mechanical reliability is greatly highlighted. Plastic ball grid array (PBGA) technology is the most widely used technology among 1st level package methods.

The most common process for fabricating PBGA packages is outlined in the following order.

First, sawing is performed to separate the semiconductor chips formed on the wafer after the FAB (Fabrication) process for forming the integrated circuit on the wafer surface.

Then, as a circuit board having wiring therein is inserted into the process, an adhesive is applied to the top surface of the circuit board to bond the cut semiconductor chip. After the chip bonding is completed, a bonding pad formed on the semiconductor chip and a predetermined The wires are electrically connected to each other by using wires. In case of Flip chip, connect with solder.

After the wire bonding is completed, a molding process of encapsulating the semiconductor chip with an epoxy molding compound (EMC) is performed. In the case of wafer level packaging, the molding process is followed by sowing. After the molding is completed, a certain pattern of solder paste is transferred onto the bottom surface of the package body made of a circuit board by screen printing, and a solder ball is attached in a predetermined pattern. Then, a reflow process as a heat treatment process is performed The solder balls are firmly fixed to the circuit board main body.

After that, cleaning and marking process will be done to ship the finished PBGA package.

One of the PBGA semiconductor packages described in Korean Registered Utility Model No. 20-148625 as shown in Figs. 1 and 2 has been developed. The technical feature of the PBGA semiconductor package includes a land portion (not shown) formed on the upper surface of the substrate 1 A plurality of solder balls 4 are attached to a lower surface of the substrate 1. The substrate 1 is provided with a plurality of internal leads 3 And the upper surface of the semiconductor chip 3 and the upper surface of the inner lead 5 are connected to each other by a metal wire 6. The semiconductor chip 3 and the metal wire 6 A molding part 7 is formed on the upper surface of the substrate 1 and the plurality of solder balls 4 are mounted on the upper surface of the substrate 8.

However, the technique described in Korean Utility Model No. 20-148625 is widely used because of its relatively simple process, low cost and effectively protecting the silicon chip. However, since the material used as a molding compound is basically an epoxy-based polymer, When exposed to a change, it sensitively expands and shrinks according to the change. Because of this phenomenon, various mechanical damages are caused due to repeated shrinkage and expansion after mounting on a substrate. Due to this warpage, As shown in FIG. 3, the breakage of the solder ball connecting the substrate and the PBGA has a problem in that the reliability of the package is seriously damaged.

In order to prevent this, basically, the thickness of the molding compound must be thin. However, since the metal wire must be protected and the appropriate thickness must be maintained for the marking on the molding compound, the crack of the solder due to the bending phenomenon can not be fundamentally prevented have.

Material property effects on solder failure analyses (Author: Yeong K. Kim, Jin Hyuk Gang, Bo-young Lee, Journals: Microelectronics Reliability, Volume 51, page 985-993, 2011)

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems described above, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which comprises joining a substrate by using a solder ball on a substrate, installing a semiconductor chip on an upper surface of the substrate, The inner lead and the semiconductor chip are connected by a metal wire, and a molding part is formed on the substrate so as to surround the semiconductor chip and the metal wire. By forming a proper deformation preventing part on the upper surface of the molding part, The present invention provides a patterned plastic ball grid array package capable of preventing solder balls from being damaged by dispersing strain energy acting on the solder balls.

SUMMARY OF THE INVENTION [0006]

A patterned plastic ball grid array package comprising a substrate and a substrate, the substrate having an upper surface coupled to a substrate using solder balls, wherein a molding portion is formed on an upper surface of the substrate to secure the semiconductor chip and the semiconductor chip, Is formed.

Here, the deformation preventing portion is formed on the upper surface of the molding portion where the solder ball to which the SED is most applied, or on the outer side thereof.

In addition, the deformation preventing portion is formed in a dull shape.

In this case, the thickness of the deformation preventing portion is formed thicker than the thickness of the molding portion.

In addition, the deformation preventing portion is formed at the same time when the molding portion is formed.

According to the present invention having the above-described structure, a substrate is coupled to an upper portion of a substrate using a solder ball, and a semiconductor chip is mounted on an upper surface of the substrate, wherein an inner lead and a semiconductor chip, And a molding part is formed on the substrate so as to surround the semiconductor chip and the metal wire or the solder ball. By forming the bump-shaped deformation preventing part on the upper surface of the molding part, deformation acting on the solder ball due to thermal deformation of the molding part The energy is dispersed and the solder ball is prevented from being damaged.

1 is a conceptual diagram of a conventional PBGA semiconductor package.
2 is a cross-sectional view of a conventional PBGA semiconductor package.
3 is a view showing an example of cracking of a solder portion of a conventional PBGA semiconductor package.
4 is a perspective view of a chip mounting state of a PBGA semiconductor package according to the present invention.
5 is a cross-sectional view of a PBGA semiconductor package according to the present invention.
6 is a schematic view of a solder ball applied to the present invention.
FIG. 7 is a simplified schematic diagram of a three-dimensional strip model of a PBGA packaging structure for explaining a method of calculating a fatigue energy of a solder by a finite element method in the present invention.
8 is a partial sectional view of Fig.
Figure 9 is a plot of the temperature cycle used to calculate strain energy.
10 is a view showing strain energy generated when the temperature cycle of FIG. 9 is applied to the model of FIG. 7. FIG.
FIG. 11 is a packaging structure diagram in which a barrier is formed on the upper surface of a molding part in the present invention. FIG.
12 is a graph comparing deformation energies of the fourth solder balls generated when the temperature cycle of FIG. 9 is applied to the models of FIGS. 7 and 8. FIG.
13 is a cross-sectional view of the semiconductor chip mounted in the form of a flip chip.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

5 is a cross-sectional view of a PBGA semiconductor package according to the present invention, FIG. 6 is a view showing the shape of a solder ball applied to the present invention, and FIG. 7 is a cross- FIG. 8 is a partial cross-sectional view of FIG. 7, and FIG. 9 is a graph showing a relationship between a temperature used to calculate the strain energy FIG. 10 is a view showing a strain energy generated when the temperature cycle of FIG. 9 is applied to the model of FIG. 7, FIG. 11 is a packing structure diagram of forming a barrier on the upper surface of the molding part according to the present invention, 12 is a graph comparing the strain energy at the fourth solder ball generated when the temperature cycle of FIG. 9 is applied to the models of FIGS. 7 and 8, and FIG. A cross-sectional view of chakdoen state.

The present invention relates to a patterned plastic ball grid array package. As shown in FIGS. 4 and 5, the present invention includes a substrate 10 on which a circuit is formed and a substrate 30 A solder ball 20 connecting the substrate 10 and the substrate 30 and a semiconductor chip 40 provided on an upper surface of the substrate 30 and a molding part 60).

The semiconductor chip 40 is mounted on the upper surface of the substrate 30 so that the semiconductor chip 40 can be mounted more easily on the upper surface of the substrate 30. The substrate 30 has upper and lower portions An inner lead (not shown) for electrically connecting the semiconductor chip 40 is formed and the inner lead is electrically connected to the semiconductor chip 40 using a metal wire 50.

13, if the semiconductor chip 40 is attached in the form of a flip chip, there is no metal wire 50 but is connected to a small solder ball 51 instead.

Each terminal of the semiconductor chip 40 and the internal leads exposed on the lower surface of the substrate 30 are connected to each other so that the terminals formed on the upper surface of the substrate 10, The inner leads exposed on the lower surface can be easily connected.

6, the solder ball 20 includes a ball-shaped solder 22 and a copper pad 21 formed on the upper and lower sides of the solder 22, and the solder 22 The copper pads 21 are formed on the upper and lower portions of the substrate 10 and the substrate 30, respectively.

The molding part 60 is formed by using an epoxy molding compound (EMC). The molding part 60 covers the upper part of the semiconductor chip 40 and is firmly fixed to the upper surface of the substrate 30 The metal wire 50 or the small solder ball 51 is prevented from being damaged by an external force by covering the metal wire 50 or the small solder ball 51 connecting the semiconductor chip 40 and the inner lead, . ≪ / RTI >

The deformation preventing portion 70 is formed on the upper surface of the molding portion 60 formed on the upper portion of the substrate 30. The deformation preventing portion 70 is formed in a dull shape protruding upward, The shape is formed in various shapes such that the upper part is formed into a square bar shape having an angular shape or the round shape is formed with a top part having a round shape.

The deformation preventing portion 70 is formed on the upper portion of the solder ball 20 having concentrated deformation energy among the plurality of solder balls 20 connecting the substrate 30 and the substrate 10, So that the solder ball 20 is improved in durability. Thus, reliability and stability of the semiconductor package are improved even when the solder ball 20 is used for a long time.

That is, when the semiconductor chip 40 mounted on the substrate 30 is supplied with electricity, heat is generated. Since the material forming the molding part 60 is an epoxy based polymer, the semiconductor chip 40 A deformation that delicately expands and contracts in the molding portion 60 is generated due to the heat discharged from the substrate 30 or the surrounding temperature environment. As a result, deformation occurs in the substrate 30, And the solder ball 20 connected to the substrate 10 is subjected to deformation energy, so that the solder ball 20 is damaged.

Here, a metal material commonly used in general solder materials is broken by stress when a change in load is fast, and is broken by a unit strain when a change in load is slow. In the case of the package In the case of structural deformations, it is caused by temperature changes at very low frequencies (5 minutes or longer per cycle), so that breakage occurs by unit strain rather than by stress, the SED is continuously accumulated in the solder ball 20, and as a result, the solder ball 20 is damaged. As a result, do.

The present invention is characterized in that a deformation preventing portion 70 of a bump shape is formed on an upper portion of the molding portion 60 to disperse strain energy concentrated on the solder ball 20 located under the deformation preventing portion 70 So that breakage of the solder ball 20 can be stably prevented.

At this time, the deformation preventing portion 70 is formed at the same time when the molding portion 60 is formed. The structure of the molding used when the epoxy molding compound (EMC) is injected can be easily modified, It is possible to easily form the deformation preventing portion 70 with the same material as the portion 60.

Of course, it is also possible to form the deformation preventing portion 70 from a separate material after the molding portion 60 is formed.

7 to 12, it can be seen that the above-described strain energy density (SED) is reduced. In a general PBGA packaging structure as shown in FIGS. 7 and 8, seven solder balls 20 are provided , The SED generated in each solder was calculated using ANSYS, a commercial finite element program, in the case of four thermal cycles with the highest and lowest temperatures of 65 ° C and -30 ° C, as shown in FIG.

As a result, the solder in which the SED is generated most is shown in FIG. 10 as the fourth solder ball 20, and 0.11 MPa is generated while the temperature cycle proceeds four times. 11, a deformation preventing portion 70 having the same thickness and the same thickness is formed on the fifth solder ball 20 where the silicon chip is terminated. This position is determined by calculation. After modifying the molding compound, the SED was calculated by applying the load of the same thermal cycle. As a result, the SED generated at the fourth solder ball 20 was 0.10 MPa, showing a reduction rate of about 10%.

Given the fact that the electronic packaging structure is exposed to more than one thousand cycles in general, due to the difference in temperature of the four cycles, it is clear that the difference becomes larger as the number of cycles increases.

That is, by forming the deformation preventing portion 70 by deforming the shape of the upper surface of the specific position in the conventional molding portion 60, it is possible to reduce the occurrence of the SED, thereby increasing the reliability of the solder ball 20 do.

A method of determining the position of the deformation preventing portion 70 is to calculate the SED applied to each solder ball 20 after forming the deformation preventing portions 70 on various portions of the upper portion of the molding portion 60, The deformation preventing portion 70 is finally installed at a position where the optimum reduction rate is shown based on the reduction rate of the SED according to the position where the deformation preventing portion 70 is formed.

As shown in FIG. 11, the deformation preventing portion 70 has the largest reduction rate when it is formed outwardly from the upper portion of the fourth solder ball 20 where the largest SED is concentrated.

That is, even if the deformation preventing portion 70 is formed on the upper surface of the molding portion 60, there is a certain reduction effect of the SED. However, when the SED is concentrated on the outside of the upper surface of the molding portion 60 where the solder ball 20 The SED reduction rate becomes higher.

The method of measuring the SED applied to each solder ball 20 is well known in various papers, and a separate explanation will be omitted.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

The present invention relates to a patterned plastic ball grid array package, and more particularly, to a patterned plastic ball grid array package, in which distribution of strain energy applied to a solder ball in a plastic ball grid array (PBGA) package is dispersed to prevent mechanical damage, And more particularly to a patterned plastic ball grid array package.

10: substrate 20: solder ball
30: Substrate 40: Semiconductor chip
50: metal wire 60: molding part
70: deformation preventing portion 80: land portion

Claims (5)

1. A patterned plastic ball grid array package, comprising: a substrate; a substrate on which a substrate is mounted using solder balls, wherein a molding part for fixing the semiconductor chip and the semiconductor chip is formed on an upper surface of the substrate,
A deformation preventing portion is formed on an upper surface of the molding portion,
Wherein the deformation preventing portion is formed on the upper surface of the molding portion where the solder ball is placed, where the SED is most applied, or on the outer side thereof.
delete The method according to claim 1,
Wherein the deformation preventing portion is formed in a form of a dam.
The method of claim 3,
And the thickness of the deformation preventing portion is formed thicker than the thickness of the molding portion.
The method according to claim 1,
Wherein the deformation preventing portion is formed at the same time when forming the molding portion.
KR20130133439A 2013-11-05 2013-11-05 Patterned plastic ball grid array packaging KR101489469B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187557A (en) * 1997-09-11 1999-03-30 Rohm Co Ltd Structure of semiconductor device equipped with semiconductor chip
US6512295B2 (en) * 2001-03-01 2003-01-28 International Business Machines Corporation Coupled-cap flip chip BGA package with improved cap design for reduced interfacial stresses
KR20070052043A (en) * 2005-11-16 2007-05-21 삼성전자주식회사 Bga type semiconductor chip package having sectionally solder ball with in plastic core
JP2011166008A (en) * 2010-02-12 2011-08-25 Nec Corp Intermediate structure of semiconductor device and method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187557A (en) * 1997-09-11 1999-03-30 Rohm Co Ltd Structure of semiconductor device equipped with semiconductor chip
US6512295B2 (en) * 2001-03-01 2003-01-28 International Business Machines Corporation Coupled-cap flip chip BGA package with improved cap design for reduced interfacial stresses
KR20070052043A (en) * 2005-11-16 2007-05-21 삼성전자주식회사 Bga type semiconductor chip package having sectionally solder ball with in plastic core
JP2011166008A (en) * 2010-02-12 2011-08-25 Nec Corp Intermediate structure of semiconductor device and method of manufacturing semiconductor device

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