The motor control circuit 10 will be described. In one embodiment, the motor control circuit 10 includes a PWM control circuit that provides a pulse-width modulation (PWM) signal. For example, the PWM control circuit may be the PWM control circuit 38 of FIG. 1A. The PWM control circuit sets the speed of the motor with other components in the motor control circuit 10 to a predetermined speed and maintains the speed of the motor at the predetermined speed for changes in the power supply voltage, And is used to control the speed of the motor, including reducing the speed of the motor during braking. In another embodiment, the motor control circuit 10 may receive a control signal that may include the PWM signal from an external device. The control signal may be received at a multifunction port, for example, the multifunctional port may be the multifunctional port 916 of FIG. The multifunctional port may also be used to perform additional functions, including driving the motor, braking the motor, and putting the motor in a sleep mode. In one embodiment, the motor control circuit 10 may be implemented as one integrated circuit, or may be partially implemented in more than one integrated circuit.
Referring to FIG. 1A, the motor control circuit 10 controls the speed of the motor 100. FIG. For example, the motor 100 may be a brushless DC motor. The motor control circuit 10 includes a supply voltage port 12, a sleep port 16, a PWM duty cycle (PDC) port 20, output ports 24a and 24b, (34). The power supply voltage port 12 receives a power supply voltage that provides power to the elements in the motor control circuit. As will be described below, the sleep port 16 receives signals that cause some of the motor control circuitry to be in the sleep mode. The PDC port 20 is used to set the duty cycle of the motor signal provided to the motor 100. Output ports 24a and 24b are respectively connected to terminals 26a and 26b of motor 100 to provide the motor signal. The grounding port 34 grounds the elements of the motor control circuit 10.
The user can control the speed of the motor 100 by providing an appropriate input control signal through the PDC port 20. [ For example, the input control signal may be a voltage signal. In one example, the input control signal provided at the PDC port 20 may be one of a plurality of signals selected. Each of the plurality of signals is associated with a respective duty cycle of the motor signal provided at the output ports 24a, 24b. That is, each of the plurality of signals is associated with a respective desired motor speed. For example, a DC signal of 5V applied to the PDC port 20 may correspond to a 75% duty cycle, and a signal of 0V may correspond to a 25% duty cycle. In another example, the PDC port 20 may be in an unconnected state, i. E. A float state, for a voltage between 1/3 and 2/3 of the power supply voltage, which may correspond to a 50% have. In one example, where the motor 100 is a brushless motor, a 100% duty cycle is provided for the first signal provided to the ports 24a, 24b for a time of 50% and the first signal provided to the ports 24a, 24b To the second signal supplied to the second terminal.
The motor control circuit 10 may control the speed of the motor based on the finite range of duty cycles. For example, a selected one of the three voltage levels may be applied to the PDC port 20 to select one of three distinct duty cycles to allow the user to externally control the motor control circuit 10 By setting the duty cycle, changes in the duty cycle over the entire range of temperature and semiconductor wafer process parameters can be achieved within +/- 5%. In other examples, referring to FIG. 12, the PWM signal may be supplied from the outside, and therefore the PDC port 20 may not be needed.
The motor control circuit 10 also includes a PWM control circuit 38, a power and sleep control (PSC) circuit 42, a stall detector 46, a Hall effect circuit 52 An amplifier 56, drive logic and a drive logic and self-switching (DLSS) control circuit 62, an H-bridge circuit 64 and a thermal shutdown protection circuit (68). The motor control circuit 10 includes an electrostatic discharge (ESD) circuit that protects the circuit elements of the motor control circuit 10 from electrostatic charges of the ports 12, 16, 20, 24a, And an ESD protection circuit (ESDPC). For example, the ESDPC may include an ESDPC 72c between the output ports 24a and 24b, an ESDPC 72b of the PDC port 20 and an ESDPC 72c between the sleep port 16 and the power supply voltage port 12. [ ). In one example, the motor control circuit 10 may be an integrated circuit in which the ports 12, 16, 20, 24a, 24b, 34 are formed as fins.
As will be described below, the DLSS control circuit 62 receives DLSS input signals. Generally, the DLSS control circuit 62 provides four DLSS output signals to the H-bridge circuit 64 via the bus 84, in response to the received DLSS input signals. For example, bus 84 may be a serial bus. The four DLSS output signals are each provided to the corresponding transistors of the H-bridge circuit 64 to generate the motor signal at the ports 24a, 24b. For example, the corresponding transistors may be a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.
In one example, a first voltage signal is provided to the ports 24a, 24b when the transistor pair Q1, Q4 is conductive and a second voltage signal is applied to the ports 24a, 24b when the transistor pair Q2, A second voltage signal is provided. Particularly, in one example where the motor 100 is a brushless motor, at 100% duty cycle, the transistor pair Q1, Q4 conducts for 50% of the time the first voltage signal (32a in FIG. 1B) The transistor pair Q2, Q3 conducts for the remaining 50% of the time that the second voltage signal (34a in Fig. 1B) is provided.
Due to the high currents flowing through the ports 24a and 24b, some applications may not require transistor pairs that are continuously conducting for a period of time, such as transistor pair Q1, Q4 and transistor pair Q2, Q3 . For example, when the motor 100 stalls, i.e., stall or decelerates, more current may flow than when the motor 100 rotates due to a back electromotive force. In the example of FIG. 1B, in which the motor 100 is a brushless motor, at 100% duty cycle, the transistor pair Q1, Q2 is turned on for a time such as between 0 and t1, between t2 and t3, Q4) may not be required to provide a continuous high voltage level. Similarly, in a 100% duty cycle, it may be unnecessary to provide a continuous high voltage level for the transistor pair (Q2, Q3) during times such as between t1 and t2, between t3 and t4, such as the second voltage signal 34a have. Rather, as shown in FIG. 1C, the transistor pair Q1, Q4 is connected to the ports 24a, 24b (not shown) in the form of pulse strings such as, for example, a pulse train 33a between 0 and t1 and a pulse train 33b between t2 and t3 To provide the first voltage signal 32b. Similarly, the transistor pair Q2 and Q3 is connected to the ports 24a and 24b in the form of pulse strings such as a pulse string 35a between t1 and t2 and a pulse string 35b between t3 and t4, 34b. In one example, the first voltage signal 32b and the second voltage signal 34b may be coupled to the transistors of each transistor pair, such as, for example, transistor Q1 is periodically disconnected and reconnected. Can be generated by periodically repeating a process in which one of the currents is floated to reduce the current and then reconnected. In another example, one of the transistors of the other transistor pair may be turned on periodically. For example, the transistor Q3 may be periodically turned on to reduce the current of the transistor Q1. In one example, the DLSS control circuit 62 controls the turn-on and turn-off of the transistors Q1, Q2, Q3, Q4. In order to prevent a short between the power supply voltage and the ground, the transistors Q1 and Q3 are not simultaneously turned on, and the transistors Q2 and Q4 are not simultaneously turned on.
In one example of a DLSS input signal, a sleep control signal is applied to an enable signal provided to the PSC circuit 42 in response to an enabled sleep port 16, i. E., Applied to a sleep port 16 and via a connection line 70 In response, it is provided from the PSC circuit 42 to the DLSS control circuit 62 via the connection line 74. In one example, the enable signal transitions the sleep signal applied to the sleep port 16 from a high voltage level to a low voltage level. The DLSS control circuit 62 causes the transistors of the H-bridge circuit 64 to go to the sleep mode in response to the received sleep control signal. That is, the transistors Q1, Q2, Q3, and Q4 are turned off, and most of the other circuits in the motor control circuit 10 are inactivated.
In another example of a DLSS input signal, a stall signal is provided from the stall detector 46 to the DLSS control circuit 62 via a link 76 when the motor 100 is stalled. The stall detector 46 determines whether the motor 100 is stalled based on the received rotor commutation signal. The rotor commutation signal is generated by a Hall effect circuit 52. The hall effect circuit 52 senses the magnetic field from the motor 100. [ For example, the Hall effect circuit 52 may sense the magnetic field by detecting the position of an alternating pole ring magnet having an alternating pole from the motor 100. The hall effect circuit 52 also includes a signal that is termed the rotor rectification circuit and has a period proportional to the speed of the motor and amplified by the amplifier 56 and provided to the stall detector 46 via the connection line 78 . In one example, an additional circuit (not shown) for converting the signal provided in the Hall effect circuit 52 from a sinusoidal wave to a pulse train may be included. For example, the sinusoidal signal may be chopped, sampled, passed through a low-pass filter, gain improved, and provided to a comparator with a Schmitt Trigger to produce a rotor commutation signal 78 ) Represents a pulse train. As is well known in the art, there are various types of Hall effect elements such as, for example, a planar Hall element and a vertical Hall element. In another embodiment, the Hall effect circuit may be replaced by any magnetic field sensor. For example, the magnetic field sensor may be a magnetotransistor or a Giant Magnetoresistive (GMR) device, an Anisotropic Magnetoresistive (AMR) device, and a Tunneling Magnetoresistive (TMR) And magnetic tunnel junctions (MTJs). ≪ RTI ID = 0.0 > [0040] < / RTI >
When the stall detector 46 determines that the speed of the motor 100 is less than the threshold stall speed threshold based on the rotor commutation signal, the stall signal is provided to the DLSS control signal 62, The duty cycle of the motor 100 is increased and the motor 100 is prevented from stalling. In one example, in order to avoid unnecessary conditions such as full current flow to the stalled motor, the DLSS control circuit 62 turns the output on and off for the polarity determined by the Hall commutation circuitry And performs an anti-stall algorithm. For example, the anti-stall algorithm may continue until a rotation occurs or the sleep signal goes low.
The various connection lines described herein may be described interchangeably with the signals carried by the respective connection lines. For example, reference numeral 78 may be used interchangeably to indicate a connection line between the amplifier 56 and the stall detector 46 and the rotor commutation signal associated with the connection line.
In another example of a DLSS input signal, the rotor commutation signal 78 is provided directly from the amplifier 56 to the DLSS control circuit 62 via a connection 78 to provide a feedback signal to monitor the speed of the motor 100 . The feedback signal 78 is also provided to the speed detection circuit of Figs. 5A and 5B. During the 100% duty cycle mode, the Hall effect circuit 52 determines which transistor pair is on and which transistor pair is off, that is, determines the direction of the current flowing in the motor 100, determines the rotational direction of the motor , It is possible to judge which transistor pair has been switched to the active state through the magnetic pole of the motor 100. For example, the stimulus of the motor may be an Arctic or Antarctic.
In another example of the DLSS input signal, a thermal shutdown signal is provided from the thermal shutdown protection circuit 68 via the connection line 80 when the motor is overheated. In one example, the thermal shutdown protection circuit 68 measures the forward voltage of the diode (not shown) of the H-bridge circuit 64 having a known temperature transfer curve through the connection line 81. For example, a known temperature characteristic parameter, such as a diode's knee voltage, and a temperature-independent fixed reference value are compared. When the difference in the comparison result reaches a certain threshold value, the thermal step circuit 68 provides the thermal step signal. When receiving the train stop signal, the DLSS control signal 62 turns off one or more of the transistors Q1, Q2, Q3, and Q4.
The PWM control circuit 38 is connected to the DLSS control circuit 62 via a connection line 82 based on at least one of the power supply voltage, the activation signal and the rotor commutation signal 78, And provides a PWM output signal. The power supply voltage is received via the connection line 86 from the supply voltage port 12, for example, as shown in Figs. 7A and 7B. The activation signal is provided via a connection line 88 in the PSC circuit 42, for example, as shown in FIG. The rotor commutation signal 78 is received via the amplifier 56 from the Hall effect circuit 52 as shown in FIG. The PWM output signal 82 has a duty cycle corresponding to the input control signal provided at the PDC port 20 and provided to the PWM control circuit 38 via the connection line 92. In one example, the PWM control circuit 38 causes the output signal 84 of the DLSS control circuit 62, which is the motor control signal, to generate a duty cycle of the 100% duty cycle signal to the user via the PDC port 20 The speed of the motor 100 is controlled by down-converting it to a duty cycle determined by the duty cycle. For example, when the speed of the motor is controlled, a predetermined time has elapsed, or in another example, the motor 100 has reached a predetermined speed.
Embodiments of the PWM control circuit will become more apparent from the following description with reference to Figs. 2, 4, 7A and 7B. For example, some of the signals input to the PWM control circuit 38 are optional signals used for sensing, and not all of the input signals are used in all embodiments of the PWM control circuit.
Referring to FIG. 2, a PWM control circuit 138, which is an example of a PWM control circuit 38, is shown. The PWM control circuit 138 includes a timer 144 coupled to the PWM sequencer 146 via a PWM sequencer 140 and a connection line 146. As shown, the activation signal 88 provided from the PSC circuit 44 is applied to a timer 144. [
In one example, when the sleep mode is enabled, the PWM output signal 82 is not provided by the PWM sequencer 140. When the sleep mode is deactivated, the DLSS control circuit 62 provides a 100% duty cycle signal to the ports 24a, 24b as shown in FIG. 1b or 1c and the PSC circuit 42 provides a 100% And activates the timer 144. The timer 144 is activated when the timer 144 is activated. After a predetermined time has elapsed, i.e., a time corresponding to the time the motor 100 has taken to reach the predetermined speed, the timer 144 causes the PWM sequencer 140 to generate an enable signal 146 To provide a PWM output signal 82 based on the input control signal received at the PDC port 20. [ In one example, the timer 144 is a countdown counter. In one example, the timer may be adjusted by a circuit (not shown) that detects the voltage level for the selected duty cycle to account for the different selected duty cycle.
One example of the PWM sequencer 140 of FIG. 2 is shown in FIG. The PWM sequencer 140 includes a duty cycle logic circuit 150 and a PWM oscillator 160. The duty cycle logic circuit 150 is coupled to a reference voltage source 154, which may include a reference current source 152 and one or more reference voltages. The PWM oscillator 160 is connected to the duty cycle logic circuit 150 by a connection line 164 and to the PWM enable circuit 162 via a connection line 166. In one example, a resistor (not shown) is connected to the PDC port 20 from outside the motor control circuit 10 and a voltage is applied to the PDC port 20 such that current flows from the reference current 152 to the resistor / RTI > The duty cycle logic circuit 150 compares the voltage of the PDC port 20 with the reference voltage 154 and provides a duty cycle control signal 164 to the PWM oscillator 160. The PWM oscillator 160 uses the duty cycle control signal 164 to provide the PWM oscillator output signal 166 to the enable circuit 162.
Referring to FIG. 3B, the duty cycle control circuit 150 ', which is an example of the duty cycle control circuit 150, is shown. The duty cycle control circuit 150 'uses three different voltage levels received at the PDC port 20. The duty cycle control circuit 150 'includes a window comparator 172 and a decoder circuit 174.
The window comparator 172 is connected to the PDC port 20 and the second threshold voltage 154b through a connection line 92 via a comparator 174a and a connection line 92 connected to the PDC port 20 and the first threshold voltage 154a via a connection line 92. [ And a comparator 174b connected to the comparator 174b. The output of comparator 174a is applied to AND gate 176a and is applied to AND gate 176b and AND gate 176c via inverter 178a. The output of comparator 174b is applied to AND gate 176a and AND gate 176b and is applied to AND gate 176c via inverter 178b. Outputs 180a-180c of AND gates 176a-176c are provided to decoder circuit 174, respectively. Decoder circuit 174 provides a corresponding duty cycle control circuit 164 to PWM oscillator 160 based on outputs 180a-180c of AND gates 176a-176c.
In one example, when the voltage level provided at the PDC port 20 has a voltage level that is higher than the first and second threshold voltages 154a, 154b, the output signal 180a has a logic state of 1 The output signals 180b and 180c have opposite logic states. When the voltage level provided at the PDC port 20 has a voltage level between the first and second threshold voltages 154a and 154b, the output signal 180b has a logic state of 1 while the output signals 180a, 180a, 180c have opposite logic states. When the voltage level provided at the PDC port 20 has a lower voltage level than the first and second threshold voltages 154a and 154b, the output signal 180c has a logic state of 1, 180a, 180b have opposite logic states. In one example of the duty cycle logic control circuit 150 ', the first reference voltage 174a is about 2V and the second reference voltage 174b is about 1V. In other examples, the first and second threshold voltages 154a and 154b may be fixed reference voltages or ratiometric reference voltages. That is, the reference voltages may be scaled up and down according to the increase or decrease of the power supply voltage, respectively.
In another example, the voltage value provided at the PDC port 20 is detected by the window comparator 172 in the duty cycle logic circuit 150 to determine whether the voltage value is the ground voltage, the power supply voltage, or the floating voltage . When the user does not apply the ground voltage or the power supply voltage to the PDC port 20, the motor control circuit 10 includes a voltage divider (not shown) capable of setting a half value of the power supply voltage . The voltage value provided at the PDC port 20 is decoded by the duty cycle logic circuit 150.
3A, when the enable signal 146 is received, the enable circuit 162 provides the PWM output signal 82 based on the PWM oscillator output signal 166. In one example, the PWM enable circuit 162 includes a switch (not shown) to provide a PWM oscillator output signal 166 as a PWM output signal 82 when the switch is closed by an enable signal 146 . In another example, the PWM enable circuit 162 may include an amplifier (not shown) to provide a PWM output signal 82, which is an amplified form of the PWM oscillator output signal 166.
Referring to FIG. 4, there is shown a PWM control circuit 238 including a threshold speed comparison circuit 250, which is another embodiment of the PWM control circuit 38. The threshold speed comparison circuit 250 determines the speed of the motor 100 based on the rotor commutation signal 78. For example, the threshold speed comparison circuit 250 may determine whether the speed of the motor 100 matches the threshold speed, and determine whether the speed of the PWM sequencer 140 And transmits the enable signal. When enabled, the PWM sequencer 140 provides a PWM output signal 82 having a duty cycle corresponding to the input control signal provided at the PDC port 20.
Referring to FIG. 5A, a threshold-speed comparison circuit 250 ', which is an example of the threshold-speed comparison circuit 250, is shown. The threshold speed comparator circuit 250 'includes a counter 312, a digital comparator 322 and a preset threshold register 332. The counter 312 is applied with a rotor commutation signal 78 and reference clock 342, for example in the form of a pulse train. Digital comparator 322 is coupled to counter 312. The threshold preset register 332 is coupled to the digital comparator 322. The counter receives pulses from the rotor commutation signal for a predetermined time that is equal to the duration of the clock pulse of the reference clock 342. The pulses received from the rotor commutation signal 78 within the predetermined time are each counted and the value of the total number of pulses received is assigned by the counter 312. After the predetermined time, the counter 312 is reset. Digital comparator 322 compares the counted value provided in counter 312 with a preset threshold value. If the value stored in the counter 312 is greater than or equal to the predetermined threshold value in the threshold preset register 332, the digital comparator 322 provides the enable signal 246, e.g., a logic high voltage level, (140 in FIG. 4). In one example, once the enable signal 246 has been latched into the PWM mode, the enable signal is not inverted until the motor control circuit 10 goes into sleep mode or repeats turn-off and turn-on.
Referring to FIG. 5B, a threshold speed comparison circuit 250 " is shown, which is another example of the threshold speed comparison circuit 250. The components of FIG. 5B are arranged differently than the components of FIG. 5A. The threshold speed comparison circuit 250 " includes a counter 312, a digital comparator 322, and a threshold preset register 332. [ The counter 312 receives clock pulses from the reference clock 342 via the connection line 362. Digital comparator 322 is coupled to counter 312. The threshold preset register 332 is coupled to a digital comparator 322 coupled to the output of the digital comparator 322. The counter 312 stores a value corresponding to the number of the received clock pulses while the rotor commutation signal 78 has a special logic state, for example, a logic high state. The counter is reset 312 if, for example, the rotor commutation signal transitions to another logic state, such as a logic low state. Digital comparator 322 compares the counted value provided in counter 312 with the preset threshold stored in threshold preset register 332. [ If the counted value stored in the counter 312 is less than the preset threshold stored in the threshold preset register 332, the digital comparator 322 provides an enable signal 246, for example a logic high voltage level do. For example, the rotor commutation signal 78 may reset the counter 312 to cause the counter to always reach a high value when the motor 100 rotates slowly, and the speed of the motor 100 The faster the reset pulses so that the counter 312 does not reach the predetermined threshold value.
Referring to FIG. 5C, a threshold speed comparison circuit 250 " 'is shown, which is yet another example of a threshold speed comparison circuit 250. The threshold-speed comparison circuit 250 '' 'includes a voltage comparator 372 and an AND gate 380. One input of the voltage comparator 372 is connected to a fixed reference voltage 364 and the other input is connected to a reference voltage source 366 and a capacitor 368. The output of the AND gate 380 is connected to a capacitor 368 and the first input is connected to the one-shot generator 376 and the second input is connected to the PSC circuit 42 ). The voltage comparator 372 compares the voltage across the capacitor 368 with the fixed reference voltage 364. [
The reference current source 366 connected to the PSC circuit 42 is activated in response to the activation signal 88. When activated by the PSC circuit 42, the reference current source 366 charges the capacitor 368 to linearly increase the voltage across the capacitor over time. In one example, if the voltage across the capacitor 368 is lower than the fixed reference voltage, such as when the motor is at a high speed, an enable signal 246, such as, for example, the enable signal 408 of FIG. 6, Is transited to a logical high level to cause the PWM sequencer (140 in FIG. 4) to provide the PWM output signal 82. On the other hand, when the voltage across the capacitor 368 is higher than the fixed reference voltage, such as when the speed of the motor is slow, the enable signal 246 is maintained at a logic low level so that the PWM sequencer (140 in FIG. 4) So that it does not provide the PWM output signal 82.
The voltage across the capacitor 368 increases until it is reset. One shot generator 376 provides a pulse signal to AND gate 380 at the edge portion of rotor rectifier circuit 78 having a pulse train. The PSC circuit 42 also provides an enable signal 88 to the AND gate 380. For example, if the pulse signal provided by activation signal 88 and one shot generator 376 has a logic high voltage level, AND gate 380 provides a reset signal to capacitor 368 to discharge the capacitor.
In another example, the threshold speed comparison circuit 250 may not operate based on a single detection of the rotor speed signal 78 at a particular speed. For example, the circuit of FIG. 5C can detect that one or more specific speeds have been reached before considering the non-uniformity of the magnetic signal emitted from the motor 100 by providing the PWM signal. have. For example, before the enable signal 246 indicates that the motor 100 has reached a certain speed, the voltage across the capacitor is measured to be at least greater than the reference voltage 364 for four different cases .
6 is a timing diagram 400 illustrating various waveforms associated with the motor control circuit 10 (Fig. Ia). 6, motor speed curve 402, rotor commutation signal 404, reference clock signal 406, and enable signal 408 are shown. The motor speed curve 402 is shown, for example, as a graph of speed-time. The rotor commutation signal 404 may be provided at the output of the amplifier 56 of FIG. 1A. The reference clock signal 406 may be provided by the reference clock 342 of FIGS. 5A and 5B. The enable signal 408 may be, for example, the enable signal 146 provided at the output of the timer 144 of Figure 2 or the enable signal 246 provided at the output of the threshold speed comparator 250 of Figure 4 ).
While the motor 100 is being driven, the speed of the motor speed curve 402 is increased by applying the 100% duty cycle to the motor 100 as shown in FIG. 1B or 1C. Once the predetermined motor speed is detected, the PWM control circuit 38 reduces the duty cycle of the motor control signal 84. As shown in FIGS. 2 and 4, the speed of the motor can be determined by measuring the time or the speed of the motor 100, respectively. For example, using a PWM control circuit (138 in FIG. 2), after a predetermined time has elapsed according to the power applied to the motor control circuit 10, that is, when the sleep signal is not enabled in the port 16 It is determined whether the motor has reached a predetermined speed. At time t T the enable signal is sent from the timer 144 to the PWM sequencer 140 and the PWM sequencer 140 provides the PWM output signal 82 to the internal control And sets the duty cycle of the motor control signal 84 to correspond to the signal.
In another example, the PWM control circuit (238 of FIG. 4) is used to determine whether the motor 100 has reached the threshold speed by the threshold speed comparison circuit 250. For example, the determination may be performed by counting the number of pulses of the rotor commutation signal corresponding to the predetermined threshold stored in the preset register 332 of FIG. 5A. The threshold speed corresponds to the threshold speed (V T ) in the motor speed signal (402). When the motor speed signal 402 reaches the threshold speed V T , the enable signal 246 is sent from the threshold speed comparison circuit 250 to the PWM sequencer 140 and the PWM sequencer 140 receives the PWM output Signal 82 to set the duty cycle of the motor control signal 84 to correspond to the internal control signal received at the PDC port 20. [ When the duty cycle signal is reduced from the 100% duty cycle to the selected duty cycle, the speed of the motor is increased until it reaches a speed corresponding to the selected duty cycle, for example, a time to reach a speed V D t S ).
7A, a PWM control circuit 338, which is another example of the PWM control circuit 38, is shown. The PWM control circuit 338 maintains the speed of the motor 100 substantially constant when the power supply voltage changes. The PWM control circuit 338 includes a PWM sequencer (140 in FIG. 3) coupled to the speed determination circuit 400 via a speed determination circuit 400 and a connection line 446.
In one example, the speed determination circuit 400 includes a timer 144 of FIG. In another example, the speed determination circuit 400 includes the threshold speed comparison circuit 250 of FIG.
The PWM control circuit 338 also includes a comparator 442 that compares the power supply voltage provided from the power supply voltage port 12 via the fixed reference voltage 444 and the connection line 86. 3, the duty cycle logic circuit 150 provides a duty cycle control signal 164 to the PWM oscillator 160 to generate a PWM output signal (e. G., A duty cycle control signal 164) in accordance with the internal signal applied to the PDC port 20. < 82 < / RTI > The duty cycle logic circuit 150 further adjusts the duty cycle of the PWM output signal 82 by responding to the signal received from the comparator 442 and providing a signal corresponding to the PWM oscillator 160, The duty cycle of the signal 82 is inversely proportional to the power supply voltage. For example, when the power supply voltage decreases, the duty cycle logic circuit 150 provides a higher voltage signal to the PWM oscillator 160 to increase the duty cycle, And maintains the selected speed through the port 20.
The enable circuit 162 receives an enable signal 446. In one example, the enable signal 446 may be provided in the form of a signal 146 from a timer (144 in FIG. 2). In another example, the enable signal 446 may be provided in the form of a signal 246 from a threshold speed comparison circuit (250 in FIG. 4).
Referring to FIG. 7B, there is shown a PWM control circuit 438, which is another example of a PWM control circuit (38 in FIG. 1). The PWM control circuit 438 includes a speed determination circuit 400 and a PWM sequencer 140 '. The PWM sequencer 140 'includes a voltage comparator (442 of FIG. 7A) and is substantially similar to the PWM sequencer 140 of FIG. 3 except that it responds to the power supply voltage level. The voltage comparator 442 compares the power supply voltage with the reference voltage (154 in Fig. 3). The reference voltage 154 is also used in the duty cycle logic circuit 150 for comparison with the voltage of the PDC port 20, as described in connection with FIG.
7A or 7B, the speed of the motor 100 is controlled within a narrow speed range for the temperature change and the motor application. Since the speed of the motor 100 is primarily related to the current flowing through the motor coil, if the duty cycle is inversely proportional to the power supply voltage as described above, the speed of the motor is controlled within a narrower range. For example, two of the four transistors Q1, Q2, Q3 and Q4 of the H-bridge 64 must be turned on in order for current to flow in the motor coil. If the two transistors are in series, the total resistance value is about 4 ohms. The resistance value of the motor coil may be 26 ohms. Therefore, when the power supply voltage is 3V, the current flowing through the motor coil is 100mA. When the power supply voltage is 4 V, the current flowing through the motor coil is about 133 mA. For a fixed duty cycle, the speed of the motor is about 33% faster than the case of having a power supply voltage value of 3V with a power supply voltage value of 4V.
The duty cycle is changed to be adjusted according to the power supply voltage. For example, for a supply voltage of 4V, the duty cycle may be adjusted to (3V / 4V) * 80% or 60% duty cycle when an 80% duty cycle is selected for a supply voltage of 3V, Can be kept constant with respect to the change of the power supply voltage.
Referring to Fig. 8, there is shown a motor control circuit 10 'including a sub-circuit 600 used during braking of a motor 100, which is an example of a motor control circuit 10. Fig. The subcircuit 600 includes a speed decision circuit 612 in a driving / braking logic circuit 602, a PSC circuit 42 and a PWM control circuit 38. The drive / braking logic circuit 602 is connected to the DLSS control circuit 62 via a connection line 604 and to the PSC circuit 42 via a connection line 606. The speed determination circuit 612 is connected to the PSC circuit 42 via a connection line 610.
In operation, the drive / braking logic circuit 602 receives the sleep signal from the sleep port 16 via the connection line 608. When the sleep mode is enabled, the drive / braking logic circuit 602 sends a motor direction change signal to the DLSS control signal 62 via the connection line 604, And reverses the direction of the motor by reversing the pairs of transistors in the on state, if any. The drive / braking logic circuit 602 transmits a braking signal to the PSC circuit 42 via a connection line 606.
The speed determining circuit 612 receives the rotor commutation signal via the connection line 78 and determines whether the motor 100 is decelerating. In one example, the threshold speed comparison signal 250 " of Figure 5B can be used to detect deceleration instead of acceleration of the motor 100. [ When the speed determining circuit 612 determines that the speed of the motor has reached a predetermined threshold speed, a brake enable signal is transmitted to the PSC circuit 42 via the connecting line 610. [ When both the braking enable signal 610 and the braking signal 606 are received, the PSC circuit 42 transmits the slip control signal 74 to the DLSS control circuit 62 so that the motor control circuit 10 ' Mode. That is, the transistors Q1, Q2, Q3 and Q4 are not conducted and most of the other circuits in the motor control circuit 10 'are inactivated. For example, receiving the braking signal 606 by the PSC circuit 42 is not due to the stall of the motor but as an additional protection for the occurrence of the predetermined braking. In another embodiment, the connection line 606 is removed and the sleep mode may be initiated based solely on the speed determination circuit 612 to determine if the predetermined threshold speed has been reached. In another embodiment, if a sleep signal is received via the connection line 608 from port 16, the sleep mode may be initiated directly without braking or changing polarity.
Referring to FIG. 10, an example of a method 700 for braking the motor 100 using the motor control circuit (10 'in FIG. 8) is shown. In method 700, the motor 100 maintains a running mode (702) until the sleep port 12 is enabled. That is, the motor 100 operates at the predetermined speed set by the input control signal applied to the PDC port 20. In one example, the sleep port is enabled when a low voltage signal is received. If it is determined that the sleep port is enabled (706), the braking operation is initiated (712). For example, a braking signal 606 is sent from the drive / braking logic circuit 602 to the PSC circuit 42, and a motor direction change signal 604 is sent to the DLSS control signal 62, The direction of rotation is reversed. If the speed of the motor 100 is determined to have reached a certain speed (716), a low power consumption mode is initiated (722). For example, the speed determination circuit 602 transmits the braking enable signal 610 to the PSC circuit 42. When both of the braking enable signal 610 and the braking signal 606 are received, the PSC circuit 42 transmits a slip control signal 74 to the DLSS control circuit 62, Q2, Q3, and Q4 and deactivates most of the other circuits in the motor control circuit 10 '.
Figure 11 is a block diagram of a motor control circuit 10 'associated with the motor control circuit 10' of Figure 8 and having three operations: a running mode phase 802, a braking phase 804 and a sleep mode phase 806 Is a timing diagram 800 illustrating various waveforms associated with the phases. In FIG. 11, motor speed curve 812, rotor commutation signal 822, reference clock signal 832, sleep signal 842, and brake enable signal 852 are shown. The motor speed curve 812 appears as a graph of speed-time. The rotor commutation signal 822 may be provided at the output of the amplifier 56 of FIG. The reference clock signal 832 may be provided at the output of the reference clock 342 of FIG. The sleep signal 842 may be provided at the sleep port 16. The drive enable signal 852 may be provided at the output of the threshold-speed comparison circuit 250 ', 250 " of FIG.
During the operating mode phase 802, the speed of the motor 100 in the motor speed curve 812 maintains a constant speed V D corresponding to the motor operating at a constant speed. For example, if the sleep signal 842 transitions from a logic high level to a logic low level at time t B , the operating mode phase 802 is terminated and the braking mode phase 804 is started. In the braking phase 804, the speed of the motor begins to decrease at the speed V D , becomes the threshold speed (V T ) at time t P , and the sleep mode phase 806 begins. For example, the time t P may be a time when the braking enable signal 852 transitions to a logic high level.
Referring to Fig. 12, a motor control circuit 10 " is shown, which is another embodiment of the motor control circuit 10. Fig. The motor control circuit 10 " includes a multifunction port 916 that receives control signals from an external source. For example, the control signal may be a digital signal. In one example, the multifunctional port 916 may be replaced by a PDC port 20 and a sleep port 16. As will be described below, the control signal provided to the multifunctional port 916 drives the motor 100, activates the motor in the PWM mode by providing the PWM signal, brakes the motor, To make the other circuits in the motor control circuit 10 " Q1, Q2, Q3, Q4 and the motor control circuit 10 " become the sleep mode.
The motor control circuit 10 " includes a control logic circuit 920 and a sleep logic circuit 924. [ The control logic circuit 920 is connected to the multifunctional port 916 via a connection line 922 and to the DLSS control circuit 62 via connection lines 926, 928 and 930. The sleep logic circuit 924 is connected to the control logic circuit 920 via connection lines 928 and 930 and to the DLSS control circuit 932 via a connection line 932.
In one example, connection line 926 provides an awake signal, connection line 928 provides a motor control signal, connection line 930 provides a braking signal, and connection line 932 provides a sleep signal to provide. For example, the motor control signal may be a PWM signal. In one example of a logic state, the awake signal 926 provided to the DLSS control circuit 62 turns on the motor 100 in the sleep mode. In one example, the awake signal 926 provided to the DLSS control circuit 62 drives the motor 100 at 100% duty cycle. In one example of a logic state, the motor control signal 928 provided to the DLSS control circuit 62 controls the speed of the motor, and the braking signal 930, which is provided to the DLSS control circuit, . In one example of a logic state, the sleep signal 932 provided to the DLSS control circuit 62 causes the motor control circuit 10 to enter the sleep mode.
Referring to FIG. 13, in one example, the control logic circuit 920 includes a window comparison circuit 937. The comparator 940a is connected to the multifunctional port 916 and the positive threshold voltage 938a via a connection line 922 and the comparator 940b is connected to the multifunctional port 916 and the positive threshold voltage 938a via the connection line 922. The window comparator 937 includes comparators 940a and 940b, Is connected to the multifunctional port 916 and the negative threshold voltage 938b via a connection line 922. [ The output of comparator 940a is applied to AND gates 942b and 942c and applied to AND gate 942a via inverter 941a. The output of comparator 940b is applied to AND gates 942a and 942c and applied to AND gate 942b via inverter 941b.
The output of the AND gate 942a is applied to the latch circuit 944. The output of the AND gate 942c is applied to the inverter 941c. The output of the latch circuit 944 is provided as an awake signal 926 and the output of the inverter 941c is provided as a motor control signal 928 and the output of the AND gate 942b is provided as a braking signal 930 do.
In one example, in the sleep mode, the multifunction port 916 receives a signal having a voltage level higher than the positive threshold voltage 938a. Correspondingly, the output of the AND gate 942a becomes, for example, a logic high voltage level, and the outputs of the AND gates 942b and 942c become, for example, a logic low voltage level. The latch circuit 944 latches, for example, a logic high voltage level and provides an awake signal 928. The output of the latch circuit 944 may remain latched until it is reset, for example, by a sleep signal 932 having a logic high voltage level.
If the control signal received at the multifunction port 916 has a voltage level between a positive threshold voltage 938a and a negative threshold voltage 938b, for example, the motor control signal 928 may be at a logical high voltage level While the braking signal 930 has a logic low voltage level. The motor control signal 928 is proportional to the control signal received at the multifunctional port 916 while having a voltage level higher than the negative threshold voltage 938b.
When the control signal received at the multi-function port 916 has a voltage level lower than the negative threshold voltage 938b, for example, the braking signal 930 has a logic high voltage level. For example, when control logic circuit 920 receives a negative logic high voltage level, control circuit 926 sends braking signal 930 to sleep logic circuit 930 and the DLSS To the control circuit 62, and brakes the motor 100 when the braking enable signal is received. The DLSS control circuit 62 can brake the motor 100 using various techniques.
In the first technique, the DLSS control circuit 62 can reverse the polarity of the H-bridge circuit 64 to drive the motor 100 in the opposite direction. In one example of the first technique, the DLSS control circuit 62 provides a motor control signal 84 to rotate the motor 100 in the opposite direction with a 100% duty cycle. In the second technique, the DLSS control circuit 62 can provide a motor control signal 84 to short-circuit the coils of the motor 100, thereby stopping the rotation of the motor 100 using a back electromotive force (back EMF) .
14, in one example, the sleep logic circuit 924 includes an OR gate 946 connected to a timer circuit 948 and a speed detection circuit 949 and providing a sleep signal 932 . The timer circuit 948 includes a counter 950 that counts the number of clock pulses received from the reference clock 952. The timer circuit 948 receives the motor control signal 928 inverted by the inverter 951. The inverted motor control signal 928 serves as a reset signal for the counter 950. The digital comparator 954 compares the counted value with a timeout threshold value stored in a timeout threshold register 956. For example, if the number of clock pulses is greater than or equal to the timeout threshold, a logic high voltage level is provided to the OR gate 946. In one example, the timer circuit 948 is used to wait a predetermined amount of time while the control signal received at the multi-function port 916 is, for example, 0V, i.e., before the sleep mode is started. For example, the predetermined time may be 1 ms.
The speed detection circuit 949 determines when the speed of the motor 100 reaches the threshold speed based on the rotor commutation signal 78. [ For example, the speed detection circuit 949 determines when the speed of the motor 100 has decreased by the threshold speed while the motor 100 is being braked. The OR gate 946 is provided when the threshold speed reaches, for example, a logic high voltage level. In one embodiment, the speed detection circuit 949 has a configuration similar to the threshold speed comparison circuit 250 of FIG. 4, except for the configuration for measuring the deceleration of the motor speed. In another embodiment, the speed detection circuit 949 may be replaced by a timer circuit having a configuration similar to the timer circuit 948, for example. When one of the timer circuit 948 or the speed detection circuit 948 provides a logic high voltage level, the OR gate 946 provides a sleep signal 932 having, for example, a logic high voltage level to the DLSS control circuit 62 ).
In one example, the DLSS control circuit 62 may be used to convert the frequency of the motor control signal 928 to a frequency suitable for the H-bridge circuit 64. In this example, to convert a high frequency control signal to a low frequency, the DLSS control circuit 62 distributes the high frequency down while maintaining the integrity of the control signal. As described above, the configuration in which the DLSS control circuit 62 distributes the frequency downwardly allows the motor control circuit 10 " to control the IC when frequencies that can be received by the H- For example. In another example, the PWM signal is provided directly to the H-bridge circuit 64 by bypassing the DLSS control circuit 62.
Referring to FIG. 15, the motor control circuit 10 " may be used in a system 960 that includes a microprocessor 962. The microprocessor 962 includes an input / output (I / O) port 964 connected to the multifunctional port 916 via a connection line 966. The microprocessor 962 may provide the control signal from the I / O port 964 to the multifunctional port 916. The power source voltage is supplied from the battery 970 to the power source voltage port 12. Capacitor 980 is connected to power supply voltage port 12, battery 970 and ground. The capacitor 980 is a bypass capacitor and is used to prevent current spikes from damaging the signal provided at the power supply. For example, the current spikes may be generated by switching the outputs fast during the PWM mode.
In one example, the microprocessor 962 provides a control signal to control the brush motor so that the microprocessor designed to drive the brush motor has a motor control circuit 10 " for driving a brushless motor Can be used together.
In a particular example, the system 960 is a mobile phone system and the motor 100 is a vibration motor. Generally, the vibration motor is designed to operate quickly by continuously driving the H-bridge circuit 62 in the acceleration section, which reaches the final speed of the motor. The final speed of the motor is much higher than the optimal ratio for optimally vibrating the vibration motor. As a result, the PWM signal is used to reduce the final speed of the motor to the speed for vibrating the vibration motor to a desired level. And a multi-function port 916 for receiving the PWM signal from the outside, so that the speed of the motor can be changed by changing the PWM duty cycle of the PWM input signal. Also, as opposed to an internally generated PWM input signal to regulate the motor 100 to only one fixed motor speed, i.e. one fixed vibration level, the multifunctional port 916 is connected to the caller ID application Various vibration tones to be implemented can be set.
16, in one example, the microprocessor 962 may provide a control signal 982 to the multifunctional port 916. The control logic circuit 920 provides the awake signal 926, the motor control signal 928, the braking signal 930 and the sleep signal 932 in response to the control signal 982. The response corresponding to the speed of the motor in the speed-time curve 986 is shown.
In one example, if the control signal applied to the multifunction port 916 has a voltage level between threshold voltages 938a, 938b, such as within 0V or +/- 0.5V for 1ms, the sleep logic circuit 924 Provides slip signal 932 to DLSS control circuit 62 to cause motor control circuit 10 " to operate in sleep mode phase 988a. For example, the braking signal 932 is a logic high voltage level. The speed of the corresponding motor during sleep mode phase 988a is zero, as shown in the first area 989 of the speed-time curve 986. In one example, the motor control signal 928 provided to the sleep logic circuit 922 in the control logic circuit 920 causes the counter 950 to exit the reset mode. If the sleep logic circuit 924 counts the number of clock pulses exceeding the timeout threshold before the counter is reset, e. G., Before the motor control signal 982 transitions to a logic low voltage level, Lt; / RTI > provides a sleep signal 932.
Control logic circuit 920 is coupled to DLSS control circuit 62 when multifunctional port 916 receives a control signal having a logic high voltage level, such as 4.5V, for example, which exceeds a positive threshold voltage 938a. Wake signal 926 to cause the motor 100 to operate in the start mode phase 990. [ In one example, the control signal provided at multifunction port 916 provides a signal to drive the motor at 100% duty cycle. The speed of the corresponding motor increases linearly during start mode 990, as shown in the second area 991 of the speed-time curve 986. [ In one example, the awake signal 928 latches the state of a logic high voltage level and the sleep signal 932 transitions to a logic low voltage level.
The control logic circuit 920 provides the PWM signal as the motor control signal 928 to the DLSS control circuit 62 to cause the motor 100 to output the PWM signal, For example, 100% duty cycle to a duty cycle corresponding to the duty cycle of the PWM signal, thereby causing the motor 100 to operate in the PWM mode phase 992. During the PWM mode phase 992, the speed of the corresponding motor increases linearly until it reaches a speed corresponding to the PWM signal, as shown in the third area 993a of the speed-time curve 986 And then maintains a constant speed as shown in the fourth region 993b of the speed-time curve 986. [
Control logic circuit 920 receives a control signal having a logic low voltage level such as -4.5 V below multivunction port 916 negative threshold voltage 938b, Braking signal 930 is applied to braking motor 100 using one of the braking techniques described above to cause motor 100 to operate in braking mode phase 998. As shown in the fifth area 995 of the speed-time curve 986, the speed of the corresponding motor decreases linearly during start mode 990. [ In one example, the awake signal 926 and the motor control signal 928 transition to a logic low voltage level, for example, at or near 0V, and the braking signal 930 transitions to a logic high voltage level.
The braking signal 930 is also provided to the slip logic circuit 924, and in particular to the speed detection circuit 949 to determine when the speed of the motor has reached the threshold speed. When the speed of the motor reaches the threshold speed, the sleep logic circuit 924 provides the DLSS control circuit 62 with a sleep signal 932, for example, which has transitioned to a logic high voltage level, And operates in the sleep mode phase 988b. As shown in the sixth area 997 of the speed-time curve 986, the speed of the corresponding motor decreases linearly during sleep mode phase 988b until it becomes zero. The braking signal 930 transitions to a logic low voltage level.
Referring to Fig. 17, there is shown a motor control circuit 10 '' ', which is another embodiment of the motor control circuit 10. The motor control circuit 10 " 'includes a control logic circuit 920'. The control logic circuit 920 'is connected to the multifunctional port 916 via a connection line 922 and connected to the DLSS control circuit 62 via the connection lines 925, 926', 928 ', 930', 932 ' do. The control logic circuit 920 'receives the rotor commutation signal via a connection line 78. In this embodiment, negative voltage applied to the multifunctional port 916 and smaller than the negative threshold voltage 938b may cause the motor 100 to operate in the opposite direction. The braking signal is enabled when the voltage applied to the multifunction port 916 has a voltage level between a positive threshold voltage 938a and a negative threshold voltage 938b for a predetermined time.
In one example, a connection line 925 provides a motor direction signal, a connection line 926 'provides the awake signal, and a connection line 928' The connection line 930 'provides the braking signal, and the connection line 932' provides the sleep signal. In one example of a logic state, the motor direction signal 925 changes the direction of rotation of the motor 100. For example, when the motor direction signal 925 is in any one logic state, the motor 100 rotates in either direction, and when the motor direction signal 925 is in the opposite logic state, .
In one example of a logic state, the awake signal 926 'provided to the DLSS control circuit 62 turns on the motor 100 in the sleep mode. In one example, the awake signal 926 'provided to the DLSS control circuit 62 drives the motor at, for example, 100% duty cycle.
In one example of a logic state, the motor control signal 928 'provided to the DLSS control circuit 62 controls the speed of the motor and the braking signal 930' provided to the DLSS control circuit 62 is applied to the motor 100). In one example of a logic state, the sleep signal 932 'provided to the DLSS control circuit 62 causes the motor control circuit 10' '' to be in the sleep mode.
Referring to FIG. 18, in one example, the control logic circuit 920 'includes a window comparison circuit 937 in FIG. 13, an OR gate 943, an SR flip flop 945, a speed determination circuit 947, (948 '). The outputs of the AND gates 942a and 942b provided in the window comparison circuit 937 are applied to the OR gate 943 and the S-R flip-flop 945. The S-R flip-flop 945 is connected to the inverter 941d. The output of the inverter 941d is provided as a motor direction signal 925. The motor direction signal 925 changes the direction of rotation of the motor 100 when the control signal applied to the multi-function port 916 changes from a positive voltage to a negative voltage, and vice versa.
The OR gate 943 is connected to the latch circuit 944. The output of the latch circuit 944 is provided as an awake signal 926 '. The latch circuit 944 is reset by the sleep signal 932 'provided by the speed determination circuit 947. [ In one example, when one of the outputs of the AND gates 942a, 942b is in a logic high state, the output of the latch circuit 944 is coupled to a sleep signal 932 ' And is provided as an awake signal 926 'having a logic high state until it is reset by a reset signal.
The output of the AND gate 942c is applied to the inverter 941c. The output of the inverter 941c is provided as a motor control signal 928 '. The output of the inverter 941c is applied to a timer circuit 948 ', for example, a timer circuit (948 in FIG. 14). Timer circuit 948 'includes a counter 950' that counts the number of clock pulses received from reference clock 952 '. Timer circuit 948 'receives a motor control signal 928' serving as a reset signal for counter 950 '. Digital comparator 954 'compares the counted value with the timeout threshold stored in threshold timeout register 956'. The output of the digital comparator 954 'is provided as a braking signal 930'. For example, a logic high voltage level is provided if the number of clock pulses received in the timer circuit 948 'before reset is greater than or equal to the timeout threshold. In one example, the timer circuit 948 'is enabled while the control signal received at the multi-function port 916 has a voltage level between a positive threshold voltage 938a and a negative threshold voltage 938b, 930 'are provided to wait a predetermined time before the braking mode is started. For example, the predetermined time may be 1 ms.
The speed determination circuit 947 receives the rotor commutation signal 78 and the brake signal 930 '. The braking signal 930 'enables the speed determining circuit 947 to determine when the speed of the motor has decreased to a threshold voltage based on the rotor commutation signal 78. When the speed of the motor reaches the threshold voltage, the speed determination circuit 947 provides a sleep signal 932 'having, for example, a logic high voltage level.
In one example, in the sleep mode, multifunction port 916 receives a signal having a voltage level that is either higher than positive threshold voltage 938a or lower than negative threshold voltage 938b. Correspondingly, the output of the AND gate 942a becomes, for example, a logic high voltage level, and the outputs of the AND gates 942b and 942c become, for example, a logic low voltage level. Latch circuit 944 latches, for example, a logic high voltage level state and provides a logic high state awake signal 928 '. The output of the latch circuit 944 may remain latched until it is reset, for example, by a sleep signal 932 'having a logic high voltage level.
If the control signal received at the multifunction port 916 has a voltage level between a positive threshold voltage 938a and a negative threshold voltage 938b, for example, the motor control signal 928 ' While the braking signal 930 'has a logic low voltage level. The motor control signal 928 'is proportional to the control signal received at the multifunctional port 916. The control signal received at the multifunctional port 916 during a predetermined time corresponding to the threshold value stored in the threshold timeout register 956 'is the voltage between the positive threshold voltage 938a and the negative threshold voltage 938b Level, the brake signal 932 'is set to the logic high voltage state.
If the control signal received at the multifunctional port 916 has a voltage level lower than the negative threshold voltage 938b, i.e., transitions from a positive voltage to a negative voltage, the motor direction signal 925 is, for example, And has a logic high voltage state. The control circuit 926'may transmit a motor control direction signal 925 to the DLSS control circuit 62 so that the motor control direction signal 925 of the motor 100 The direction of rotation is reversed.
19 shows an example of controlling the rotation direction of the motor 100 by using the multifunctional port 916. Fig. In one example, the microprocessor (962 of FIG. 15) may provide control signal 982 'to multifunctional port 916 of motor control circuit 10' ''. In response to control signal 982 ', control logic circuit 920' includes an awake signal 926 ', a motor control signal 928'. Braking signal 930 'and a sleep signal 932'. The response corresponding to the speed of the motor in the speed-time curve 986 'is shown.
A 100% duty cycle control signal provided to the multifunction port 916 and greater than the positive threshold voltage 938a fully accelerates the motor 100. Once the PWM signal is applied to the multi-function port 916, the acceleration is reduced and the speed 986 'of the motor is stabilized. The speed of the motor 986 'is proportional to the duty cycle of the PWM signal applied to the multifunctional port 916. In this example, if the voltage level of the control signal 982 'is lower than the voltage level of the negative threshold voltage 938b, the motor direction signal 925 will change the motor control signal 84, Change the direction of rotation. Likewise, the PWM signal may be applied in the form of a negative voltage, in which case the duty cycle of the signal affects the speed of the motor in the opposite direction.
For example, if the speed of the motor 986 'is reduced below the threshold voltage as determined by the value stored in the threshold timeout register 956', the speed determination circuit 947 may determine that the DLSS control circuit 62 to provide a slip signal 932 'to cause the motor control circuit 10' '' to operate in the sleep mode phase 1002. For example, the sleep signal 932 'has a logic high voltage level. The speed of the corresponding motor during sleep mode phase 988a is zero, as shown in the first area 1022 of the speed-time curve 986 '.
Control logic circuit 920'disconnects the DLSS control circuit 62 to the awake signal 920. If the multifunctional port 916 receives a logic high voltage level, such as 4.5V, for example, which exceeds the positive threshold voltage 938a, And provides motor 926 'to allow motor 100 to operate in start-up phase 1004. In one example, the control signal 982 'provided at the multifunctional port 916 provides a signal to drive the motor at 100% duty cycle. The speed of the corresponding motor increases linearly during start mode 1004, as shown in the second region 1024 of the speed-time curve 986 '. In one example, the awake signal 928 'latches the state of a logic high voltage level, and the sleep signal 932' transitions to a logic low voltage level.
When the multifunctional port 916 receives a control signal 982 'comprising a PWM signal, the control logic circuit 920' provides the PWM signal to the DLSS control circuit 62 as a motor control signal 928 ' Thereby causing the motor 100 to operate in the PWM mode phase 1006 by changing the duty cycle of the motor 100 to a duty cycle corresponding to the duty cycle of the PWM signal, for example, at a duty cycle of 100%. During the PWM mode phase 1006, the speed of the corresponding motor is maintained at 100% until a speed corresponding to the PWM signal is reached, as shown in the third region 1026 of the speed-time curve 986 ' Linearly increases with reduced acceleration than in the case of a duty cycle and then maintains a constant speed as shown in the fourth region 1028 of the speed-time curve 986 '.
When the multifunctional port 916 receives a control signal 982 'having a logic low voltage level such as, for example, -4.5 V below the negative threshold voltage 938b, the control logic circuit 920' The motor control signal 925 is provided to the circuit 62 to cause the motor 100 to operate in the reverse mode 1008 by reversing the direction of rotation of the motor 100. [ In the first region 1010 of the reverse mode phase 1008, the direction of rotation of the motor is reversed for a 100% duty cycle corresponding to the control signal 982 '. The speed of the corresponding motor decreases linearly during the first region 1010 of the reverse mode phase 1008, as shown in the fifth region 1030 of the speed-time curve 986 '. In the second region 1012 of the reverse mode phase 1008, the direction of rotation of the motor is reversed with respect to the PWM duty cycle corresponding to the control signal 982 '. The speed of the corresponding motor during a second region 1012 of the reverse mode phase 1008 is less than that of the 100% duty cycle, as shown in the sixth region 1032 of the speed-time curve 986 ' Decreases linearly with reduced acceleration, and then maintains a constant speed as shown in the seventh region 1034 of the speed-time curve 986 '.
Fig. 20 shows that the control signal applied to the multifunctional port 916 of the motor control circuit 10 " 'in the microprocessor (962 of Fig. 15) has a positive threshold voltage 938a for longer than a predetermined time, And the voltage 938b. The predetermined time is the time to set the brake signal 932 'to a logic high state. Once the motor 100 begins to brake, the speed of the motor decreases. Once the speed of the motor decreases below the threshold speed, the speed determination circuit 947 sets the sleep signal 932 'to a logic high voltage and the DLSS control circuit 62 enters the sleep mode. For simplicity's sake, the reference numerals shown in FIG. 20 and corresponding explanations are the same as those shown in FIG. 19, except for the portions in which differences are described in detail below.
For example, when the control signal 982 'provided to the multifunctional port 916 has a voltage level between the threshold voltages 938a and 938b for a predetermined time, for example, a portion of the control signal 982' The timer circuit 924'provides a braking signal 930'to the DLSS control circuit 62 to change the direction of rotation of the motor in the opposite direction if it has a voltage level of 0V or within 0.5V during the time of the motor 1014 , Causing the motor 100 to operate in the braking mode phase 1016. The braking mode phase 1016 may be used to drive the motor 100 in the braking mode. In one example, the braking signal 930 'has a logic high voltage level. The velocity of the corresponding motor during the first zone 1018 of the braking mode phase 1016, as shown in a partial area 1036 of the velocity-time curve 986 ', is linear until the threshold speed is reached . Once the threshold speed is reached, the speed determination circuit 947, enabled by the braking signal 930 ', provides a sleep signal 932' to the DLSS control circuit 62 to enter the sleep mode. During the second region 1020 of the braking mode phase 1016, the speed of the corresponding motor, as shown in a partial region 1038 of the speed-time curve 986 ' Lt; RTI ID = 0.0 > 1018 < / RTI >
The components of the different embodiments described herein may be combined with one another to form other embodiments not specifically described above. Other embodiments not described herein are also included within the scope of the following claims.
