KR101335656B1 - Fabrication method of cigs thin films - Google Patents

Fabrication method of cigs thin films Download PDF

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KR101335656B1
KR101335656B1 KR1020110124190A KR20110124190A KR101335656B1 KR 101335656 B1 KR101335656 B1 KR 101335656B1 KR 1020110124190 A KR1020110124190 A KR 1020110124190A KR 20110124190 A KR20110124190 A KR 20110124190A KR 101335656 B1 KR101335656 B1 KR 101335656B1
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cis
thin film
indium
copper
depositing
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KR20130058271A (en
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고항주
김효진
한명수
신재철
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한국광기술원
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0749Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/541CuInSe2 material PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

본 발명은 CIS계 박막 제조방법에 관한 것으로서, 셀렌화 공정을 2회 실시하여 CIS계 결정질 박막을 형성할 때 공간(cavity)결함이 없는 CIS계(Cu-III-VI2계, 다시말해 Cu(InXGa1-X)(SYSe1-Y)2) 박막을 제조하기 위한 CIS계 박막 제조방법을 제공한다.
이러한 기술적 과제를 달성하기 위한 본 발명은, (a) 기판 위에 몰리브덴(Mo) 배면전극을 증착하는 단계, (b) 상기 배면전극 상에 인듐(In)을 증착함과 동시에 제1셀렌화 공정으로 인듐셀렌(InxSey)을 형성하거나 구리(Cu)를 증착함과 동시에 제1셀렌화 공정으로 구리셀렌(CuxSey)을 형성하는 단계 및 (c) 상기 인듐셀렌(InxSey) 위에 구리(Cu)를 증착하거나 상기 구리셀렌(CuxSey) 위에 인듐(In)을 증착함과 동시에 제2셀렌화 공정으로 CIS계 흡수층을 형성하는 단계를 포함하고, 상기 제1셀렌화 공정 또는 제2셀렌화 공정에서 기판의 온도는 250℃ 내지 550℃로 가열하는 것을 특징으로 한다.
The present invention relates to a method for manufacturing a CIS-based thin film, wherein the CIS-based (Cu-III-VI 2 -based, that is, Cu ( In X Ga 1-X ) (S Y Se 1-Y ) 2 ) Provides a CIS-based thin film manufacturing method for manufacturing a thin film.
The present invention for achieving the technical problem, (a) depositing a molybdenum (Mo) back electrode on the substrate, (b) depositing indium (In) on the back electrode at the same time as the first selenization process Forming indium selenium (In x Se y ) or depositing copper (Cu) and simultaneously forming copper selenium (Cu x Se y ) in a first selenization process; and (c) the indium selenium (In x Se y). ) Depositing copper (Cu) or depositing indium (In) on the copper selenium (Cu x Se y ) and simultaneously forming a CIS-based absorption layer by a second selenization process, wherein the first selenization The temperature of the substrate in the process or the second selenization process is characterized in that the heating to 250 ℃ to 550 ℃.

Description

CIS계 박막 제조방법{FABRICATION METHOD OF CIGS THIN FILMS} CIS-based thin film manufacturing method {FABRICATION METHOD OF CIGS THIN FILMS}

본 발명은 CIS계 박막 제조방법에 관한 것으로, 보다 상세하게는 몰리브텐(Molybdenum: Mo) 배면전극이 증착된 기판위에 "III족 금속막-Cu 막"을 증착(혹은 적층)하고 셀렌화(혹은 황화)처리하여 CIS계 결정질 박막을 형성할 때 공간(cavity)결함이 없는 CIS계(Cu-III-VI2계, 다시말해 Cu(InXGa1-X)(SYSe1-Y)2) 박막을 제조하는 방법을 제공한다. The present invention relates to a method for manufacturing a CIS-based thin film, and more particularly, to deposit (or laminate) a "Group III metal film-Cu film" on a substrate on which a molybdenum (Mo) back electrode is deposited and selenization ( Or CIS-based (Cu-III-VI 2 ), ie Cu (In X Ga 1-X ) (S Y Se 1-Y ), which has no cavity defects when forming CIS-based crystalline thin film. 2 ) It provides a method for producing a thin film.

칼코피라이트(chalcopyrite) 구조의 구리인듐셀렌(CuInSe2; CIS)계 화합물은 직접 천이형 반도체로서 높은 광흡수 계수(1ㅧ 105-1)와 밴드갭 조절의 용이성 및 열적 안정성 등으로 인해 고효율 박막태양전지용 흡수층과 적외선영역의 광검출기 재료로 주목받고 있다.The chalcopyrite structure of CuInSe 2 (CIS) -based compound is a direct transition semiconductor due to its high light absorption coefficient (1 ㅧ 10 5 cm -1 ), ease of band gap control, and thermal stability. It is attracting attention as an absorbing layer for high efficiency thin film solar cells and photodetector material in the infrared region.

특히, CIS계(Cu(InXGa1-X)(SYSe1-Y)2)에 속하는 Cu(InGa)Se2 (CIGS) 태양전지의 경우, 박막태양전지 중 세계 최고 효율인 20.1%를 달성한바 있으며, 이는 기존 다결정 웨이퍼형 실리콘 태양전지의 효율에 근접하는 수치이다. In particular, the Cu (InGa) Se 2 (CIGS) solar cell belonging to the CIS system (Cu (In X Ga 1-X ) (S Y Se 1-Y ) 2 ) is 20.1%, the world's highest efficiency among thin film solar cells. It has been achieved, which is close to the efficiency of the existing polycrystalline wafer-type silicon solar cell.

현재까지 연구되고 있는 CIS계 태양전지의 흡수층 제작방법은 동시증착(co-evaporation)법, 스퍼터링(sputtering)법, 전착(electro-deposition)법, 유기금속 기상성장법(metal organic chemical vapor deposition, MOCVD)법 등이 있고, 상용화가 추진 중인 제작방법은 동시증착법과 스퍼터링법이 주를 이룬다. 이중 스퍼터링법은 비교적 장치가 간단하고 손쉽게 금속 또는 절연체를 대면적으로 증착할 수 있어 제품을 생산하는 장치로 폭넓게 활용되고 있으며, 많은 박막태양전지 기업에서 Cu와 III족 금속을 Mo 배면전극위에 스퍼터링 증착 후 셀렌화(selenization)를 통해 CIS계 흡수층 박막을 제조하고 있다. The absorbing layer manufacturing method of CIS solar cell which is studied until now is co-evaporation method, sputtering method, electro-deposition method, metal organic chemical vapor deposition method, MOCVD ), Etc., and commercialization is being promoted mainly by simultaneous deposition and sputtering. The double sputtering method is widely used as a device for producing a product because it is relatively simple and can easily deposit a large area of metal or insulator. In many thin film solar cell companies, Cu and III metals are sputter deposited on Mo back electrodes. After the selenization (selenization) to produce a CIS-based absorption layer thin film.

통상적으로 CIGS 박막은 몰리브덴(molybdenum; Mo) 배면전극이 증착된 유리기판 위에 스퍼터링 장비를 이용하여 Cu-Ga-In 금속(금속과 셀레나이드 화합물을 포함) 한층한층 적층하고 셀레늄(Se) 소스를 주입하고 열을 가하여 식혀(열처리) 흡수층을 제조한다.In general, CIGS thin films are further laminated on Cu-Ga-In metals (including metals and selenide compounds) by sputtering on a glass substrate on which molybdenum (Mo) back electrodes are deposited, and a selenium (Se) source is injected. The mixture is then cooled to prepare a heat-absorbing layer.

Mo 배면전극 위에 증착된 금속을 Se 분위기에서 열처리하는 공정을 셀렌화(selenization)이라 하며, 일반적으로 대면적의 셀렌화 공정에는 Se 공급 유량 조절이 용이하고 반응성이 좋은 H2Se 기체가 사용되지만, H2Se 기체는 독성이 강할 뿐만 아니라 사용상 가스 누출을 막는 안전장치 등의 추가 장비가 필요하다.The process of heat-treating the metal deposited on the Mo back electrode in the Se atmosphere is called selenization. Generally, a large-area selenization process uses H 2 Se gas, which is easy to control the Se supply flow rate and has high reactivity. The H 2 Se gas is not only toxic but also requires additional equipment such as a safety device to prevent leakage of gas.

이러한, 셀렌화에 의한 광흡수층 제조장치 및 그 제조방법에 대해서는 대한민국등록특허 제 10-0922890호(발명의 명칭 : CIGS 광흡수층 제조방법 및 CIGS 광흡수층을 포함하는 태양전지)(이하 '종래기술')외에 다수 출원 및 등록되어있다. Such a device for manufacturing a light absorption layer by selenization and a method of manufacturing the same are described in Korean Patent No. 10-0922890 (Invention: CIGS Light Absorption Layer Manufacturing Method and Solar Cell Including CIGS Light Absorption Layer) (hereinafter 'Prior Art' In addition, there are a number of applications and registered.

상기 종래기술은 화합물 박막 태양전지의 광흡수층의 제조방법에 있어서, 기판의 상부에 구리갈륨(CuGa) 및 셀레나이드 화합물의 제 1혼합층과 구리인듐(CuIn) 및 셀레나이드 화합물의 제 2혼합층을 적층하여 전구체를 형성하는 단계; 및 상기 전구체를 열처리하는 단계; 를 포함하는 것을 특징으로 한다. 따라서, 혼합 금속 및 셀레나이드 화합물을 함께 사용하여 전구체를 형성함으로써, 셀렌화 공정에서 기판과의 접착 문제를 유발하지 않고 CIGS 광흡수층을 형성하는 효과가 있었다. According to the related art, in the method of manufacturing a light absorption layer of a compound thin film solar cell, a first mixed layer of copper gallium (CuGa) and selenide compound and a second mixed layer of copper indium (CuIn) and selenide compound are laminated on the substrate. To form a precursor; And heat treating the precursor; And a control unit. Therefore, by using the mixed metal and the selenide compound together to form a precursor, there was an effect of forming a CIGS light absorption layer without causing adhesion problems with the substrate in the selenization process.

다만, 셀렌화 공정 후 CIGS 광흡수층과 Mo 배면전극 사이에 공간(cavity)이 형성되어 CIGS 박막과 Mo배면전극의 접촉면적이 줄어드는 문제가 발생한다. However, after the selenization process, a cavity is formed between the CIGS light absorbing layer and the Mo back electrode, thereby reducing the contact area between the CIGS thin film and the Mo back electrode.

본 발명은 상기와 같은 문제점을 감안하여 안출된 것으로, 셀렌화 공정을 2회 실시하여 CIS계 결정질 박막을 형성할 때 공간(cavity)결함이 없는 CIS계(Cu-III-VI2계, 다시말해 Cu(InXGa1-X)(SYSe1-Y)2) 박막을 제조하기 위한 CIS계 박막 제조방법을 제공한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is a CIS system (Cu-III-VI 2 system, that is, no cavity defect) when forming a CIS-based crystalline thin film by performing the selenization process twice. Provided are a CIS-based thin film manufacturing method for manufacturing Cu (In X Ga 1-X ) (S Y Se 1-Y ) 2 ) thin film.

이러한 기술적 과제를 달성하기 위한 본 발명은, (a) 기판 위에 몰리브덴(Mo) 배면전극을 증착하는 단계, (b) (b) 상기 배면전극 상에 인듐(In)을 증착함과 동시에 제1셀렌화 공정으로 인듐셀렌(InxSey)을 형성하거나 구리(Cu)를 증착함과 동시에 제1셀렌화 공정으로 구리셀렌(CuxSey)을 형성하는 단계 및 (c) 상기 인듐셀렌(InxSey) 위에 구리(Cu)를 증착하거나 상기 구리셀렌(CuxSey) 위에 인듐(In)을 증착함과 동시에 제2셀렌화 공정으로 CIS계 흡수층을 형성하는 단계를 포함하고, 상기 제1셀렌화 공정 또는 제2셀렌화 공정에서 기판의 온도는 250℃ 내지 550℃로 가열하는 것을 특징으로 한다. The present invention for achieving the technical problem, (a) depositing a molybdenum (Mo) back electrode on the substrate, (b) (b) depositing indium (In) on the back electrode and at the same time the first selenium Forming indium selenium (In x Se y ) by a oxidization process or depositing copper (Cu) and simultaneously forming copper selenium (Cu x Se y ) by a first selenization process; and (c) the indium selenium (In x Se y ) or depositing copper (Cu) or indium (In) on the copper selenium (Cu x Se y ) and simultaneously forming a CIS-based absorption layer by a second selenization process, The temperature of the substrate in the one selenization process or the second selenization process is characterized in that the heating to 250 ℃ to 550 ℃.

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상기와 같은 본 발명에 따르면, Mo 배면전극과 CIS계 박막 사이에 공간결함이 줄어들어 CIS계 박막태양전지의 효율 향상 효과가 있다.According to the present invention as described above, the space defect between the Mo back electrode and the CIS-based thin film is reduced, thereby improving the efficiency of the CIS-based thin film solar cell.

도 1 은 본 발명의 일실시예에 따른 CIS계 박막 제조방법의 흐름도.
도 2 는 종래 기술에 따라 제조된 CIS계 박막의 측면도.
도 3 은 본 발명의 CIS계 박막 제조방법에 따라 제조된 CIS계 박막의 측면도.
1 is a flow chart of a CIS-based thin film manufacturing method according to an embodiment of the present invention.
Figure 2 is a side view of a CIS-based thin film prepared according to the prior art.
Figure 3 is a side view of the CIS-based thin film prepared according to the CIS-based thin film manufacturing method of the present invention.

본 발명의 구체적 특징 및 이점들은 첨부도면에 의거한 다음의 상세한 설명으로 더욱 명백해질 것이다. 이에 앞서 본 발명에 관련된 공지 기능 및 그 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는, 그 구체적인 설명을 생략하였음에 유의해야 할 것이다.Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. It is to be noted that the detailed description of known functions and constructions related to the present invention is omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

이하, 첨부된 도면을 참조하여 본 발명을 상세하게 설명한다.
Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

본 발명에 따른 CIS계 박막 제조방법에 관하여 도 1 내지 도 3 을 참조하여 설명하면 다음과 같다.
The CIS-based thin film manufacturing method according to the present invention will be described with reference to FIGS. 1 to 3 as follows.

도 1 은 본 발명의 일실시예에 따른 CIS계 박막 제조방법의 흐름도로서, 도시된 바와 같이 기판(10) 위에 배면전극(20)을 증착하는 단계(S100), 배면전극(20) 위에 인듐(In) 금속을 증착하는 단계(S200), 제1셀렌화 공정으로 InxSey를 형성하는 단계(S300), InxSey 위에 구리(Cu) 금속을 증착하는 단계(S400) 및 제2셀렌화 공정으로 CIS계 흡수층(30)을 형성하는 단계를 포함한다.
1 is a flow chart of a CIS-based thin film manufacturing method according to an embodiment of the present invention, as shown in the step of depositing the back electrode 20 on the substrate 10 (S100), the indium (20) on the back electrode 20 In) depositing the metal (S200), forming the In x Se y by the first selenization process (S300), depositing the copper (Cu) metal on the In x Se y (S400) and the second selenium Forming the CIS-based absorbing layer 30 by the oxidization process.

도 2 는 종래 기술에 따라 제조된 CIS계 박막의 측면도로서, 도시된 바와 같이 종래에는 유리 기판(10)에 배면전극(20)을 형성하고 그 상단에 CIS계 박막을 형성하였다. FIG. 2 is a side view of a CIS-based thin film manufactured according to the prior art, and as shown in the related art, a back electrode 20 is formed on a glass substrate 10 and a CIS-based thin film is formed on the top thereof.

종래에는 배면전극(20) 상에 구리와 인듐을 한꺼번에 증착시킨 후 단 한번의 셀렌화 공정을 거쳤기 때문에 배면전극(20)과 CIS계 흡수층(30) 사이에 빈 공간(40)이 형성되어 CIS계 박막의 효율을 저하시키는 문제점이 있었다. 따라서, 본 발명에서는 CIS계 박막 형성시 2번의 셀렌화 공정으로 빈공간(40)을 획기적으로 감소시켰다.
In the related art, since the copper and indium are deposited on the back electrode 20 at once, and then subjected to only one selenization process, an empty space 40 is formed between the back electrode 20 and the CIS-based absorbing layer 30 to form a CIS system. There was a problem of lowering the efficiency of the thin film. Therefore, in the present invention, the void space 40 is dramatically reduced by two selenization processes when forming the CIS-based thin film.

먼저, 상기 S100 단계에서는 기판(10) 위에 배면전극(20)을 증착한다. 이때, 상기 기판(10)은 유리기판, 세라믹 기판 또는 금속기판 등이 쓰일 수 있다. 또한 상기 배면전극(20)은 몰리브덴(Mo)이 쓰일 수 있으나 이에 한정되는 것은 아니다.First, in step S100, the back electrode 20 is deposited on the substrate 10. In this case, the substrate 10 may be a glass substrate, a ceramic substrate or a metal substrate. In addition, the rear electrode 20 may be molybdenum (Mo), but is not limited thereto.

또한 상기 S200 단계에서는 상기 배면전극(20) 위에 인듐(In) 또는 인듐-갈륨(In-Ga) 금속을 증착한다. 다만, 배면전극(20)에 증착하는 금속은 이에 한정되는 것은 아니다. In the step S200, an indium (In) or indium-gallium (In-Ga) metal is deposited on the rear electrode 20. However, the metal deposited on the back electrode 20 is not limited thereto.

이어서, 제1셀렌화 공정으로 배면전극(20)위에 형성된 인듐(In)계 금속과 셀레나이드 화합물이 결합하여 InxSey를 형성한다(S300). 상기 제1셀렌화 공정은 셀레나이드 화합물을 스퍼터링법, 동시증착법 등을 이용하여 배면전극(20)에 이미 형성된 인듐 금속과 결합시켜 InxSey이 되도록 할 수 있다.Subsequently, an indium (In) -based metal formed on the back electrode 20 and the selenide compound are combined to form In x Se y in the first selenization process (S300). In the first selenization process, the selenide compound may be combined with the indium metal already formed on the rear electrode 20 by using a sputtering method, a co-deposition method, and the like to make In x Se y .

또한, 인듐 금속을 배면전극(20)에 증착하는 것(S200)과 제1셀렌화 공정(S300)을 동시에 실행하여 배면전극(20) 위에 InxSey를 형성할 수도 있다.
Further, In x Se y may be formed on the back electrode 20 by simultaneously depositing the indium metal on the back electrode 20 (S200) and the first selenization process (S300).

뒤이어, 상기 형성된 InxSey에 구리(Cu) 금속을 증착하고(S400), 증착된 InxSey 및 구리(Cu)에 다시 제2셀렌화 공정으로 CIS계 흡수층(30)을 형성한다(S500).Subsequently, a copper (Cu) metal is deposited on the formed In x Se y (S400), and a CIS-based absorption layer 30 is formed on the deposited In x Se y and copper (Cu) by a second selenization process ( S500).

이때, 구리(Cu) 와 제2셀렌화 공정을 동시에 행할 수도 있고, 구리(Cu)를 먼저 증착시킨 후 제2셀렌화 공정을 진행할 수도 있다.At this time, the copper (Cu) and the second selenization process may be simultaneously performed, or the copper (Cu) may be deposited first, and then the second selenization process may be performed.

또한, 인듐을 먼저 증착하고 제1셀렌화 공정을 거쳐 구리를 증착하고 제2셀렌화 공정으로 CIS계 박막을 형성할 수도 있으나, 인듐과 구리의 순서를 바꿔 구리를 먼저 증착하고 제1셀렌화 공정을 거쳐 인듐을 증착하고 제2셀렌화 공정으로 CIS계 박막을 형성할 수도 있다.In addition, indium is deposited first, copper is deposited through a first selenization process, and a CIS-based thin film may be formed by a second selenization process, but copper is first deposited by changing the order of indium and copper, and a first selenization process is performed. Indium may be deposited through a second selenization process to form a CIS-based thin film.

그리고, 바람직하게는 상기 제1셀렌화 공정 또는 제2셀렌화 공정시 기판(10)의 온도를 250 ℃ 내지 550 ℃ 로 열처리한다.
Preferably, the temperature of the substrate 10 is heat treated at 250 ° C. to 550 ° C. during the first selenization process or the second selenization process.

따라서, 기존에 배면전극(20) 및 기판(10)위에 종래 Cu-In-Ga 금속 적층 후에 셀렌화를 통하여 제조한 CIS계 박막에 형성된 공간결함이 발생하던 것을, 본 발명에 따르면 2회 셀렌화 공정을 도입함으로 CIS계 박막과 배면전극(20)사이의 공간결함을 완전히 제거된 CIS계 박막을 제공함으로 효율을 높일 수 있다.
Therefore, according to the present invention, a space defect formed in a CIS-based thin film manufactured by selenization after conventional Cu-In-Ga metal deposition on the back electrode 20 and the substrate 10 has been generated twice. By introducing the process, it is possible to increase the efficiency by providing a CIS-based thin film completely eliminated the space defect between the CIS-based thin film and the back electrode 20.

이상으로 본 발명의 기술적 사상을 예시하기 위한 바람직한 실시예와 관련하여 설명하고 도시하였지만, 본 발명은 이와 같이 도시되고 설명된 그대로의 구성 및 작용에만 국한되는 것이 아니며, 기술적 사상의 범주를 일탈함이 없이 본 발명에 대해 다수의 변경 및 수정이 가능함을 당업자들은 잘 이해할 수 있을 것이다. 따라서, 그러한 모든 적절한 변경 및 수정과 균등물들도 본 발명의 범위에 속하는 것으로 간주되어야 할 것이다. While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It will be appreciated by those skilled in the art that numerous changes and modifications may be made without departing from the invention. Accordingly, all such appropriate modifications and changes, and equivalents thereof, should be regarded as within the scope of the present invention.

10 : 기판 20 : 배면전극
30 : CIS계 흡수층 40 : 빈 공간
10: substrate 20: back electrode
30: CIS absorber layer 40: empty space

Claims (4)

(a) 기판 위에 몰리브덴(Mo) 배면전극을 증착하는 단계,
(b) 상기 배면전극 상에 인듐(In)을 증착함과 동시에 제1셀렌화 공정으로 인듐셀렌(InxSey)을 형성하거나 구리(Cu)를 증착함과 동시에 제1셀렌화 공정으로 구리셀렌(CuxSey)을 형성하는 단계 및
(c) 상기 인듐셀렌(InxSey) 위에 구리(Cu)를 증착하거나 상기 구리셀렌(CuxSey) 위에 인듐(In)을 증착함과 동시에 제2셀렌화 공정으로 CIS계 흡수층을 형성하는 단계를 포함하고,
상기 제1셀렌화 공정 또는 제2셀렌화 공정에서 기판의 온도는 250℃ 내지 550℃로 가열하는 것을 특징으로 하는 CIS계 박막 제조방법.
(A) depositing a molybdenum (Mo) back electrode on the substrate,
(b) forming indium selenium (In x Se y ) in a first selenization process or depositing copper (Cu) at the same time as depositing indium (In) on the rear electrode and copper in a first selenization process Forming selenium (Cu x Se y ), and
(c) depositing copper (Cu) on the indium selenium (In x Se y ) or indium (In) on the copper selenium (Cu x Se y ) and simultaneously forming a CIS-based absorbing layer by a second selenization process Including the steps of:
CIS-based thin film manufacturing method characterized in that the temperature of the substrate in the first selenization process or the second selenization process is heated to 250 ℃ to 550 ℃.
삭제delete 삭제delete 삭제delete
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009507369A (en) 2005-09-06 2009-02-19 エルジー・ケム・リミテッド Manufacturing method of solar cell absorption layer
KR20090100692A (en) * 2008-03-20 2009-09-24 엘지마이크론 주식회사 The method of manufacturing cigs thin film by using three-step heat treatment and cigs solar cell
KR20110000690A (en) * 2008-04-04 2011-01-04 이 아이 듀폰 디 네모아 앤드 캄파니 Solar cell modules comprising high melt flow poly(vinyl butyral) encapsulants
KR20110060139A (en) * 2009-11-30 2011-06-08 삼성전자주식회사 Method of manufacturing solar cell

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009507369A (en) 2005-09-06 2009-02-19 エルジー・ケム・リミテッド Manufacturing method of solar cell absorption layer
KR20090100692A (en) * 2008-03-20 2009-09-24 엘지마이크론 주식회사 The method of manufacturing cigs thin film by using three-step heat treatment and cigs solar cell
KR20110000690A (en) * 2008-04-04 2011-01-04 이 아이 듀폰 디 네모아 앤드 캄파니 Solar cell modules comprising high melt flow poly(vinyl butyral) encapsulants
KR20110060139A (en) * 2009-11-30 2011-06-08 삼성전자주식회사 Method of manufacturing solar cell

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