KR101307163B1 - The printed circuit board manufacturing method - Google Patents

The printed circuit board manufacturing method Download PDF

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KR101307163B1
KR101307163B1 KR1020120136933A KR20120136933A KR101307163B1 KR 101307163 B1 KR101307163 B1 KR 101307163B1 KR 1020120136933 A KR1020120136933 A KR 1020120136933A KR 20120136933 A KR20120136933 A KR 20120136933A KR 101307163 B1 KR101307163 B1 KR 101307163B1
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South Korea
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circuit
inner layer
outer layer
ink
peelable ink
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KR1020120136933A
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Korean (ko)
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이대원
서정식
이성기
조승훈
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주식회사 에스아이 플렉스
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Priority to CN201310616262.6A priority patent/CN103857192B/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

PURPOSE: A protection method for an inner circuit of a printed circuit board is provided to enable shielding with one ink application and prevent liquid from permeating into a circuit in a liquid process in which cohesive power is increased and coated afterward by processing thermal compression bonding after the printing of peelable ink. CONSTITUTION: A protection method for an inner circuit of a printed circuit board comprises a step (S10) of forming a circuit on an inner layer forming the circuit on the upper part of a copper substrate of a raw material state; a step (S20) of laminating a coverlay on the upper part of the inner layer; a step (S30) of laminating an outer layer on the upper surface by using a hot press; a step (S40) of printing a peelable ink in order to prevent the circuit of the inner layer exposed to the outside; a step (S50) of performing copper plating between the laminated inner layer and the outer layer to comprise electrical connection; a step (S60) of forming an outer layer circuit forming the circuit on the laminated outer layer; and a step (S70) of removing the peelable ink printed on the upper part of the inner layer circuit. [Reference numerals] (AA) Start; (BB) End; (S10) Step of forming a circuit on an inner layer; (S20) Step of preparing a coverlay; (S30) Step of laminating an outer layer; (S40) Step of printing a peelable ink; (S50) Step of performing copper plating; (S60) Step of forming an outer layer circuit; (S70) Step of removing the peelable ink

Description

인쇄회로기판의 내층회로 보호공법{The printed circuit board manufacturing method}The inner circuit protection method of a printed circuit board {The printed circuit board manufacturing method}

본 발명은 인쇄회로기판의 내층회로 보호공법에 관한 것으로서, 더욱 상세하게는 내층의 상부에 위치하는 외층을 핫 프레스(hot press)로 적층한 다음에 보호하고자 하는 내층회로의 상부에 필라블 잉크 (Peelable Ink)을 인쇄함으로서, 상기 필라블 잉크 (Peelable Ink)의 인쇄 횟수를 단축할 수 있고 상기 외층 핫 프레스(hot press)에 의해 잉크가 잔류되는 것을 방지할 수 있도록 하는 인쇄회로기판의 내층회로 보호공법에 관한 것이다. The present invention relates to a method for protecting an inner layer circuit of a printed circuit board. More particularly, the present invention relates to a peelable ink formed on an upper portion of an inner layer circuit to be protected by laminating an outer layer located on the upper layer by a hot press. By printing Peelable Ink, it is possible to shorten the number of printing of the Peelable Ink and to protect the inner circuit of the printed circuit board to prevent the ink remaining by the outer layer hot press. It is about public law.

현재 F.PCB를 제조하는 업체에서 R/F TYPE (RIGID/FLEXIBLE TYPE)의 MLB(MULTI - LAYER BOARD) 를 생산함에 있어 외층(RIGID층) 제조 공정 진행 시, 내층(FLEXIBLE층)에서 이미 형성되어진 회로를 보호하기 위해 2종의 Peelable ink를 이용하여 내층 회로보호를 하고 있다. Currently, F.PCB makers have already formed the inner layer (FLEXIBLE layer) during the process of manufacturing the outer layer (RIGID layer) in producing MLB (MULTI-LAYER BOARD) of R / F TYPE (RIGID / FLEXIBLE TYPE). In order to protect the circuit, two kinds of Peelable Ink are used to protect the inner layer.

상기 필라블 잉크 (Peelable Ink)는 인쇄 공정에서 사용하는 자재의 일종으로 인쇄-건조 후, 수 작업의 벗겨냄 방식으로 제거가 가능한 잉크로서, 상기 필라블 잉크 (Peelable Ink)는 제거가 가능하므로 주로 보호 목적의 차폐용으로 사용이 되어지고, 잉크 종류 및 특성에 따라 밀착성 / Peel성의 차이가 있어, 차폐력 부족에 따른 회로 손상 및 잉크 과 경화에 따른 잉크 잔류 등의 불량 발생에 유의차가 크게 나타나는 경향이 있다.
The peelable ink is a kind of material used in a printing process, and after printing-drying, the peelable ink is an ink which can be removed by manual peeling. The peelable ink is mainly removable because the peelable ink can be removed. It is used for shielding for protection purpose, and there is a difference in adhesion / peel property according to ink type and characteristics, and there is a tendency to show significant difference in defect occurrence such as circuit damage due to lack of shielding power and ink residue due to ink and curing. There is this.

도 1 내지 도 2는 종래의 인쇄회로기판의 내층회로 보호공법에 대해 개략적으로 도시한 공정도이고, 도 3은 종래의 인쇄회로기판의 내층회로 보호공법에 의한 문제점을 개략적으로 도시한 도면이다.
1 to 2 is a process diagram schematically showing the inner layer circuit protection method of a conventional printed circuit board, Figure 3 is a view schematically showing a problem by the inner layer circuit protection method of a conventional printed circuit board.

따라서, 상기 필라블 잉크 (Peelable Ink)를 이용하여 내층에 형성된 회로를 보호하기 위한 공법은 도 1에 도시된 바와 같이, 내층회로 형성단계(S01), 커버레이 적층단계(S02), 필라블 잉크 (Peelable Ink)인쇄 단계(S03), 외층 적층 단계(S04), 동도금 단계(S05), 외층 회로형성단계(S06), 필라블 잉크 (Peelable Ink)제거단계(S07)를 포함한다. Therefore, the method for protecting the circuit formed in the inner layer using the peelable ink is shown in Figure 1, the inner layer circuit forming step (S01), coverlay lamination step (S02), pillable ink (Peelable Ink) printing step (S03), outer layer stacking step (S04), copper plating step (S05), outer layer circuit forming step (S06), peelable ink (Peelable Ink) removing step (S07).

이때, 상기 필라블 잉크 (Peelable Ink)인쇄 단계(S03)에서 도포되는 필라블 잉크 (Peelable Ink)는 두가지의 타입을 이용하여 나뉘어 두번 인쇄되는데, 내층 회로에 맞닿는 1차 잉크는 EPOXY 수지 계열의 액상 잉크류로써, 특성으로는 PEEL성 및 제거성이 좋은 것을 사용하며, 상기 1차 잉크의 상부에 도포되는 2차 잉크는 1차 잉크와 마찬가지로 EPOXY 계열의 액상 INK류이나, 다만 1차 잉크와 달리 밀착력이 강하여 액 공정 및 열,압력 공정등으로부터 내층 회로 보호를 위하여 1차 잉크 외부 모두를 가리도록 넓게 도포하는 형상으로 인쇄를 하게 된다.At this time, the peelable ink applied in the peelable ink printing step (S03) is divided and printed twice using two types, and the primary ink contacting the inner layer circuit is an EPOXY resin-based liquid phase. As the inks, PEEL property and good removal property are used as properties, and the secondary ink applied on the upper part of the primary ink is an EPOXY-based liquid INK like the primary ink, but unlike the primary ink. It has strong adhesion and prints in a shape that is widely applied to cover the outside of the primary ink to protect the inner circuit from the liquid process, heat, and pressure process.

상기와 같이 필라블 잉크 (Peelable Ink)가 두번으로 나뉘어 인쇄되므로 공정시간이 늘어나게 되고 그로 인해 생산성 저하 및 자재비가 상승되는 요인이 된다. As described above, the peelable ink is divided into two prints, thereby increasing the processing time, thereby causing a decrease in productivity and a material cost.

또한 필라블 잉크 (Peelable Ink)를 인쇄한 후에 Hot press를 이용해 외층을 적층하고 동도금 및 외층 회로 형성 등에 사용되는 액 처리 공정에 따라 회로내에 액 침투 발생이 잦아 회로가 손상이 되거나 필라블 잉크 (Peelable Ink)가 잔류되는 문제가 발생되는 단점이 있었다. In addition, after printing the Peelable Ink, the liquid layer is used to laminate the outer layer using hot press and the liquid processing process used for copper plating and the formation of the outer layer circuit often causes the circuit to be damaged or the Peelable Ink (Peelable Ink). There was a disadvantage that the problem of ink remaining occurs.

대한민국 특허청 등록특허공보 제10-0632557호Korea Patent Office Registered Patent Publication No. 10-0632557

본 발명은 상기와 같은 종래의 문제점을 해소하기 위한 것으로서, 본 발명의 목적은 먼저 Hot press를 이용해 외층을 적층한 후에 필라블 잉크 (Peelable Ink)를 인쇄함으로서 1번의 잉크 도포만으로도 차폐가 가능하도록 하며, 필라블 잉크 (Peelable Ink) 인쇄 후에 열압착이 진행되므로 필라블 잉크 (Peelable Ink)의 밀착력이 증가되어 추후 도포되는 액공정에서 액이 회로내에 침투하는 것을 방지할 수 있도록 하는 인쇄회로기판의 내층회로 보호공법을 제공하는 것이다. The present invention is to solve the conventional problems as described above, the object of the present invention by first laminating the outer layer using a hot press and then printing the peelable ink (Peelable Ink) so that it is possible to shield by only one application of ink. Since the thermal compression process is performed after printing the Peelable Ink, the adhesion of the Peelable Ink is increased to prevent the liquid from penetrating into the circuit in the later applied liquid process. It is to provide a circuit protection method.

본 발명은 앞서 본 목적을 달성하기 위하여 다음과 같은 구성을 가진 실시예에 의해 구현된다.
In order to achieve the above object, the present invention is implemented by the following embodiments.

본 발명은 동(Cu)으로 형성된 내층의 표면을 에칭 제거하여 내층회로를 형성하는 내층 회로를 형성하는 단계(S10)와, 상기 내층 회로 형성단계(S10)를 거친 내층의 상부에 내층의 일부분이 외부로 노출될 수 있도록 가공된 커버레이를 적층하는 단계(S20)와, 상기 커버레이 적층 단계(S20)에서 적층된 커버레이의 상면에 핫프레스(hot press)를 이용하여 내층의 일부분이 외부로 노출될 수 있도록 가공된 외층을 적층하는 단계(S30)와, 상기 외층 적층 단계(S30)를 거친 기판에 있어서 내층의 상부에 외층 및 커버레이가 적층되지 않아 외부로 노출된 내층 회로를 보호하기 위하여 인쇄되는 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)와, 동(Cu)으로 형성된 내층과 외층 사이에 전기적인 커넥션이 이루어질 수 있도록 내층 회로와 외층 회로가 중첩되는 구간에 가공된 홀(hole)의 내벽에 동도금을 하는 동도금 단계(S50)와, 상기 외층 적층 단계(S30)에서 적층된 동(Cu)으로 형성된 외층에 회로를 형성하는 외층 회로 형성단계(S60)와, 상기 외층 회로 형성단계(S60)를 완료한 기판에 있어서 상기 내층회로의 상부에 인쇄된 필라블 잉크 (Peelable Ink)를 제거하는 필라블 잉크 제거단계(S70)를 포함하는 것을 특징으로 한다.
The present invention provides a step of forming an inner layer circuit for forming an inner layer circuit by etching and removing the surface of the inner layer formed of copper (Cu), and a portion of the inner layer formed on the inner layer through the inner layer circuit forming step (S10). Stacking the coverlay processed to be exposed to the outside (S20), and a portion of the inner layer by using a hot press (hot press) on the upper surface of the coverlay laminated in the coverlay stacking step (S20) to the outside In order to protect the inner layer circuit exposed to the outside because the outer layer and the coverlay are not stacked on the upper layer of the inner layer in the step (S30) and the outer layer lamination step (S30) substrate to be exposed so as to be exposed Peelable Ink to be Printed Holes processed in a section where the inner layer circuit and the outer layer circuit overlap so that an electrical connection can be made between the printing step S40 and the inner and outer layers formed of copper. Copper plating step (S50) for copper plating on the inner wall, outer layer circuit forming step (S60) for forming a circuit in the outer layer formed of copper (Cu) laminated in the outer layer stacking step (S30), and the outer layer circuit forming step (S60) And a peelable ink removing step (S70) of removing peelable ink printed on the upper portion of the inner layer circuit.

상기에서 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)는 내층 회로와 맞닿게 인쇄되며, 밀착력이 높은 잉크를 한번만 도포하여 차폐가 될 수 있도록 하는 것을 특징으로 한다.
Peelable ink printing step (S40) is printed in contact with the inner layer circuit, it is characterized in that it can be shielded by applying only one ink having a high adhesion.

상기에서 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)는 필라블 잉크 (Peelable Ink)가 인쇄된 후에 열압착을 하여 밀착력을 증가시켜 회로내에 액이 침투되는 것을 방지할 수 있도록 하는 것을 특징으로 한다. Peelable ink printing step (S40) is characterized in that to prevent the liquid from penetrating into the circuit by increasing the adhesion by thermo-compression after the peelable ink (Peelable Ink) is printed. .

상술한 바와 같이 본 발명에 따른 인쇄회로기판의 내층회로 보호공법은 필라블 잉크 (Peelable Ink)를 인쇄하기 전에 Hot press를 이용해 외층을 적층함으로서 1번의 잉크 도포만으로도 차폐가 가능하여 생산성이 향상되며 자재비를 절감할 수 있는 효과를 도모할 수 있다. As described above, the inner circuit protection method of the printed circuit board according to the present invention can be shielded by only one ink application by improving the productivity by materially stacking the outer layer using hot press before printing the peelable ink. The effect can be reduced.

또한, 필라블 잉크 (Peelable Ink) 인쇄 후에 열압착이 진행되므로 필라블 잉크 (Peelable Ink)의 밀착력이 증가되어 추후 도포되는 액공정에서 액이 회로내에 침투하는 것을 방지할 수 있도록 하여 불량 감소 및 잔류된 잉크 재처리 LOSS 감소 등의 효과를 지닌다. In addition, since the thermocompression is performed after printing the Peelable Ink, the adhesion of the Peelable Ink is increased to prevent the liquid from penetrating into the circuit in the later applied liquid process. Reduced ink reprocessing loss.

도 1 내지 도 2는 종래의 인쇄회로기판의 내층회로 보호공법에 대해 개략적으로 도시한 공정도이고,
도 3은 종래의 인쇄회로기판의 내층회로 보호공법에 의한 문제점을 개략적으로 도시한 도면이고,
도 4는 본 발명의 일 실시예에 따른 인쇄회로기판의 내층회로 보호공법에 대해 개략적으로 도시한 공정도이다. 1 to 2 is a process diagram schematically showing the inner layer circuit protection method of a conventional printed circuit board,
3 is a view schematically showing a problem caused by an inner layer circuit protection method of a conventional printed circuit board,
4 is a process diagram schematically illustrating an inner circuit protection method of a printed circuit board according to an exemplary embodiment of the present invention.

이하에서는 본 발명에 따른 인쇄회로기판의 내층회로 보호공법을 첨부된 도면을 참조하여 상세히 설명한다. 도면들 중 동일한 구성요소들은 가능한 어느 곳에서든지 동일한 부호들로 나타내고 있음에 유의해야 한다. 또한 본 발명의 요지를 불필요하게 흐릴 수 있는 공지 기능 및 구성에 대한 상세한 설명은 생략한다.
Hereinafter, a method of protecting an inner layer circuit of a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. It is to be noted that like elements in the drawings are represented by the same reference numerals as possible. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

도 4는 본 발명의 일 실시예에 따른 인쇄회로기판의 내층회로 보호공법에 대해 개략적으로 도시한 공정도이다.
4 is a process diagram schematically illustrating an inner circuit protection method of a printed circuit board according to an exemplary embodiment of the present invention.

본 발명은 도 4에 도시된 바와 같이, 동(Cu)으로 형성된 내층의 표면을 에칭 제거하여 내층회로를 형성하는 내층 회로를 형성하는 단계(S10)와, 상기 내층 회로 형성단계(S10)를 거친 내층의 상부에 내층의 일부분이 외부로 노출될 수 있도록 가공된 커버레이를 적층하는 단계(S20)와, 상기 커버레이 적층 단계(S20)에서 적층된 커버레이의 상면에 핫프레스(hot press)를 이용하여 내층의 일부분이 외부로 노출될 수 있도록 가공된 외층을 적층하는 단계(S30)와, 상기 외층 적층 단계(S30)를 거친 기판에 있어서 내층의 상부에 외층 및 커버레이가 적층되지 않아 외부로 노출된 내층 회로를 보호하기 위하여 인쇄되는 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)와, 동(Cu)으로 형성된 내층과 외층 사이에 전기적인 커넥션이 이루어질 수 있도록 내층 회로와 외층 회로가 중첩되는 구간에 가공된 홀(hole)의 내벽에 동도금을 하는 동도금 단계(S50)와, 상기 외층 적층 단계(S30)에서 적층된 동(Cu)으로 형성된 외층에 회로를 형성하는 외층 회로 형성단계(S60)와, 상기 외층 회로 형성단계(S60)를 완료한 기판에 있어서 상기 내층회로의 상부에 인쇄된 필라블 잉크 (Peelable Ink)를 제거하는 필라블 잉크 제거단계(S70)를 포함한다.
As shown in FIG. 4, the present invention has a step (S10) of forming an inner layer circuit forming an inner layer circuit by etching and removing the surface of the inner layer formed of copper (Cu) and the inner layer circuit forming step (S10). Stacking the processed coverlay to expose a portion of the inner layer to the upper part of the inner layer (S20), and applying a hot press (hot press) to an upper surface of the coverlay laminated in the coverlay stacking step (S20). Stacking the processed outer layer so that a portion of the inner layer may be exposed to the outside (S30), and the outer layer and the coverlay are not stacked on the upper part of the inner layer in the substrate having passed the outer layer stacking step (S30). The inner layer circuit and the outer layer circuit are superimposed so that an electrical connection can be made between the peelable ink printing step S40 and the inner and outer layers formed of copper to protect the exposed inner circuit. The copper plating step (S50) for copper plating on the inner wall of the hole (hole) processed in the section and the outer layer circuit forming step (S60) for forming a circuit in the outer layer formed of copper (Cu) laminated in the outer layer stacking step (S30) And a peelable ink removing step S70 for removing the peelable ink printed on the inner layer circuit on the substrate on which the outer layer circuit forming step S60 is completed.

상기 내층 회로 형성 단계(S10)는 동(Cu)으로 형성된 내층의 상부에 감광성 FILM인 DRY FILM을 코팅한 후, 노광 공정 진행으로 원하는 회로 형상대로 노광 빛을 조사시켜주고, 현상 공정을 진행하여 노광 빛 조사를 받지않은 DRY FILM을 제거한다. 제거된 DRY FILM이 있던 영역에 있던 영역에 에칭을 진행하여 Cu를 부식시켜 제거하게 되고, 박리공정을 추가 진행하여 남아있는 dry film을 제거함으로서 원자재 상태였던 동 기판에 회로를 형성하는 단계이다.
In the inner layer circuit forming step (S10), after the DRY FILM, which is a photosensitive film, is coated on the inner layer formed of copper (Cu), the exposure process proceeds to irradiate the exposure light in a desired circuit shape, and the development process proceeds to the exposure. Remove DRY FILM that is not irradiated with light. It is a step of forming a circuit on the copper substrate, which is a raw material state, by etching to the area in the area where the removed DRY FILM was removed by etching Cu and removing the remaining dry film by further performing the peeling process.

상기 커버레이 적층 단계(S20)는 상기 내층 회로 형성 단계(S10)를 거친 내층의 상부에 내층의 일부분이 노출될 수 있도록 가공된 커버레이를 적층하는 단계로서, 상기 커버레이는 내층에 형성된 회로를 보호하기 위한 film류 자재로 PI+BOND의 층 구조로 되어있으며 흔히 SOLDER RESIST 역할을 한다. 상기 커버레이는 기판의 표면에 열압착으로 하여 내층에 형성된 회로층을 보호하며 커버레이를 적층할 때 적층 압력에 의해 밀리거나 틀어지는 것을 방지하기 위해 임시로 붙이는 가접공정을 거친 후에 적층한다.
The coverlay stacking step (S20) is a step of stacking a coverlay processed to expose a portion of the inner layer on the inner layer through the inner layer circuit forming step (S10), wherein the coverlay is a circuit formed on the inner layer As a film material for protection, it has a layer structure of PI + BOND and often plays the role of solid resin. The coverlay is thermally compressed to the surface of the substrate to protect the circuit layer formed in the inner layer, and laminated after the temporary bonding process to temporarily prevent the coverlay from being pushed or twisted by the stacking pressure.

상기 외층 적층 단계(S30)는 상기 커버레이 적층 단계(S20)를 거쳐 커버레이가 적층된 상부에 동(Cu)으로 형성된 외층을 적층하는 단계로서, 외층은 내층의 일부분이 외부로 노출될 수 있도록 미리 가공된 것을 준비하며, 외층을 적층하는 방법은 적층과 열압착 공정으로 나뉘어지며, 적층 및 열압착은 모두 열판 사이사이에 기판을 적재하여 열과 압력을 가함으로서 상기 내층에 외층을 적층할 수 있도록 하는 것으로 적층의 경우 고압으로 장시간 동안 압착이 필요한 사항이고, 열압착의 경우 저압으로 짧은 시간동한 압착을 하는 공정이다. The outer layer stacking step (S30) is a step of stacking the outer layer formed of copper (Cu) on the coverlay laminated step through the coverlay stacking step (S20), the outer layer so that a portion of the inner layer can be exposed to the outside Preparing the pre-processed, laminating the outer layer is divided into lamination and thermocompression process, both lamination and thermocompression so that the outer layer can be laminated on the inner layer by applying heat and pressure by loading the substrate between the hot plate In the case of lamination, it is a matter of pressing for a long time at high pressure, and in the case of thermocompression, pressing is performed for a short time at low pressure.

다만, 두 공정 모두 원자재간의 접합이 목적이으로 사용되나, 적층은 PCB 제품의 층간 접착을 목적으로 하고, 열압착은 PCB 제품과 부자재(보강대, TAPE 등)간 접착 목적으로 한다.
However, in both processes, the purpose of bonding between raw materials is used, but lamination is for the purpose of adhesion between layers of PCB products, and thermocompression is for the purpose of adhesion between PCB products and subsidiary materials (reinforcement bars, TAPE, etc.).

상기 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)는 내층의 일부분이 외부로 노출될 수 있도록 가공된 커버레이와 외층을 내층의 상부에 적층함으로서, 커버레이 및 외층이 적층되지 못하고 노출된 내층 회로에 필라블 잉크를 인쇄하여 회로를 보호할 수 있도록 하는 단계로서, 상기 필라블 잉크 (Peelable Ink)는 EPOXY 수지 계열의 액상 INK류로써 PEEL성 및 제거성이 좋아 내층 회로에 맞닿게 형성되며 밀착력이 강한 잉크를 사용하여 액 공정 및 열,압력 공정 등으로부터 내층 회로 보호할 수 있도록 한다. The peelable ink printing step (S40) may include a coverlay and an outer layer, which are processed to expose a portion of the inner layer to the outside, on the upper portion of the inner layer, so that the coverlay and the outer layer may not be stacked, and the inner layer circuit may be exposed. The peelable ink is a liquid INK of EPOXY resin series, which is formed in contact with the inner layer circuit with good PEEL property and removability. Strong ink is used to protect inner layer circuit from liquid process, heat and pressure process.

상기 필라블 잉크 (Peelable Ink)의 인쇄방법은 SILK SCREEN 인쇄 공법을 적용하며 액상의 잉크를 인쇄 형상에 맞게 기공이 형성되어진 기판 위에 도포하여 스퀴지가 이동하며 압력을 가함으로서 기판(PCB)에 인쇄된다. 인쇄된 후에는 건조 공정을 진행하여 경화를 시켜주어야 한다.
The peelable ink is printed on a substrate by applying a SILK SCREEN printing method and applying liquid ink on a substrate having pores formed in accordance with a printing shape by moving a squeegee and applying pressure. . After printing, the drying process should be performed to cure.

상기 동도금 단계(S50)는 상기 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)까지 거친 기판에 가공된 홀(HOLE)의 내벽에 동도금을 하는 단계로서, 동(Cu)으로 형성된 내층과 외층으로 구성되는 인쇄회로기판에서 층간의 전기적 커넥션(CONNECTION)을 위하여 내층 회로와 외층 회로가 중첩되는 구간에 드릴로 홀(HOLE)을 천공한 다음, 홀(HOLE)의 내벽에 도금(Cu)하여 층간 통전이 이루어질 수 있도록 하는 공정이다.The copper plating step (S50) is a step of copper plating the inner wall of the hole (HOLE) processed in the rough substrate until the peelable ink printing step (S40), consisting of an inner layer and an outer layer formed of copper (Cu) In the printed circuit board, the hole (HOLE) is drilled in the section where the inner layer circuit and the outer layer circuit overlap for the electrical connection between the layers, and then plated (Cu) on the inner wall of the hole (Hu) to conduct the interlayer It is a process to make it possible.

액 처리를 통하여 무전해 동도금에서 전해 동도금의 순서로 진행된다.
The solution is processed in the order of electroless copper plating from electroless copper plating.

상기 외층 회로 형성단계(S60)는 동(Cu)으로 형성된 외층에 회로를 형성하는 단계로서 이는 상기 내층 회로 형성 단계(S10)에서 진행된 공정방법과 동일하게 드라이필름(Dry film) 코팅 -> 노광 -> 현상 -> 에칭 -> 박리의 단계를 통해 외층에 회로를 형성한다.
The outer circuit forming step (S60) is a step of forming a circuit in the outer layer formed of copper (Cu), which is the same as the process proceeded in the inner circuit forming step (S10) Dry film coating-> exposure- A circuit is formed in the outer layer through the steps of development-etching-peeling.

상기 필라블 잉크 제거단계(S70)는 상기 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)에서 인쇄된 필라블 잉크 (Peelable Ink)를 제거하는 단계로서 외층 회로형성 공정이 끝나면, 차폐 보호목적으로 적용된 PEELABLE INK를 제거해야 하는데 집게 등을 이용하여 수작업으로 뜯어내는 방식으로 제거를 한다.
The peelable ink removing step (S70) is a step of removing the peelable ink printed in the peelable ink printing step (S40). When the outer layer circuit forming process is completed, the peelable ink is applied for shielding protection purposes. PEELABLE INK needs to be removed. Remove it by hand torn off with forceps.

이상에서, 출원인은 본 발명의 다양한 실시예들을 설명하였지만, 이와 같은 실시예들은 본 발명의 기술적 사상을 구현하는 일 실시예일 뿐이며, 본 발명의 기술적 사상을 구현하는 한 어떠한 변경예 또는 수정예도 본 발명의 범위에 속하는 것으로 해석되어야 한다.While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Should be interpreted as falling within the scope of.

S10 : 내층 회로 형성 단계
S20 : 커버레이 적층 단계
S30 : 외층 적층 단계
S40 : 필라블 잉크 (Peelable Ink) 인쇄 단계
S50 : 동도금단계
S60 : 외층 회로 형성단계
S70 : 필라블 잉크 제거단계S10: inner layer circuit forming step
S20: Coverlay Lamination Step
S30: outer layer stacking step
S40: Peelable Ink Printing Steps
S50: Copper Plating Step
S60: outer layer circuit forming step
S70: peelable ink removal step

Claims (3)

동(Cu)으로 형성된 내층의 표면을 에칭 제거하여 내층회로를 형성하는 내층 회로를 형성하는 단계(S10)와, 상기 내층 회로 형성단계(S10)를 거친 내층의 상부에 내층의 일부분이 외부로 노출될 수 있도록 가공된 커버레이를 적층하는 단계(S20)와, 상기 커버레이 적층 단계(S20)에서 적층된 커버레이의 상면에 핫프레스(hot press)를 이용하여 내층의 일부분이 외부로 노출될 수 있도록 가공된 외층을 적층하는 단계(S30)와, 상기 외층 적층 단계(S30)를 거친 기판에 있어서 내층의 상부에 외층 및 커버레이가 적층되지 않아 외부로 노출된 내층 회로를 보호하기 위하여 인쇄되는 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)와, 동(Cu)으로 형성된 내층과 외층 사이에 전기적인 커넥션이 이루어질 수 있도록 내층 회로와 외층 회로가 중첩되는 구간에 가공된 홀(hole)의 내벽에 동도금을 하는 동도금 단계(S50)와, 상기 외층 적층 단계(S30)에서 적층된 동(Cu)으로 형성된 외층에 회로를 형성하는 외층 회로 형성단계(S60)와, 상기 외층 회로 형성단계(S60)를 완료한 기판에 있어서 상기 내층회로의 상부에 인쇄된 필라블 잉크 (Peelable Ink)를 제거하는 필라블 잉크 제거단계(S70)를 포함하는 것을 특징으로 하는 인쇄회로기판의 내층회로 보호공법Etching the surface of the inner layer formed of copper (Cu) to form an inner layer circuit to form an inner layer circuit (S10), and a portion of the inner layer is exposed to the outside on the upper portion of the inner layer that has passed through the inner layer circuit forming step (S10). A step of stacking the coverlay processed to be possible (S20), and by using a hot press (hot press) on the upper surface of the coverlay laminated in the coverlay stacking step (S20) may be a portion of the inner layer exposed to the outside. In order to protect the inner circuits exposed to the outside because the outer layer and the coverlay are not stacked on the upper layer of the inner layer in the substrate having undergone the step S30 and the outer layer stacking step S30, Peelable Ink In the printing step (S40) and the inner wall of the hole processed in the section where the inner layer circuit and the outer layer circuit overlap so that an electrical connection can be made between the inner layer and the outer layer formed of copper (Cu).Copper plating step (S50) for plating, outer layer circuit forming step (S60) for forming a circuit in the outer layer formed of copper (Cu) laminated in the outer layer stacking step (S30), and the outer layer circuit forming step (S60) A method of protecting an inner layer circuit of a printed circuit board, the method comprising: a peelable ink removing step (S70) of removing the peelable ink printed on an upper portion of the inner layer circuit on the completed substrate; 제1항에 있어서,
상기 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)는 내층 회로와 맞닿게 인쇄되며, 필라블 잉크를 한번만 도포하여 차폐가 될 수 있도록 하는 것을 특징으로 하는 인쇄회로기판의 내층회로 보호공법The method of claim 1,
The peelable ink printing step (S40) is printed in contact with the inner layer circuit, the inner layer circuit protection method of the printed circuit board, characterized in that the shielding by applying the pillable ink only once. 제1항에 있어서,
상기 필라블 잉크 (Peelable Ink) 인쇄 단계(S40)는 필라블 잉크 (Peelable Ink)가 인쇄된 후에 열압착을 하여 밀착력을 증가시켜 회로내에 액이 침투되는 것을 방지할 수 있도록 하는 것을 특징으로 하는 인쇄회로기판의 내층회로 보호공법

The method of claim 1,
The peelable ink printing step (S40) may be performed by thermal compression after the peelable ink is printed to increase adhesion to prevent the liquid from penetrating into the circuit. Inner Circuit Protection Method of Circuit Board

KR1020120136933A 2012-11-29 2012-11-29 The printed circuit board manufacturing method KR101307163B1 (en)

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KR1020120136933A KR101307163B1 (en) 2012-11-29 2012-11-29 The printed circuit board manufacturing method
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