KR101289666B1 - Bulk-type nanostructure transistor and manufacturing method therefor - Google Patents

Bulk-type nanostructure transistor and manufacturing method therefor Download PDF

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Publication number
KR101289666B1
KR101289666B1 KR1020120088191A KR20120088191A KR101289666B1 KR 101289666 B1 KR101289666 B1 KR 101289666B1 KR 1020120088191 A KR1020120088191 A KR 1020120088191A KR 20120088191 A KR20120088191 A KR 20120088191A KR 101289666 B1 KR101289666 B1 KR 101289666B1
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South Korea
Prior art keywords
gate
bulk
bulk substrate
channel
nanostructure
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KR1020120088191A
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Korean (ko)
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최양규
설명록
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한국과학기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around

Abstract

The bulk nanostructure transistor of the present invention includes a bulk substrate; A source and a drain formed on the bulk substrate and spaced apart from each other with a channel having a nanostructure spaced apart from the bulk substrate therebetween; A first buried insulating layer disposed between the bulk substrate and the source and a second buried insulating layer positioned between the bulk substrate and the drain; And a gate located between the source and the drain on the bulk substrate.

Description

Bulk-type Nanostructure Transistor and Manufacturing Method Thereof {Bulk-Type NanoStructure Transistor and Manufacturing Method therefor}

The present invention relates to a bulk nanostructure transistor and a method of manufacturing the same.

The development of semiconductor transistors is focused on the size reduction of devices. As the device's size decreases, more transistors are included in the same area, while the device's operating speed is faster, enabling the chip to achieve both high performance and high capacity. However, when the size of the device is reduced to less than 1 micrometer based on the gate length, short-channel effects cause a problem in the operation of the device.

While research on techniques to reduce these short channel effects could reduce the size of the device to 30 nanometers based on the current gate length, scaling down to less than 30 nanometers is not possible due to physical and / or technical limitations. It has been recognized that the planar MOS transistor structure is difficult to achieve. In order to overcome these limitations, nanostructured transistors, which are nanostructured channels and structures that surround these channels in three-dimensional form, have been intensively studied.

The easiest way to fabricate a channel in nanostructure form is to use a silicon on insulator (SOI) wafer. Using such an SOI wafer, it is easy to fabricate a nanostructured channel because a buried insulating layer is inserted before the process. However, SOI wafers have the disadvantage of significantly higher manufacturing costs compared to bulk type wafers. Therefore, when using an SOI wafer, there is a limit in being used in an actual industry because it does not receive a good evaluation in terms of price / performance, which is one of the important measures for evaluating the performance of a transistor chip.

There is a need for a technique for fabricating high performance nanostructure transistors at low cost.

Korean Laid-Open Publication No. 10-2006-0028833 (2006.04.04)

SUMMARY OF THE INVENTION The present invention has been made to meet the needs of the prior art, and provides a technique capable of manufacturing high performance nanostructure transistors at low cost by effectively blocking leakage current through a body while using a bulk substrate.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

The bulk nanostructure transistor according to the present invention includes a bulk substrate; A source and a drain formed on the bulk substrate and spaced apart from each other with a channel having a nanostructure spaced apart from the bulk substrate therebetween; A first buried insulating layer disposed between the bulk substrate and the source and a second buried insulating layer positioned between the bulk substrate and the drain; And a gate located between the source and the drain on the bulk substrate.

A method of manufacturing a bulk nanostructure transistor according to the present invention includes forming a first buried insulating layer and a second buried insulating layer spaced apart from each other on a bulk substrate; Epitaxially growing a semiconductor on the bulk substrate and then planarizing the epitaxially grown semiconductor; The semiconductor is etched to form a nanostructured channel spaced apart from the bulk substrate and a source and a drain spaced apart from each other with the nanostructured channel interposed therebetween on the first buried insulating layer and the second buried insulating layer, respectively. Doing; And forming a gate between the source and the drain on the bulk substrate.

According to the present invention, it is possible to provide a high performance nanostructure transistor at low cost. According to the present invention, it is possible to effectively block leakage current through a body while using a bulk substrate in a nanostructure transistor. According to the present invention, the bulk leakage current can be effectively blocked by inserting a partially buried insulating layer under the source and drain regions in the nanostructure transistor.

1 illustrates a bulk nanostructure transistor in accordance with an embodiment of the present invention.
2A and 2I illustrate a process of manufacturing a bulk nanostructure transistor according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity of explanation and the same reference numerals are used for the same elements and the same elements are denoted by the same quote symbols as possible even if they are displayed on different drawings Should be. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

1 illustrates a bulk nanostructure transistor in accordance with an embodiment of the present invention. The bulk nanostructure transistor according to the exemplary embodiment of the present invention includes a source 111, a drain 11, and a first buried insulating layer 130a formed to be spaced apart from each other with a bulk substrate 100 and a channel 110 having a nanostructure therebetween. ) And a second buried insulating layer 130b and gates 113a and 113b.

The bulk substrate 100 according to the embodiment of the present invention may be a silicon bulk substrate, but is not limited thereto. For example, the bulk substrate 100 according to the embodiment of the present invention may include at least one of Si, Ge, SiC, SiGe, GaAs, AlGaAs and InGaAs. In addition, the bulk substrate 100 according to the embodiment of the present invention may be a p-type or n-type substrate depending on the type of the dopant.

In the bulk nanostructure transistor according to the embodiment of the present invention, the source 111 and the drain formed on the bulk substrate 100 and spaced apart from each other with the channel 110 of the nanostructure spaced apart from the bulk substrate 100 interposed therebetween. (112). In an embodiment of the present invention, the source 111 and the drain 112 may include a material having high conductivity. For example, the source 111 and the drain 112 may be made of a metal or a semiconductor material having a high doping concentration. For example, the source 111 and the drain 112 may be formed by doping an n-type impurity (Atomic Periodic Group 5 element) or a p-type impurity (Atomic Periodic Table Group 3 element) to the semiconductor material, respectively.

A nanostructured channel 110 is defined between the source 111 and the drain 112. In this case, the channel 110 of the nanostructure may have any one of a form of a nano-dot, a nano-wire, or a nano-belt. In addition, the nanostructure channel 110 according to the embodiment of the present invention is spaced apart from the bulk substrate 100. In addition, the nanostructure channel 110 according to an embodiment of the present invention may include at least one or more of silicon (Si), germanium (Ge), and carbon (C). The channel 110 may form a current path through which a drain current flows later depending on whether a voltage is applied to the gate 113.

In FIG. 1, the gate 113 is positioned between the source 111 and the drain 112 on the bulk substrate 100 and has a shape separated from each other. In an embodiment of the invention, the gate 113 may comprise a material having a high conductivity. For example, the gate 113 may be made of a metal or a semiconductor material having a high doping concentration.

In the bulk nanostructure transistor according to the embodiment of the present invention, the gate insulating layers 120a and 120b for insulating the gate 113 from the channel 110, the source 111, the drain 112, and the bulk substrate 100 are provided. It may further include. The gate insulating layers 120a and 120b may include a material having low conductivity. For example, the gate insulating layers 120a and 120b may include an insulating material such as silicon oxide or a high insulating material (High-K).

As shown in FIG. 1, in the bulk nanostructure transistor according to the exemplary embodiment of the present invention, the first buried insulating layer 130a and the drain 112 and the bulk substrate 100 are disposed between the source 111 and the bulk substrate 100. ) Further includes a second buried insulating layer (130b). The first buried insulating layer 130a and the second buried insulating layer 130b may include a material having low conductivity. For example, the first and second buried insulating layers 130a and 130b may include an insulating material such as silicon oxide or a high insulating material.

As such, by including the first and second buried insulating layers 130a and 130b, the leakage current path from the bulk nanostructure transistor according to the embodiment of the present invention to the body may be blocked.

2A and 2I illustrate a process of manufacturing a bulk nanostructure transistor according to an embodiment of the present invention. Hereinafter, a method of manufacturing a bulk-type nanostructure transistor according to an embodiment of the present invention will be described sequentially with reference to FIGS. 2A to 2I.

As shown in FIG. 2A, a bulk substrate 100 is prepared. In the embodiment of the present invention, the bulk substrate 100 may be a general bulk silicon substrate.

A material forming the buried insulating layers 130a and 130b is deposited on the bulk substrate 100. The first buried insulating layer 130a spaced apart from each other by patterning the buried insulating layer 130 so that the buried insulating layer 130 may be located only in the lower regions of the source 111 and the drain 112. And a second buried insulating layer 130b. It is shown in Figure 2b that the buried insulating layer 130 is separated into two parts by patterning. In this case, the first buried insulating layer 130a and the second buried insulating layer 130b may be formed of the same material to simplify the manufacturing process.

As shown in FIG. 2C, the semiconductor 101 is epitaxially grown on the bulk substrate 100. In an embodiment of the present invention, a silicon substrate is used as the bulk substrate 100 and silicon may be epitaxially grown using silicon as the semiconductor 101. The epitaxially grown semiconductor 101 may form regions of the channel 110, the source 111, and the drain 112. Since the semiconductor 101 grows isotropically around a portion without the first and second buried insulating layers 130a and 130b on the bulk substrate 100, the first buried insulating layer and the second buried insulating layer 130a and 130b may be buried between the bulk substrate 100 and the semiconductor 101.

As shown in Fig. 2D, the epitaxially grown semiconductor 101 is planarized. The thickness of the source 111 and the drain 112 to be formed later may be determined according to the degree of planarization. The process of planarizing the semiconductor 101 may be performed through, for example, a chemical mechanical polishing (CMP) process.

As shown in FIG. 2E, the nanostructure morphology to be used later as the channel 110 by etching the semiconductor 101 may be configured. Through etching of the semiconductor 101, the nanostructured channel 110 is spaced apart from the bulk substrate 100 and the semiconductor 111 to form the source 111 and the drain 112 later with the nanostructured channel 110 interposed therebetween. A portion may remain only on the first buried insulating layer 130a and the second buried insulating layer 130b.

In the embodiment of the present invention is shown assuming that the Bosch process (Bosch Process) is used to form the channel 110 of the nanostructure. Through this Bosch process, both ends of the nanostructures remain fixed and floating in the air, and the bottom of the nanostructures can be deeply etched and exposed to the air. At this time, the bottom of the nanostructure is etched deeper than the buried insulating layer (130a and 130b) is shown. Through the Bosch process, not only the semiconductor 101 but also a portion of the bulk substrate 100 may be etched.

As shown in FIG. 2F, a gate insulating layer 120 is formed so that the gate 113 to be formed later is insulated from the channel 110, the source 111, the drain 112, and the bulk substrate 100. Can be. For example, the gate insulating layer 120 may be formed by depositing, planarizing, and wet etching silicon oxide (SiO 2 ) through chemical vapor deposition (CVD). In this case, after the wet etching, the silicon oxide may be thermally grown to form the gate insulating layer 120 around the nanostructure. In the embodiment of the present invention, the gate insulating layers 120a and 120b are portions etched through the Bosch process, and may be formed on the bulk substrate 100, on the inner side of the semiconductor 101, and on the side and bottom surfaces of the nanostructure. have. In FIG. 2F, the gate insulating layers 120a and 120b are not formed at the upper surface of the nanostructure, so that the gate insulating layers 120a and 120b are separated, but this is only an example, and the gate insulating layers 120a and 120b are illustrated. Silver may also be formed on the top surface of the nanostructures.

As shown in FIG. 2G, a material to be used as the gate 113 may be deposited and then patterned. In this case, the gate 113 may be formed on the bulk substrate 100 between the source 111 and the drain 112. As the material for forming the gate 113, a material having high conductivity, for example, a metal or a semiconductor material which may have high conductivity according to a doping condition, may be used as a material for forming the gate 113. In an embodiment of the present invention, poly-silicon is used as the gate 113.

As shown in FIG. 2H, doping is performed on the source 111, the drain 112, and the gate 113. In this embodiment, the electrode has a high conductivity through this doping process. After the doping process is completed, the bulk nanostructure transistor as shown in FIG. 2H operates as a tri-gate nanostructure transistor and can be used immediately as a device. In this case, the gate 113 has a shape surrounding the three surfaces including both sides and the top surface of the channel 110 of the nanostructure. In this case, the gate insulating layer 120 needs to be formed on the upper surface of the channel 110 of the nanostructure. Since the gate 113 surrounds three surfaces of the channel 110 having the nanostructure, the three-gate gate nanostructure transistor can control the gate 113 with high efficiency.

As shown in FIG. 2I, the gate 113 may be separated into the first gate 113a and the second gate 113b by performing planarization on the gate 113 shown in FIG. 2H. Since the first gate 113a and the second gate 113b are spaced apart from each other, the bulk type nanostructure transistor illustrated in FIG. 2I may be used as an independent double-gate nanostructure transistor. In this case, the first gate 113a and the second gate 113b may be independent so that different voltages may be applied.

As described above, the bulk-type nanostructure transistor according to the embodiment of the present invention includes a first buried insulating layer 130a and a second buried insulating layer 130b while using the bulk substrate 100 to form a body. The leakage current can be effectively blocked. Thereby, it is possible to manufacture a high performance three-dimensional transistor.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. will be. Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, It is intended that all changes and modifications derived from the equivalent concept be included within the scope of the present invention.

100: bulk substrate
101: epitaxially grown semiconductor
110: nanostructured channel
111: source
112: drain
113: gate
120: gate insulating layer
130; Investment insulation layer

Claims (13)

Bulk substrates;
A source and a drain formed on the bulk substrate and spaced apart from each other with a channel having a nanostructure spaced apart from the bulk substrate therebetween;
A first buried insulating layer positioned between the bulk substrate and the source and a second buried insulating layer positioned between the bulk substrate and the drain; And
A gate located between said source and said drain on said bulk substrate,
Bulk nanostructure transistors. The method of claim 1,
The gate has a shape surrounding three surfaces including both sides and an upper surface of the channel of the nanostructure,
And a gate insulating layer for insulating the gate from the channel, the source, the drain, and the bulk substrate. The method of claim 1,
The gate includes a first gate and a second gate formed to be spaced apart from each other with the channel therebetween,
And a gate insulating layer for insulating the gate from the channel, the source, the drain, and the bulk substrate. The method according to claim 2 or 3,
The bulk substrate is a bulk nanostructure transistor comprising at least one of Si, Ge, SiC, SiGe, GaAs, AlGaAs and InGaAs. The method according to claim 2 or 3,
The nanostructured channel is bulk nanostructure transistor, characterized in that it comprises at least one or more of silicon (Si), germanium (Ge) and carbon (C). The method according to claim 2 or 3,
The nanostructured channel is a bulk nanostructure transistor, characterized in that it has a form of any one of nano dots, nanowires, or nano belts. Forming a first buried insulating layer and a second buried insulating layer spaced apart from each other on the bulk substrate;
Epitaxially growing a semiconductor on the bulk substrate and then planarizing the epitaxially grown semiconductor;
The semiconductor is etched to form a nanostructured channel spaced apart from the bulk substrate and a source and a drain spaced apart from each other with the nanostructured channel interposed therebetween on the first buried insulating layer and the second buried insulating layer, respectively. Making; And
Forming a gate between the source and the drain on the bulk substrate,
Bulk nanostructure transistor manufacturing method. The method of claim 7, wherein
The gate is formed to surround three surfaces including both sides and an upper surface of the channel of the nanostructure through the forming of the gate,
After etching the semiconductor and before forming the gate,
And forming a gate insulating layer to insulate said gate from said channel, said source, said drain, and said bulk substrate. 9. The method according to claim 7 or 8,
And doping the source, the drain, and the gate. 9. The method according to claim 7 or 8,
And planarizing the gate such that the gate is separated into a first gate and a second gate spaced apart from each other with the channel interposed therebetween. 9. The method according to claim 7 or 8,
The bulk substrate is a bulk nanostructure transistor manufacturing method characterized in that it is formed to include at least one or more of Si, Ge, SiC, SiGe, GaAs, AlGaAs and InGaAs. 9. The method according to claim 7 or 8,
The semiconductor is a bulk nanostructure transistor manufacturing method characterized in that it is formed to include at least one or more of silicon (Si), germanium (Ge) and carbon (C). 9. The method according to claim 7 or 8,
The nanostructured channel is a bulk nanostructure transistor manufacturing method characterized in that it is formed to have a form of any one of nano dots, nanowires, or nano belts.
KR1020120088191A 2012-08-13 2012-08-13 Bulk-type nanostructure transistor and manufacturing method therefor KR101289666B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679965B1 (en) 2015-12-07 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor device having a gate all around structure and a method for fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060001109A1 (en) 2004-06-30 2006-01-05 Shaheen Mohamad A High mobility tri-gate devices and methods of fabrication
KR20080051030A (en) * 2006-12-04 2008-06-10 한국전자통신연구원 Schottky barrier nanowire field effect transistor and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060001109A1 (en) 2004-06-30 2006-01-05 Shaheen Mohamad A High mobility tri-gate devices and methods of fabrication
KR20080051030A (en) * 2006-12-04 2008-06-10 한국전자통신연구원 Schottky barrier nanowire field effect transistor and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679965B1 (en) 2015-12-07 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor device having a gate all around structure and a method for fabricating the same

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