KR101174912B1 - Method of manufacturing substrate having bump - Google Patents
Method of manufacturing substrate having bump Download PDFInfo
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- KR101174912B1 KR101174912B1 KR1020050072638A KR20050072638A KR101174912B1 KR 101174912 B1 KR101174912 B1 KR 101174912B1 KR 1020050072638 A KR1020050072638 A KR 1020050072638A KR 20050072638 A KR20050072638 A KR 20050072638A KR 101174912 B1 KR101174912 B1 KR 101174912B1
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- South Korea
- Prior art keywords
- bump
- conductive
- conductive foil
- substrate
- bumps
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Wire Bonding (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
An object of this invention is to provide the manufacturing method of the board | substrate which has bump which can form a high bump and can control the height of bump easily. To this end, first, the first conductive foil 12 is adhered to the upper surface, the substrate having the second conductive foil 13 adhered to the lower surface thereof, and the through hole 14 is formed. Next, the first conductive foil 12 and the second conductive foil 13 are electrically connected through the through holes 14, and the through holes 14 are filled with the filler 16. Then, the bumps 18 are formed by etching the first conductive foils 12, and the conductive paths extending from the bumps 18 are formed by etching the first conductive foils 12 except the portion where the bumps 18 are formed. Form. Therefore, by controlling the thickness of the first conductive foil 12, the height of the bumps 18 can be controlled.
Substrate having bumps, conductive foil, filler, conductive path, fine metal wire
Description
(A)-(c) is sectional drawing for demonstrating the manufacturing method of the board | substrate which has a bump of this invention.
(A)-(c) is sectional drawing for demonstrating the manufacturing method of the board | substrate which has a bump of this invention.
(A) and (b) are sectional drawing for demonstrating the manufacturing method of the board | substrate with a bump of this invention.
4 is a cross-sectional view illustrating a method for manufacturing a substrate having a bump of the present invention.
5 (a) and 5 (b) are a top view and a back view for explaining the method for manufacturing a circuit board of the present invention.
6 (a) to 6 (c) are cross-sectional views illustrating a method for manufacturing a substrate having a bump of the present invention.
7 (a) to 7 (c) are diagrams for explaining a conventional method for manufacturing a circuit board.
Description of the Related Art
10: substrate with bumps
11: substrate
12: 1st conductive foil
13: 2nd conductive foil
14: through hole
15: conductive film
16: filling material
18: bump
22: first conductive pattern
23: second conductive pattern
24: conductive film
25: insulation film
26: challenge road
28: electrical components
29: thin metal wire
[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-40764
This invention relates to the manufacturing method of the board | substrate which has a bump which can form a high bump and can select a bump height easily.
With reference to FIG. 7, the formation method of the conventional solder bump is demonstrated.
First, referring to FIG. 7A, the circuit board 100 is formed by forming the first conductive pattern 102 on the upper surface of the substrate 101 and the second conductive pattern 103 on the lower surface. .
Referring to FIG. 7B, the semiconductor device 104 is placed on the first conductive pattern 102, and the first conductive pattern 102 and the semiconductor device 104 are formed using the fine metal wires 105. Connect electrically. Then, the upper surface of the substrate 101 is sealed with the sealing resin 106 so that the semiconductor element 104 and the fine metal wire 105 are covered.
Referring to FIG. 7C, the resist 107 is patterned such that a desired portion of the second conductive pattern 103 is exposed on the surface of the second conductive pattern 103. Then, the solder bumps 108 are formed by placing and reflowing the solder balls on the second conductive patterns 103 exposed from the resist 107 (see Patent Document 1).
However, the above-described method of forming the solder bumps 108 has the following problems.
Since the bumps 108 are formed of solder, the height of the bumps 108 cannot be selected. Moreover, it was difficult for the height of bumps to be 100 micrometers or more by soldering.
In addition, since the solder bumps 108 are formed by placing and reflowing the solder balls, it is difficult to form bump heights with high accuracy.
Moreover, since bumps were formed by solder, it could not be mounted simultaneously with other circuit components using solder cream on the mounting board | substrate.
This invention is made | formed in view of such a problem, and the main objective of this invention is providing the manufacturing method of the board | substrate which has bump which has sufficient bump height.
The manufacturing method of the board | substrate with a bump of this invention is a process of preparing the board | substrate with which the 1st conductive foil of thickness corresponding to the height of the bump was adhere | attached on the upper surface, and the 2nd conductive foil corresponding to the thickness of wiring was adhered to the lower surface, Forming a through hole penetrating the substrate, the first conductive foil, and the second conductive foil; forming through hole plating in the through hole, and electrically connecting the first conductive foil and the second conductive foil to the through hole. A step of forming a bump by half-etching the step of filling the filler, the first conductive foil except for the region where the through hole is formed, and a conductive path extending from the bump by etching the first conductive foil except the region where the bump is formed. And forming a wiring by etching the second conductive foil.
Moreover, the manufacturing method of the board | substrate with a bump of this invention forms the through-hole plating which coat | covers the surface of a 1st conductive foil and a 2nd conductive foil, and also covers the inner wall of a through hole, The 1st conductive foil and a 2nd The electrically conductive foil is electrically connected.
In the method for manufacturing a substrate having a bump of the present invention, the through hole plating and the first conductive foil are made of the same metal, and the bumps are formed by simultaneously etching the conductive film and the first conductive foil. do.
Moreover, the manufacturing method of the board | substrate with a bump of this invention is characterized by selecting the height of a bump by selecting the thickness of a 1st electrically conductive foil.
Moreover, the manufacturing method of the board | substrate with a bump of this invention is characterized by electrically connecting between bumps provided by the electrically conductive path.
Moreover, the manufacturing method of the board | substrate with a bump of this invention is characterized in that a filler is a electrically-conductive material.
Moreover, the manufacturing method of the board | substrate with a bump of this invention is characterized by the filler being resin.
<Example>
With reference to FIGS. 1-3, the manufacturing method of the circuit board of this form is demonstrated.
First, referring to FIG. 1A, a substrate 11 having a first conductive foil 12 adhered to an upper surface and a second conductive foil 13 adhered to a lower surface thereof is prepared.
As the substrate 11, a glass epoxy substrate or a glass polyimide substrate is preferably used. However, in some cases, a fluorine substrate, a glass PPO substrate, a ceramic substrate, or the like may be employed. Moreover, a flexible sheet, a film, etc. may be sufficient. In this embodiment, the glass epoxy substrate about 200 micrometers in thickness was employ | adopted.
As the 1st conductive foil 12 and the 2nd conductive foil 13, what is necessary is just a metal which can be etched. In this embodiment, a metal foil made of copper is employed. And as the 1st conductive foil 12, copper foil with a film thickness of about 175 micrometers was employ | adopted. This film thickness is determined so as to correspond to the height of the bump described later. A conductive foil having a film thickness of up to about 230 μm can be employed. Therefore, the height of the bump can be selected according to the thickness of the conductive foil, so that the accuracy with respect to the height of the bump can be improved. In addition, it is possible to easily form a bump having a height in accordance with the standard, for example, it is possible to form the bump higher than the conventional solder bumps.
As the second conductive foil 13, a conductive foil having a thickness corresponding to the height of the wiring is used. In this aspect, the film thickness of the 2nd conductive foil 13 was about 18 micrometers. The thickness of the wiring can be arbitrarily determined according to the current capacity of the circuit element to be mounted.
Referring to FIG. 1B, a through hole 14 penetrating through the substrate 11, the first conductive foil 12, and the second conductive foil 13 is formed. Here, the through hole 14 with a diameter of about 0.25 mm was formed. The through hole 14 can be formed using an NC machine tool.
Referring to FIG. 1C, the conductive film 15 is a through hole plating covering the surfaces of the first conductive foil 12 and the second conductive foil 13 and covering the inner wall of the through hole 14. ). The first conductive foil 12 and the second conductive foil 13 are electrically connected by the conductive film 15. In this embodiment, the conductive film 15 is copper plating having a thickness of about 20 μm, and was formed by an electroless plating method. However, the electroconductive plating method or the electroless plating method and the electrolytic plating method may be combined to form the conductive film 15.
Referring to FIG. 2A, the through hole 14 is filled by the filler 16. The filler 16 can be filled by screen printing. When the conductive material such as copper paste is used as the filler 16, the electrical connection between the first conductive pattern 12 and the second conductive pattern 13 can be ensured, and the current capacity can be ensured. And the like. However, resin or the like may be used for the filler 16. When the resin is used, the through hole can be easily filled as compared with the copper paste or the like. By the filler 16, the surface of the bump mentioned later can be made evenly flat, and connection reliability with a mounting surface can be improved.
Referring to FIG. 2B, the first conductive foil 12 and the conductive film 15 are partially removed by half etching to form a bump 18. Therefore, a part of 1st conductive foil 12 has a fixed thickness, and remains. In this embodiment, since the first conductive foil 12 and the conductive film 15 are made of copper, the bumps 18 can be formed by one etching. In addition, the bump 18 includes a region in which the through hole 14 is formed. In the case of forming by wet etching, ferric chloride or cupric chloride is mainly used as the etchant. Then, in a state where a desired portion of the conductive foil is exposed from the resist, it is dipped into this etchant or showered with this etchant. In this embodiment, the etchant is showered and the etching depth is controlled according to the time.
In this way, by forming the bumps 18 by etching, the positional accuracy of the bumps can be improved to provide a substrate having bumps with high connection reliability with the mounting substrate side. It is also possible to arbitrarily determine the shape of the bumps.
The bump 18 is formed of the laminate of the first conductive foil 12 and the conductive film 15 and the filler 16. Although the height of the bump 18 of this form is about 215 micrometers including the film thickness of the electrically conductive film mentioned later, it is possible to form about 250 micrometers at maximum. And the 1st conductive foil 12 thinly formed by half etching becomes a film thickness of about 35 micrometers-45 micrometers, for example. As a matter of course, the first conductive foil 12 may be left to have a film thickness of 35 µm or less or 45 µm or more.
Referring to FIG. 2C, a laminate layer is formed on the upper surface of the bump 18, and the first conductive foil 12 is etched to expose the upper surface of the substrate 11. This etching can be stopped at the stage where the substrate 11 is exposed, so that the etching can be easily controlled. The first conductive foils 12 are electrically separated from each other, and the first conductive patterns 22 having the bumps 18 are formed. Here, the bump 18 includes a region in which the through hole 14 is formed. In addition, the first conductive pattern 22 includes a conductive path formed integrally with the bump 18. This electrically conductive path is electrically connected between the bumps 18 spaced apart from each other. Therefore, the wiring on the mounting substrate side can be extended between the bumps.
Referring to FIG. 3A, a resist is patterned on the surface of the second conductive foil 13, and the second conductive pattern 23 is formed by etching through the resist. The second conductive pattern 23 is a wiring formed on a surface on which a circuit element or the like is mounted, and also includes lands and bonding pads.
Thus, since bumps are formed first and wirings and conductive paths are formed in accordance with the positions of the formed bumps, a substrate having bumps with improved positional accuracy of the bumps can be provided.
Referring to FIG. 3B, the upper surface of the first conductive pattern 22 including the upper surface of the bump 18 is covered by the conductive film 24. Similarly, the upper surface of the second conductive pattern 23 is covered with the conductive film 24. The conductive film 24 is formed to prevent oxidation of the surface of the conductive pattern. This conductive film 24 is gold plating, for example. Of course, after a Ni plating is performed as basic plating, the laminated body etc. which formed gold plating are also included. Although the thickness of the conductive film 24 is not specifically limited, In this embodiment, it formed in the film thickness of about 20 micrometers.
Moreover, you may form the insulating film 25 in the part in which the electrical component of the 2nd conductive pattern 23, or the metal fine wire is not electrically connected. The insulating film 25 may be formed on a desired portion after the conductive film 24 is formed on the entire surface of the second conductive pattern 24. As described above, the substrate 10 having the bumps is manufactured.
4 and 5, the details of the bumps 18 will be described.
First, the thickness of bump 18 is demonstrated with reference to FIG. 4 which is an enlarged view of bump 18 vicinity. The thickness of the bump 18 here is a thickness obtained by adding the thickness T1 of the first conductive foil 12A, the thickness T2 of the conductive film 15 and the thickness T3 of the conductive film 24. In this embodiment, as mentioned above, since T1 is 175 micrometers, T2 is 20 micrometers, and T3 is 20 micrometers, bump height becomes 215 micrometers. Therefore, it becomes possible to fully separate the board | substrate 10 which has a bump and the mounting board | substrate by the bump 18. FIG. For example, it is very effective in the case where a part of a mounting component protrudes from the main end part of the board | substrate 10 which has bump, etc., and conventionally required the electrode which protrudes from the board | substrate side, but solder cream is applied. It is possible to mount the reflow using this.
The bump height is controlled by the thickness T1 of the first conductive foil 12. Since the conductive film 15 and the conductive film 24 are formed by plating, it takes time and cost to form a thick film. In addition, there is a limit to the thickness thereof. By using the manufacturing method of the board | substrate which has a bump of this form, it is possible to form the bump which has a height of up to 250 micrometers.
The first conductive foil 12B thinly formed by half etching includes a conductive path 26 that electrically connects a plurality of formed bumps. Therefore, when the bump 18 is mounted on the mounting substrate, the wiring of the mounting substrate can be extended between the bumps 18. In this embodiment, the thickness T4 of the second conductive pattern is formed to about 35 µm to 45 µm.
FIG. 5A illustrates a bump formation surface of a substrate having bumps, and FIG. 5B illustrates a circuit component mounting surface of the substrate 10 having bumps. In FIGS. 1-4, sectional drawing of the X-X 'line | wire in (a) of FIG. 5 is shown and demonstrated.
Referring to FIG. 5A, the conductive paths 26 electrically connect the bumps 18A and the bumps 18B. Here, the conductive film and the conductive film formed on the surface of the second conductive pattern 22 are omitted. In this embodiment, the through-holes are formed at the site where the bumps 18 are formed, and each bump 18 has a role of transmitting an electrical signal, and the dummy for stably supporting the substrate 10 having the bumps. Bumps and the like may also be formed. In addition, the bumps for exchanging electric signals are not directly connected to the second conductive patterns 22 through the through holes 14 but electrically connected to the other bumps 18 by the conductive paths 26. May be formed. That is, by forming the conductive paths 26, the design of the arrangement position of the bumps 18 can be facilitated. And since a multilayer wiring board can be formed, miniaturization of a circuit board is possible.
Referring to FIG. 5B, an electrical component 28 is mounted on the second conductive pattern 23. The electrical component 28A is a semiconductor element such as a transistor, a diode, or an IC. You may electrically connect using the fine metal wire 29. The electrical component 28B is a circuit element such as a chip resistor. And it can be set as a semiconductor device by sealing using resin or a casing so that the circuit component 28 may be coat | covered.
With reference to FIG. 6, the manufacturing method of the board | substrate 10 which has another form bump is demonstrated. Here, a description will be given focusing on the difference from the above-described manufacturing method. In the manufacturing method of the board | substrate 10 which has a bump of this form, bump 18 is not connected to the 1st conductive pattern 22, and the conductive path 26 of thickness smaller than the bump 18 can be formed. have.
First, referring to FIG. 6A, the filler 16A is filled in the through hole 14A, and the filler 16B is filled in the through hole 14B. The through holes 14A and the through holes 14B are formed simultaneously by the above-described method. The through hole 14A is formed in the site where the bump 18 is to be formed, and the through hole 14B is formed in the site where the wiring is formed. The filler 16A is the material described above, but the filler 16B used gypsum. However, the filler 16B may be a material which is not affected by the etching solution and can be removed by a solvent that does not affect the conductive foil.
Referring to FIG. 6B, the bumps 18 are formed by half etching the first conductive foil 12 and the conductive film 15 to form a predetermined thickness of the first conductive foil 12. At this time, the filler 16B filled in the through hole 14B has a structure protruding in a columnar shape.
Referring to FIG. 6C, a first conductive pattern 22 and a second conductive pattern 23 are formed by etching the first conductive foil 12 and the second conductive foil 13. Then, the filler 16B is removed, for example, with an alkaline solution such as caustic soda having a concentration of about 4%. That is, the filler 16B is formed to protect the conductive film 15 provided on the inner wall of the through hole 14 by etching for forming a conductive pattern. After removing the filler 16B, the through hole 14B may be filled with the filler 16A. In this way, a conductive path 26 having a thickness thinner than that of the bumps 18 is formed. This conductive path 26 makes it possible to form a wiring layer on the upper and lower surfaces of the substrate 11 with high complexity and high density.
It is also possible to form the bumps 18 in portions extending from the conductive paths 26 without forming the through holes 14 in the areas where the bumps 18 are formed.
According to the manufacturing method of the board | substrate with bump of this invention, bump is formed by etching the 1st conductive foil of thickness corresponding to the height of bump. Therefore, it can select with the thickness of the 1st conductive foil which employ | adopts the height of a bump. Thereby, it is possible to improve the precision with respect to the height of a bump. In addition, it is possible to easily form a bump having a height according to the standard, for example, it becomes possible to form the bump higher than the conventional solder bumps.
Moreover, according to the manufacturing method of the board | substrate with bump of this invention, bump is formed by etching a 1st conductive foil. Therefore, the positional accuracy of bumps is improved, and it becomes possible to provide the board | substrate which has bump with high connection reliability with the mounting board side. It is also possible to arbitrarily determine the shape of the bumps.
According to the method for manufacturing a substrate having a bump of the present invention, the first conductive foil is half-etched to form a bump, and the first conductive foil other than the region where the bump is formed is etched to form a conductive path having a lower height than the bump. Forming. Therefore, it is possible to electrically connect the bumps spaced apart from each other by the conductive path. This makes it possible to extend the wiring on the mounting substrate side between the bumps.
Moreover, according to the manufacturing method of the board | substrate with bump of this invention, bump is formed first and another wiring is formed according to the position of the formed bump. Therefore, it becomes possible to provide the board | substrate which has bump with high bump positional accuracy.
Moreover, according to the manufacturing method of the board | substrate with a bump of this invention, through-hole plating coat | covers the 1st conductive foil, the upper surface of the 2nd conductive foil, and the inner wall of a through hole integrally. Therefore, it becomes possible to reliably perform electrical connection of a 1st conductive foil and a 2nd conductive foil.
Moreover, according to the manufacturing method of the board | substrate with a bump of this invention, through-hole plating and a 1st conductive foil are made from the same metal. Therefore, since the through-hole plating and the first conductive foil can be etched using the same etchant, the manufacturing process can be simplified.
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2005-00034434 | 2005-02-10 | ||
JP2005034434A JP3955086B2 (en) | 2005-02-10 | 2005-02-10 | Manufacturing method of substrate with bumps |
Publications (2)
Publication Number | Publication Date |
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KR20060090739A KR20060090739A (en) | 2006-08-16 |
KR101174912B1 true KR101174912B1 (en) | 2012-08-17 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020050072638A KR101174912B1 (en) | 2005-02-10 | 2005-08-09 | Method of manufacturing substrate having bump |
Country Status (4)
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JP (1) | JP3955086B2 (en) |
KR (1) | KR101174912B1 (en) |
CN (1) | CN100521121C (en) |
TW (1) | TWI342730B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100752953B1 (en) * | 2006-08-23 | 2007-08-30 | 주식회사 유니테스트 | Method for manufacturing bump of probe card |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1027865A (en) | 1996-07-09 | 1998-01-27 | Mitsui Petrochem Ind Ltd | Semiconductor substrate |
JP2002076159A (en) | 2000-09-01 | 2002-03-15 | Hitachi Aic Inc | Case for electronic component and its manufacturing method |
-
2005
- 2005-02-10 JP JP2005034434A patent/JP3955086B2/en active Active
- 2005-07-13 TW TW094123677A patent/TWI342730B/en not_active IP Right Cessation
- 2005-08-09 KR KR1020050072638A patent/KR101174912B1/en not_active IP Right Cessation
- 2005-08-10 CN CNB2005100894452A patent/CN100521121C/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1027865A (en) | 1996-07-09 | 1998-01-27 | Mitsui Petrochem Ind Ltd | Semiconductor substrate |
JP2002076159A (en) | 2000-09-01 | 2002-03-15 | Hitachi Aic Inc | Case for electronic component and its manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
KR20060090739A (en) | 2006-08-16 |
CN100521121C (en) | 2009-07-29 |
TW200630001A (en) | 2006-08-16 |
JP2006222275A (en) | 2006-08-24 |
CN1819128A (en) | 2006-08-16 |
JP3955086B2 (en) | 2007-08-08 |
TWI342730B (en) | 2011-05-21 |
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