KR101140584B1 - Method for manufacturing high voltage semiconductor device - Google Patents
Method for manufacturing high voltage semiconductor device Download PDFInfo
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- KR101140584B1 KR101140584B1 KR1020100014085A KR20100014085A KR101140584B1 KR 101140584 B1 KR101140584 B1 KR 101140584B1 KR 1020100014085 A KR1020100014085 A KR 1020100014085A KR 20100014085 A KR20100014085 A KR 20100014085A KR 101140584 B1 KR101140584 B1 KR 101140584B1
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- 239000002019 doping agent Substances 0.000 abstract description 7
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/8232—Field-effect technology
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- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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Abstract
고전압 반도체 소자를 제조함에 있어서 Ron(Channel의 On저항)을 감소시킴으로써 칩(Chip)의 제조비용을 절감한 제조방법에 관해 개시한다. 본 발명의 방법은, 반도체 기판 상에 고전압 N웰 영역 및 고전압 P웰 영역을 형성하는 제1 단계와; 상기 고전압 P웰 영역 내에는 N형 불순물을 주입하여 NDR(Negative Differential Resistance) 영역을, 상기 고전압 N웰 영역 내에는 P형 불순물을 주입하여 PDR(Positive Differential Resistance) 영역을 각각 형성하는 제2 단계와; 상기 제2 단계의 결과물에 대해 소자분리 공정을 진행하는 제3 단계와; 상기 NDR 영역에 N형 불순물을, 상기 PDR 영역에 P형 불순물 추가로 도핑하여 턴온 저항을 낮추는 제4 단계를 구비하는 것을 특징으로 한다. 본 발명에 따르면, 장시간의 열처리를 하여 접합부(Junction)의 표면의 도펀트(Dophant) 농도가 낮아지는 것을 추가 도핑으로 보상할 수 있으므로 Ron을 감소시킬 수 있고, 이에 따라서 칩 면적이 증가하는 문제점도 해결할 수 있다.Disclosed is a manufacturing method in which a manufacturing cost of a chip is reduced by reducing Ron (on resistance of a channel) in manufacturing a high voltage semiconductor device. A method of the present invention includes a first step of forming a high voltage N well region and a high voltage P well region on a semiconductor substrate; A second step of forming NDR (Negative Differential Resistance) regions by injecting N-type impurities into the high voltage P well region and forming PDR (Positive Differential Resistance) regions by implanting P-type impurities into the high voltage N well region; ; A third step of performing a device isolation process on the resultant of the second step; And a fourth step of lowering a turn-on resistance by doping an N-type impurity into the NDR region and an additional P-type impurity into the PDR region. According to the present invention, the dopant concentration on the surface of the junction can be compensated by additional doping by prolonged heat treatment, so that Ron can be reduced, thereby solving the problem of increasing the chip area. Can be.
Description
본 발명은 고전압 반도체 소자 제조방법에 관한 것으로, 특히 이동기기의 파워 관리용 IC(Battery Manager, LED Power IC, LCD Power Management IC 등)의 제조를 위한 고전압 반도체 소자를 제조함에 있어서 Ron(Channel의 On저항)을 감소시킴으로써 칩(Chip)의 면적을 줄여서 제조비용을 절감한 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a high voltage semiconductor device, and particularly, in the manufacture of a high voltage semiconductor device for manufacturing a power management IC (Battery Manager, LED Power IC, LCD Power Management IC, etc.) of a mobile device. The present invention relates to a manufacturing method which reduces manufacturing cost by reducing an area of a chip by reducing resistance).
고전압 반도체 소자의 소스, 드레인(Source, Drain)은 통상적으로 이온 주입(Ion Implant)공정을 진행한 후에, 접합 항복(Junction Breakdown) 전압을 확보하기 위해 고온에서 장시간 열처리를 하게 된다. 그런데, 이러한 장시간의 열처리로 인하여 접합부(Junction)의 표면의 도펀트(Dophant) 농도가 낮아지게 된다. 도펀트(Dophant) 농도가 낮아지게 되면, 표면의 저항이 증가 하게 되고 이로 인해서 트랜지스터(Transistor)가 턴온(Turn On)되어 전류가 흐를때 낮은 표면 농도로 인해서 표면저항, 즉 턴온 저항(Ron)이 증가하게 된다. 일반적으로 트랜지스터의 턴온 저항(Ron)이 증가하게 되면 파워 관리용(Power Management) IC제품의 경우 증가된 저항을 극복하기 위해 파워(Power) 구동부의 면적이 증가하게 되고 이로 인해 제품의 사이즈가 커지게 된다.Source and drain of the high-voltage semiconductor device is typically subjected to an ion implantation process, and then heat treated at a high temperature for a long time to secure a junction breakdown voltage. However, due to such a long heat treatment, the dopant concentration on the surface of the junction is lowered. When the dopant concentration is lowered, the surface resistance increases, which causes the transistor to turn on, resulting in an increase in surface resistance, ie, turn-on resistance, due to the low surface concentration when the current flows. Done. In general, when the turn-on resistance of the transistor increases, the area of the power driving unit increases to overcome the increased resistance in the case of a power management IC product, which increases the size of the product. do.
따라서, 본 발명이 해결하려는 과제는, 트랜지스터의 턴온 저항을 감소시켜서 파워 구동부의 면적 증가에 따른 제품의 사이즈 증가문제를 발생시키지 않는 고전압 반도체 소자 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method for manufacturing a high voltage semiconductor device, which reduces the turn-on resistance of a transistor and does not cause an increase in size of a product due to an increase in the area of the power driver.
상기한 과제를 해결하기 위한 본 발명은: 반도체 기판 상에 고전압 N웰 영역 및 고전압 P웰 영역을 형성하는 제1 단계와; 상기 고전압 P웰 영역 내에는 N형 불순물을 주입하여 NDR(Negative Differential Resistance) 영역을, 상기 고전압 N웰 영역 내에는 P형 불순물을 주입하여 PDR(Positive Differential Resistance) 영역을 각각 형성하는 제2 단계와; 상기 제2 단계의 결과물에 대해 소자분리 공정을 진행하는 제3 단계와; 상기 NDR 영역에 N형 불순물을, 상기 PDR 영역에 P형 불순물 추가로 도핑하여 턴온 저항을 낮추는 제4 단계를 구비하는 것을 특징으로 한다.The present invention for solving the above problems comprises: a first step of forming a high voltage N well region and a high voltage P well region on a semiconductor substrate; A second step of forming NDR (Negative Differential Resistance) regions by injecting N-type impurities into the high voltage P well region and forming PDR (Positive Differential Resistance) regions by implanting P-type impurities into the high voltage N well region; ; A third step of performing a device isolation process on the resultant of the second step; And a fourth step of lowering a turn-on resistance by doping an N-type impurity into the NDR region and an additional P-type impurity into the PDR region.
여기서 상기 고전압 N웰 영역 및 고전압 P웰 영역을 형성하는 제1 단계가: 고전압 N웰 영역을 규정짓기 위한 포토 리소그래피 단계와; 31P+를 70~150KeV, 6.0E12~1.5E13로 상기 고전압 N웰 영역에 이온주입하는 단계와; 고전압 P웰 영역을 규정짓기 위한 포토 리소그래피 단계와; 49BF2+를 100~150KeV, 6.0E12~1.5E13로 상기 고전압 P웰 영역에 이온주입하거나 11B+를 60~100KeV, 6.0E12~1.5E13로 상기 고전압 P웰 영역에 이온주입하는 단계와; 1200℃에서 550~660분간 열처리하여 웰 드라이브인(Well Drive In) 공정을 진행하는 단계를 구비하는 것이 바람직하다.Wherein a first step of forming the high voltage N well region and the high voltage P well region comprises: a photolithography step for defining a high voltage N well region; Implanting 31P + into the high voltage N well region at 70 to 150 KeV and 6.0E12 to 1.5E13; A photolithography step for defining a high voltage P well region; Implanting 49BF2 + into the high voltage P well region at 100 to 150 KeV and 6.0E12 to 1.5E13 or ion implanting 11B + into the high voltage P well region at 60 to 100 KeV and 6.0E12 to 1.5E13; It is preferable to have a step of performing a well drive in (Well Drive In) process by heat treatment at 1200 ℃ 550 ~ 660 minutes.
또한, 상기 제2 단계가: NDR 영역을 규정짓기 위한 포토 리소그래피 단계와; 31P+를 120~170KeV, 1.0~2.0E13로 상기 NDR 영역에 이온주입하는 단계와; PDR 영역을 규정짓기 위한 포토 리소그래피 단계와; 49BF2+를 100~180KeV, 1.0~2.0E13로 상기 PDR 영역에 이온주입하는 단계와; 1100 ~ 1200℃에서 180~250분간 열처리하여 드리프트 드라이브인(Drift Drive In) 공정을 진행하는 단계를 구비하는 것이 바람직하다.The second step further comprises: a photolithography step for defining an NDR region; Implanting 31P + into the NDR region at 120 to 170 KeV and 1.0 to 2.0E13; Photolithography step for defining a PDR region; Implanting 49BF 2+ into the PDR region at 100 to 180 KeV and 1.0 to 2.0E13; It is preferable to have a step of performing a drift drive In (Drift Drive In) process by heat treatment at 1100 ~ 1200 ℃ for 180 ~ 250 minutes.
더욱이, 상기 제4 단계가: 상기 NDR 영역에 31P+을 400~500KeV, 4.0~8.0E12로 이온주입하고, 31P+을 200~500KeV, 6.0~9.0E12로 이온주입하는 단계와; 상기 PDR 영역에 11B+을 300~500KeV, 2.0~4.0E13로 이온주입하고, 11B+을 160~200KeV, 4.0~8.0E12로 이온주입하고, 11B+를 20KeV, 2.0~5.0E12로 이온주입하는 단계를 구비하는 것이 바람직하다.Further, the fourth step includes: ion implantation of 31P + into 400-500 KeV, 4.0-8.0E12, and ion implantation of 31P + into 200-500 KeV, 6.0-9.0E12 into the NDR region; Ion implanting 11B + into the PDR region at 300 to 500 KeV, 2.0 to 4.0E13, ion implanting 11B + at 160 to 200 KeV, 4.0 to 8.0E12, and ion implanting 11B + at 20 KeV, 2.0 to 5.0E12. It is preferable.
상기한 본 발명에 따르면, 고전압 반도체 소자가 동일한 성능을 발휘하면서도 턴온 저항(Ron)을 감소시킬 수 있으며, 턴온 저항(Ron)의 감소로 인해 제품의 사이즈도 현격히 감소시킬 수 있다.According to the present invention, the high-voltage semiconductor device can reduce the turn-on resistance (Ron) while performing the same performance, and the size of the product can be significantly reduced due to the decrease in the turn-on resistance (Ron).
도 1a 내지 도 1d는 본 발명의 실시예에 따른 고전압 반도체 소자 제조방법을 설명하기 위한 단면도들;
도 2a는 본 발명의 실시예에 따른 고전압 PMOS 소자의 레이아웃;
도 2b는 본 발명의 실시예에 따른 고전압 NMOS 소자의 레이아웃;
도 3a 및 도 3b는 본 발명의 실시예에 따른 고전압 PMOS 소자를 바이폴라 트랜지스터 및 유니폴라 트랜지스터로 각각 구현한 예를 나타낸 단면도;
도 3c 및 도 3d는 본 발명의 실시예에 따른 고전압 NMOS 소자를 바이폴라 트랜지스터 및 유니폴라 트랜지스터로 각각 구현한 예를 나타낸 단면도; 및
도 4a 내지 도 4d는 본 발명의 방법이 유효함을 나타내기 위해 전기적 특성을 측정한 그래프들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a high voltage semiconductor device according to an embodiment of the present invention;
2A is a layout of a high voltage PMOS device in accordance with an embodiment of the present invention;
2B is a layout of a high voltage NMOS device in accordance with an embodiment of the present invention;
3A and 3B are cross-sectional views illustrating examples of implementing a high voltage PMOS device according to an embodiment of the present invention as a bipolar transistor and a unipolar transistor, respectively;
3C and 3D are cross-sectional views illustrating examples of implementing a high voltage NMOS device according to an embodiment of the present invention as a bipolar transistor and a unipolar transistor, respectively; And
4A-4D are graphs of measuring electrical properties to show that the method of the present invention is effective.
이하에서, 본 발명의 바람직한 실시예를 첨부한 도면들을 참조하여 상세히 설명한다. 아래의 실시예는 본 발명의 내용을 이해하기 위해 제시된 것일 뿐이며 당 분야에서 통상의 지식을 가진 자라면 본 발명의 기술적 사상 내에서 많은 변형이 가능할 것이다. 따라서 본 발명의 권리범위가 이러한 실시예에 한정되는 것으로 해석되어서는 안 된다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are merely provided to understand the contents of the present invention, and those skilled in the art will be able to make many modifications within the technical scope of the present invention. Therefore, the scope of the present invention should not be construed as limited to these examples.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 고전압 반도체 소자 제조방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a high voltage semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 고전압 N웰 영역(110) 및 고전압 P웰 영역(120)이 기판(미도시)에 형성된다. 이 공정은, 고전압 N웰 영역(110)을 규정짓기 위한 포토 리소그래피(photolithography) 공정을 진행하고, 31P+를 70~150KeV, 6.0E12~1.5E13로 고전압 N웰 영역(110)에 이온주입한 다음, 고전압 P웰 영역(120)을 규정짓기 위한 포토 리소그래피 공정을 진행하고, 49BF2+를 100~150KeV, 6.0E12~1.5E13로 고전압 P웰 영역(120)에 이온주입하거나 11B+를 60~100KeV, 6.0E12~1.5E13로 상기 고전압 P웰 영역(120)에 이온주입한 후에, 전체 기판을 1200℃에서 550~660분간 열처리하여 웰 드라이브인(Well Drive In) 공정을 진행함으로써 이루어진다.Referring to FIG. 1A, a high voltage N
이어서, 도 1b에 도시한 바와 같이, 고전압 P웰 영역(120) 내에는 N형 불순물을 주입하여 NDR(Negative Differential Resistance) 영역(122)을, 고전압 N웰 영역(110) 내에는 P형 불순물을 주입하여 PDR(Positive Differential Resistance) 영역(112)을 각각 형성한다. NDR 영역(122)과 PDR영역(112)은 다음 공정을 진행함으로써 형성한다. 먼저, NDR 영역(122)을 규정짓기 위한 포토 리소그래피 공정을 진행하고, 31P+를 120~170KeV, 1.0~2.0E13로 NDR 영역(122)에 이온주입한 다음, PDR 영역(112)을 규정짓기 위한 포토 리소그래피 공정을 진행하고, 49BF2+를 100~180KeV, 1.0~2.0E13로 PDR 영역(112)에 이온주입한 후, 결과물 기판을 1100 ~ 1200℃에서 180~250분간 열처리하여 드리프트 드라이브인(Drift Drive In) 공정을 진행한다.Subsequently, as shown in FIG. 1B, an N type impurity is implanted into the high voltage
도 1c를 참조하면, 소자 분리(isolation)를 위한 절연막(130)을 형성한 후, NDR 영역(122)에 N형 불순물을 추가로 도핑하여 ADDN 영역(124)을 만들고, PDR 영역(112)에 P형 불순물 추가로 도핑하여 ADDP 영역(114)을 만든다. 이와 같이 추가 도핑에 의해 ADDN 영역(124)과 ADDP 영역(114)을 만드는 이유는, 장시간의 열처리를 하여 접합부(Junction)의 표면의 도펀트(Dophant) 농도가 낮아지는 것을 보상하기 위함이다. 따라서, ADDN 영역(124)과 ADDP 영역(114)은 고전압 소자의 턴온 저항(Ron)을 낮추는 용도로 사용할 뿐 아니라, 동시에 시스템에서 로직(LOGIC)전원으로 사용되는 저전압소자(3.3V 혹은 5.0V)의 웰(WELL)로도 사용한다. 이 때, ADDN 영역(124)은 구체적으로 NDR 영역(122)에 31P+을 400~500KeV, 4.0~8.0E12로 이온주입하고, 31P+을 200~500KeV, 6.0~9.0E12로 이온주입하여 형성하고, ADDP 영역(114)은 PDR 영역(112)에 11B+을 300~500KeV, 2.0~4.0E13로 이온주입하고, 11B+을 160~200KeV, 4.0~8.0E12로 이온주입하고, 11B+를 20KeV, 2.0~5.0E12로 이온주입하여 형성한다.Referring to FIG. 1C, after forming an
이어서, 게이트 산화막(Gate Oxide)과 게이트 전극을 차례로 형성하여 게이트 구조(140)를 도 1d와 같이 완성한다.Subsequently, a gate oxide film and a gate electrode are sequentially formed to complete the
그 다음, 통상의 제조공정과 마찬가지로 소스(Source), 드레인(Drain)을 형성하고 배선(interconnection)공정을 진행하여 고전압 반도체 소자의 제조를 완료한다(이후 공정 미도시).Then, as in the usual manufacturing process, the source and the drain are formed and the interconnection process is performed to complete the manufacture of the high voltage semiconductor device (the subsequent process is not shown).
도 2a는 본 발명의 실시예에 따른 고전압 PMOS 소자의 레이아웃이다. 도 2a를 참조하면, PDR영역(112) 내에 P형 불순물 추가로 도핑된 ADDP 영역(114)이 형성되어 있음을 알 수 있다. 도 2a에서 참조번호 150은 필드 플레이트(field plate), 참조번호 160은 액티브영역(active area)을 각각 나타낸다.2A is a layout of a high voltage PMOS device in accordance with an embodiment of the present invention. Referring to FIG. 2A, it can be seen that the ADDP
도 2b는 본 발명의 실시예에 따른 고전압 NMOS 소자의 레이아웃이다. 도 2b를 참조하면, NDR 영역(122) 내에 N형 불순물 추가로 도핑된 ADDN 영역(124)이 형성되어 있음을 알 수 있다.2B is a layout of a high voltage NMOS device in accordance with an embodiment of the present invention. 2B, it can be seen that the ADDN
도 3a 및 도 3b는 본 발명의 실시예에 따른 고전압 PMOS 소자를 바이폴라 트랜지스터 및 유니폴라 트랜지스터로 각각 구현한 예를 나타낸 단면도이다. 도 3b의 경우, P형 기판 상에 트랜지스터를 형성하였으며, 도 3a와는 달리 몸체(벌크, Bulk), 소스, 드레인에 대한 콘택까지 형성된 상태를 나타내었다. 콘택 형성부위 부근에 ADDP 영역이 형성되기 때문에, 장시간의 열처리에 의한 도펀트 손실을 보상할 수 있어서 턴온 저항(Ron)이 감소하게 됨을 알 수 있다.3A and 3B are cross-sectional views illustrating examples in which a high voltage PMOS device according to an embodiment of the present invention is implemented as a bipolar transistor and a unipolar transistor, respectively. In the case of FIG. 3B, a transistor is formed on a P-type substrate, and unlike FIG. 3A, a contact is formed to a body (bulk, bulk), a source, and a drain. Since the ADDP region is formed in the vicinity of the contact forming portion, it can be seen that the dopant loss due to prolonged heat treatment can be compensated, thereby reducing the turn-on resistance Ron.
도 3c 및 도 3d는 본 발명의 실시예에 따른 고전압 NMOS 소자를 바이폴라 트랜지스터 및 유니폴라 트랜지스터로 각각 구현한 예를 나타낸 단면도이다. 도 3d의 경우, P형 기판 상에 트랜지스터를 형성하였으며, 도 3c와는 달리 몸체(벌크, Bulk), 소스, 드레인에 대한 콘택까지 형성된 상태를 나타내었다. 콘택 형성부위 부근에 ADDN 영역이 형성되기 때문에, 장시간의 열처리에 의한 도펀트 손실을 보상할 수 있어서 턴온 저항(Ron)이 감소하게 됨을 알 수 있다.3C and 3D are cross-sectional views illustrating examples in which a high voltage NMOS device according to an embodiment of the present invention is implemented as a bipolar transistor and a unipolar transistor, respectively. In the case of FIG. 3D, a transistor is formed on the P-type substrate, and unlike FIG. 3C, a contact with respect to a body (bulk, bulk), a source, and a drain is illustrated. Since the ADDN region is formed in the vicinity of the contact forming portion, it can be seen that the dopant loss due to the long heat treatment can be compensated for, thereby reducing the turn-on resistance (Ron).
도 4a 내지 도 4d는 본 발명의 방법이 유효함을 나타내기 위해 전기적특성을 측정한 그래프들이다.4A-4D are graphs of electrical properties measured to show that the method of the present invention is effective.
구체적으로 도 4a는 고전압 PMOS 유니폴라 트랜지스터에 대해 턴온 저항(Ron.sp)과 소스-드레인 간의 최대 전압값(BVDSS)을 측정한 결과이다. 종래 기술에 비해 우월한 효과를 확인하기 위해 본 발명의 방법으로 제조된 것과 종래기술의 방법으로 제조된 것을 함께 비교하였다. 본 발명의 방법으로 제조된 3가지 다른 샘플에 대해 측정을 행하였다. 그 결과, 소스-드레인 간의 최대 전압값(BVDSS)에서는 종래기술과 본 발명이 큰 차이를 나타내지 않았지만, 턴온 저항(Ron.sp)에 대해서는 본 발명의 경우에 훨씬 낮은 값을 갖는 것을 확인할 수 있었다.In detail, FIG. 4A illustrates a result of measuring the maximum voltage value BVDSS between the turn-on resistance Ron.sp and the source-drain of the high voltage PMOS unipolar transistor. In order to confirm the superior effect compared to the prior art, the one prepared by the method of the present invention and the one prepared by the method of the prior art were compared together. Measurements were made on three different samples made by the method of the present invention. As a result, the maximum voltage value (BVDSS) between the source and the drain did not show a significant difference between the present invention and the present invention, but it was confirmed that the turn-on resistance (Ron.sp) had a much lower value in the case of the present invention.
도 4b는 고전압 PMOS 바이폴라 트랜지스터에 대해 턴온 저항(Ron.sp)과 소스-드레인 간의 최대 전압값(BVDSS)을 측정한 결과이다. 측정방식은 도 4a의 경우와 마찬가지로 행하였으며, 그 결과 역시 도 4a의 경우와 마찬가지인 것으로 확인되었다.4B is a result of measuring the maximum voltage value (BVDSS) between the turn-on resistor (Ron.sp) and the source-drain for the high voltage PMOS bipolar transistor. The measurement method was performed similarly to the case of FIG. 4A, and the result was confirmed to be the same as that of FIG. 4A.
도 4c 및 도 4d는 고전압 NMOS 유니폴라 트랜지스터와 바이폴라 트랜지스터의 각각에 대해 턴온 저항(Ron.sp)과 소스-드레인 간의 최대 전압값(BVDSS)을 측정한 결과이다. 측정방식은 도 4a의 경우와 마찬가지로 행하였으며, 그 결과 역시 도 4a의 경우와 마찬가지인 것으로 확인되었다.
4C and 4D show the results of measuring the maximum voltage value BVDSS between the turn-on resistance Ron.sp and the source-drain for each of the high voltage NMOS unipolar transistor and the bipolar transistor. The measurement method was performed similarly to the case of FIG. 4A, and the result was confirmed to be the same as that of FIG. 4A.
110: 고전압 N웰 영역
112: PDR(Positive Differential Resistance) 영역
114: P형 불순물이 추가로 도핑된 ADDP 영역
120: 고전압 P웰 영역
122: NDR(Negative Differential Resistance) 영역
124: N형 불순물이 추가로 도핑된 ADDN 영역
130: 소자 분리(isolation)를 위한 절연막
140: 게이트 구조
150: 필드 플레이트(field plate)
160: 액티브영역(active area)110: high voltage N well area
112: Positive Differential Resistance (PDR) region
114: ADDP region further doped with P-type impurity
120: high voltage P well region
122: NDR (Negative Differential Resistance) region
124: ADDN region further doped with N-type impurities
130: insulating film for device isolation
140: gate structure
150: field plate
160: active area
Claims (4)
(B) 상기 고전압 P웰 영역 내에는 N형 불순물을 주입하여 NDR(Negative Differential Resistance) 영역을, 상기 고전압 N웰 영역 내에는 P형 불순물을 주입하여 PDR(Positive Differential Resistance) 영역을 각각 형성하는 제2 단계와;
(C) 상기 제2 단계의 결과물에 대해 소자분리 공정을 진행하는 제3 단계와;
(D) 상기 NDR 영역에 N형 불순물을, 상기 PDR 영역에 P형 불순물 추가로 도핑하여 턴온 저항을 낮추는 제4 단계;
를 포함하고,
상기 단계 (A)는,
(A-1) 고전압 N웰 영역을 규정짓기 위한 포토 리소그래피 단계와;
(A-2) 31P+를 70~150KeV, 6.0E12~1.5E13로 상기 고전압 N웰 영역에 이온주입하는 단계와;
(A-3) 고전압 P웰 영역을 규정짓기 위한 포토 리소그래피 단계와;
(A-4) 49BF2+를 100~150KeV, 6.0E12~1.5E13로 상기 고전압 P웰 영역에 이온주입하거나 11B+를 60~100KeV, 6.0E12~1.5E13로 상기 고전압 P웰 영역에 이온주입하는 단계와;
(A-5) 1200℃에서 550~660분간 열처리하여 웰 드라이브인(Well Drive In) 공정을 진행하는 단계;를 포함하고,
상기 단계 (B)는,
(B-1) NDR 영역을 규정짓기 위한 포토 리소그래피 단계와;
(B-2) 31P+를 120~170KeV, 1.0~2.0E13로 상기 NDR 영역에 이온주입하는 단계와;
(B-3) PDR 영역을 규정짓기 위한 포토 리소그래피 단계와;
(B-4) 49BF2+를 100~180KeV, 1.0~2.0E13로 상기 PDR 영역에 이온주입하는 단계와;
(B-5) 1100 ~ 1200℃에서 180~250분간 열처리하여 드리프트 드라이브인(Drift Drive In) 공정을 진행하는 단계;를 포함하고,
상기 단계 (D)는,
(D-1) 상기 NDR 영역에 31P+을 400~500KeV, 4.0~8.0E12로 이온주입하고, 31P+을 200~500KeV, 6.0~9.0E12로 이온주입하는 단계와;
(D-2) 상기 PDR 영역에 11B+을 300~500KeV, 2.0~4.0E13로 이온주입하고, 11B+을 160~200KeV, 4.0~8.0E12로 이온주입하고, 11B+를 20KeV, 2.0~5.0E12로 이온주입하는 단계;를 포함하는 것을 특징으로 하는 고전압 반도체 소자 제조방법.(A) forming a high voltage N well region and a high voltage P well region on the semiconductor substrate;
(B) forming a negative differential resistance (NDR) region by injecting N-type impurities into the high voltage P well region, and forming a positive differential resistance (PDR) region by implanting P-type impurities into the high voltage N well region; Two steps;
(C) a third step of proceeding with a device isolation process for the resultant of the second step;
(D) a fourth step of lowering turn-on resistance by doping an N-type impurity in the NDR region and a P-type impurity in the PDR region;
Including,
Step (A) is,
(A-1) photolithography step for defining a high voltage N well region;
(A-2) ion implantation of 31P + into the high voltage N well region at 70 to 150 KeV and 6.0E12 to 1.5E13;
(A-3) photolithography step for defining a high voltage P well region;
(A-4) ion implantation of 49BF2 + into the high voltage P well region at 100 to 150 KeV, 6.0E12 to 1.5E13, or ion implantation of 11B + at the high voltage P well region at 60 to 100 KeV, 6.0E12 to 1.5E13;
(A-5) performing a well drive-in process by performing heat treatment at 1200 ° C. for 550 to 660 minutes; and
Step (B) is,
(B-1) photolithography step for defining the NDR region;
(B-2) ion implantation of 31P + into the NDR region at 120 to 170 KeV and 1.0 to 2.0E13;
(B-3) photolithography step for defining the PDR region;
(B-4) implanting 49BF 2+ into the PDR region at 100 to 180 KeV and 1.0 to 2.0E13;
(B-5) performing a drift drive in process by heat-treating at 1100 to 1200 ° C. for 180 to 250 minutes.
The step (D),
(D-1) ion implantation of 31P + into 400-500 KeV, 4.0-8.0E12 in the NDR region, and ion implantation of 31P + into 200-500 KeV, 6.0-9.0E12;
(D-2) 11B + is ion implanted into the PDR region at 300 to 500 KeV, 2.0 to 4.0E13, 11B + is ion implanted at 160 to 200 KeV, 4.0 to 8.0E12, and 11B + is ion implanted to 20 KeV, 2.0 to 5.0E12. High voltage semiconductor device manufacturing method comprising a.
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|---|---|---|---|---|
| KR20020056275A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Seconductor device |
| KR20040002138A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Logic prat isolation type high voltage transistor |
| KR20040100918A (en) * | 2003-05-21 | 2004-12-02 | 샤프 가부시키가이샤 | Semiconductor device and method of manufacturing the same |
| KR20060053442A (en) * | 2004-11-15 | 2006-05-22 | 매그나칩 반도체 유한회사 | Method for fabricating high voltage device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020056275A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Seconductor device |
| KR20040002138A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Logic prat isolation type high voltage transistor |
| KR20040100918A (en) * | 2003-05-21 | 2004-12-02 | 샤프 가부시키가이샤 | Semiconductor device and method of manufacturing the same |
| KR20060053442A (en) * | 2004-11-15 | 2006-05-22 | 매그나칩 반도체 유한회사 | Method for fabricating high voltage device |
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