KR101078309B1 - Method for forming contacts of semiconductor devices using the selective deposition - Google Patents
Method for forming contacts of semiconductor devices using the selective deposition Download PDFInfo
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- KR101078309B1 KR101078309B1 KR1020090025405A KR20090025405A KR101078309B1 KR 101078309 B1 KR101078309 B1 KR 101078309B1 KR 1020090025405 A KR1020090025405 A KR 1020090025405A KR 20090025405 A KR20090025405 A KR 20090025405A KR 101078309 B1 KR101078309 B1 KR 101078309B1
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 230000008021 deposition Effects 0.000 title description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 35
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 32
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- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 28
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000013545 self-assembled monolayer Substances 0.000 claims abstract description 22
- 239000002094 self assembled monolayer Substances 0.000 claims abstract description 20
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 18
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- PYJJCSYBSYXGQQ-UHFFFAOYSA-N trichloro(octadecyl)silane Chemical compound CCCCCCCCCCCCCCCCCC[Si](Cl)(Cl)Cl PYJJCSYBSYXGQQ-UHFFFAOYSA-N 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000002243 precursor Substances 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical group N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
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- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000010926 purge Methods 0.000 description 7
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- 238000010438 heat treatment Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 4
- 238000004630 atomic force microscopy Methods 0.000 description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
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- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
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- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical group 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
Abstract
본 발명은 전이금속의 원자층 증착 공정과 자기조립 단분자막을 이용하여 원하는 부분에 박막을 증착할 수 있어 실리콘 소자의 콘택트 형성에 적용할 수 있는 방법에 관한 것으로서, 자기조립 단분자막을 원하는 부분에 코팅하여 표면 개질을 행한 뒤 원자층 증착 공정을 실행하여 개질된 표면, 혹은 개질되지 않은 표면 위에만 선택적으로 증착이 일어나도록 한다. 이를 사용하여 실리콘 전자소자의 콘택트 형성시에 간편화된 방법으로 기존의 방법을 대체 할 수 있다.The present invention relates to a method for applying a thin film to a desired portion using an atomic layer deposition process of a transition metal and a self-assembled monomolecular film, which can be applied to contact formation of a silicon device. After surface modification, an atomic layer deposition process is performed to selectively deposit only on the modified or unmodified surface. By using this, it is possible to replace the existing method by a simplified method when forming a contact of a silicon electronic device.
원자층 증착 공정, 자기조립 단분자막, 코발트, 니켈, 금속 박막, 콘택트, 실리사이드 Atomic Layer Deposition Process, Self-assembled Monolayer, Cobalt, Nickel, Metal Thin Film, Contact, Silicide
Description
본 발명은 선택적인 증착 방법을 이용하여 반도체 소자의 콘택트를 형성하는 방법에 관한 것으로서, 보다 구체적으로는 원자층 증착법과 자기조립 단분자막을 활용하여 필요한 부분에만 금속 박막을 선택적으로 증착함으로써, 반도체 소자의 콘택트 형성 방법을 간소화하고 형성된 콘택트 소자의 신뢰성을 개선하는데 적용할 수 있는 기술에 관한 것이다.The present invention relates to a method of forming a contact of a semiconductor device using a selective deposition method, and more particularly, by selectively depositing a metal thin film only in necessary portions by using atomic layer deposition and self-assembled monolayer film, The present invention relates to a technique that can be applied to simplify the method of forming a contact and to improve the reliability of the formed contact device.
반도체 소자 혹은 전자 소자의 특성을 향상시키기 위해서는 콘택트 저항을 낮추는 것이 매우 중요한데, 이를 위해 실리콘 기반의 전자 소자에서는 실리콘과 물리적 전기적으로 적합성이 뛰어난 금속 실리사이드를 콘택트로 사용해오고 있다.In order to improve the characteristics of a semiconductor device or an electronic device, it is very important to lower contact resistance. To this end, silicon-based electronic devices have used metal silicides having excellent physical and electrical compatibility with silicon as contacts.
한편, 금속 실리사이드를 제작하는 통상적인 방법은 실리콘 기판 위에 금속 박막을 증착하고 난 뒤, 열처리를 통해 실리콘과 금속 박막을 열적으로 반응시켜 금속 실리사이드를 형성하는 것이다. 이때 원하는 콘택트 부분에만 금속 실리사이드를 형성하기 위해서 금속 박막 증착 직후 에칭을 통한 패터닝(patterning)을 하거나, 금속 실리사이드가 형성된 후 에칭을 통해 패터닝을 하는 공정을 사용한다.On the other hand, a conventional method for manufacturing a metal silicide is to deposit a metal thin film on a silicon substrate, and then thermally react the silicon and the metal thin film through heat treatment to form a metal silicide. At this time, in order to form the metal silicide only on the desired contact portion, patterning is performed by etching immediately after deposition of the metal thin film, or patterning is performed by etching after the metal silicide is formed.
이러한 기술을 개선시켜 공정을 간편화한 방법이 금속 산화물 반도체 트랜지스터 (metal-oxide-semiconductor field effect transistor; MOSFET) 소자 제작 공정에서 사용되는 소위 '샐리사이드(self-algined silicide; SALICIDE)' 기법이다. 샐리사이드 기법은 금속 박막이 실리콘 산화물 위에서는 열처리에 의해 금속 실리사이드로 변하지 않는 점을 이용하여, 도 9에 도시된 바와 같이, 마스크를 사용하지 않고 반도체 소자 전체에 금속 박막을 형성한 후 열처리를 한 후에, 산화물 상에 증착된 미반응 금속 박막을 제거하는 것을 특징으로 하는 방법이다.An improved method to simplify the process is a so-called 'salidal (SALICIDE)' technique used in the manufacturing process of metal-oxide-semiconductor field effect transistor (MOSFET) devices. In the salicide method, since the metal thin film does not change into metal silicide by heat treatment on silicon oxide, as shown in FIG. 9, the metal thin film is formed on the entire semiconductor device without using a mask and then heat treated. Afterwards, the unreacted metal thin film deposited on the oxide is removed.
그런데, 샐리사이드 기법은 마스크를 이용하지 않는 점에서는 전술한 방법에 비해 개선되었다고 할 수 있으나, 여전히 미반응 금속 박막을 제거해야 하는 공정이 필요하고, 잔존하는 금속 박막에 의해 실리콘 산화물(스페이서)에서 발생할 수 있는 브리징(bridging)에 의한 누설 전류 발생의 단점을 내포하고 있다. 더욱이 기존의 샐리사이드 기법은 단차 피복성에도 한계가 있다. 현재 샐리사이드 기법에서 사용하는 스퍼터링과 같은 물리적 기상 증착법은 단차 피복성이 좋지 않기 때문에, 소자의 소형화에 따라 요구되는 깊은 콘택트 홀 내부에의 증착과 같은 기술적 요구에 대응하기 어렵다.By the way, the salicide technique has been improved over the aforementioned method in that it does not use a mask, but it still requires a process to remove the unreacted metal thin film, and the remaining metal thin film is used in the silicon oxide (spacer). There is a disadvantage of leakage current generation due to bridging that may occur. Moreover, the conventional salicide technique also has a limitation in step coverage. Physical vapor deposition methods such as sputtering currently used in the salicide technique have poor step coverage, making it difficult to meet technical requirements such as deposition into deep contact holes required by the miniaturization of devices.
이에 따라 단차 피복성이 매우 우수한 원자층증착법(Atomic Layer Deposition, ALD)을 콘택트의 제작에 적용할 필요가 있으나, 콘택트 물질로 사용되는 전이 금속(코발트, 니켈 등)에 관한 연구와 그에 대한 ALD의 선택적 증착 방법은 거의 연구되지 않고 있는 실정이다.As a result, it is necessary to apply ALD (Atomic Layer Deposition), which has very high step coverage, in the manufacture of contacts, but studies on transition metals (cobalt, nickel, etc.) used as contact materials and ALD Selective deposition methods are rarely studied.
한편, 원자층증착법은 원하는 원소가 포함된 화합물인 전구체와 이를 산화 또는 환원시키는 반응물이 구분되어 투입되면서 오직 표면 위에서만 일어나는 반응에 기반하기 때문에, 증착될 표면의 변화에 따라 다양한 증착 특성이 구현될 수 있다.On the other hand, the atomic layer deposition method is based on the reaction that occurs only on the surface of the precursor and the reactant oxidizing or reducing it containing the desired element is separated, so that various deposition characteristics can be implemented according to the change of the surface to be deposited Can be.
또한, 표면의 개질에 쉽게 사용할 수 있는 물질로는 자기조립 단분자막 (self-assembled monolayer, SAM)이 알려져 있다. 자기조립 단분자막의 한 종류인 (octadecyltrichlorosilane; OTS)을 예를 들면, OTS는 길이가 2.7nm인 길쭉한 형태의 분자로서, 한쪽 끝(반응기)이 실란기 (-SiCl3)로 끝나며, 다른 한쪽(작용기)은 메틸기 (-(CH3)3)으로 끝나고 중간은 18개의 탄소 체인으로 이루어져 있다. 이중 실란기로 끝나는 부분은 친수성인 표면(예: SiO2)에 잘 흡착되어 기판과 공유결합으로 이루며 분자들 간의 자발적인 정렬이 이루어지고, 반대편 메틸기로 끝나는 부분에 의해 OTS가 코팅된 표면은 소수성으로 변한다.In addition, a self-assembled monolayer (SAM) is known as a material that can be easily used for surface modification. For example, octadecyltrichlorosilane (OTS), which is a type of self-assembled monolayer, is an elongated molecule of 2.7 nm in length, with one end (reactor) ending with a silane group (-SiCl 3 ) and the other (functional group). ) Ends with a methyl group (-(CH 3 ) 3 ) and the middle consists of 18 carbon chains. The end of the double silane group is well adsorbed on a hydrophilic surface (eg SiO 2 ) to form a covalent bond with the substrate, spontaneous alignment between molecules, and the OTS-coated surface becomes hydrophobic by the end of the opposite methyl group. .
이러한 원리를 이용하여, 자기조립 단분자막의 반응기와 작용기를 조절하면 박막을 형성하고자 하는 표면을 친수성 혹은 소수성으로 만들 수 있을 뿐 아니라, 자기조립 단분자막 자체도 특정 부분에만 흡착시킬 수 있다.By using this principle, by controlling the reactor and the functional group of the self-assembled monolayer, the surface to be formed as a thin film can be made hydrophilic or hydrophobic, and the self-assembled monolayer can itself be adsorbed only to a specific portion.
본 발명은 전술한 종래의 반도체 소자의 콘택트용 금속 실리사이드 제조방법의 문제점을 해결하기 위해 창안된 것으로서, 단차 피복성이 우수하여 소자의 초소형화에 용이하게 대응할 수 있을 뿐 아니라, 추가적인 패터닝 공정이 필요 없고, 샐리사이드법과 같은 금속 박막 제거 공정이나 이에 따른 누설전류 발생의 문제점이 제거될 수 있는, 간소화된 반도체 소자의 콘택트 형성방법을 제공하는 것을 목적으로 한다.The present invention was devised to solve the above-mentioned problems of the conventional method of manufacturing a metal silicide for contact of a semiconductor device, and it is excellent in step coverage and can easily cope with the miniaturization of the device, and requires an additional patterning process. It is an object of the present invention to provide a simplified method for forming a contact of a semiconductor device, which can eliminate a metal thin film removing process such as the salicide method and a problem of leakage current.
또한, 본 발명의 다른 목적은 상기 반도체 소자의 콘택트용 금속 실리사이드 제조방법에 적용될 수 있는 전이금속 박막의 형성방법을 제공하는 것이다.In addition, another object of the present invention is to provide a method for forming a transition metal thin film that can be applied to the method for producing a metal silicide for contact of the semiconductor device.
상기 과제를 해결하기 위한 수단으로서 본 발명은, 소스, 드레인, 게이트 및 상기 게이트의 양측에 형성되는 스페이서를 구비한 반도체 소자의 콘택트 형성방법으로, 상기 스페이서에 선택적으로 결합하는 자기조립 단분자막을 상기 반도체 소자에 도포하여 상기 스페이서의 표면을 개질하는 단계; 원자층 증착법을 통해 상기 표면이 개질된 부분을 제외한 상기 반도체 소자의 표면에 금속 박막을 형성하는 단계; 및 금속 박막을 열처리하여, 실리사이드를 형성하고 상기 자기조립 단분자막을 분해하여 제거하는 단계;를 포함하는 방법을 제공한다.As a means for solving the above problems, the present invention provides a contact forming method of a semiconductor device having a source, a drain, a gate and a spacer formed on both sides of the gate, wherein the semiconductor is a self-assembled monomolecular film selectively coupled to the spacer. Applying to the device to modify the surface of the spacer; Forming a metal thin film on the surface of the semiconductor device except for the portion where the surface is modified by atomic layer deposition; And heat treating the metal thin film to form silicide and decompose and remove the self-assembled monomolecular film.
또한, 본 발명에 따른 콘택트 형성방법은 다양한 반도체 소자에 적용될 수 있으며, 특히 MOSFET 소자의 콘택트 형성에 적합하다. In addition, the contact forming method according to the present invention can be applied to various semiconductor devices, and is particularly suitable for forming contacts of MOSFET devices.
또한, 본 발명에 따른 콘택트 형성방법에 있어서, 상기 자기조립 단분자막은 그 반응기가 산소, 수소, 질소 또는 불소를 포함하는 기판에 결합될 수 있는 것이면 어느 것이 사용될 수 있으며, MOSFET 소자의 경우, 특히 산화물에 결합될 수 있는 것이 바람직하다. In addition, in the method for forming a contact according to the present invention, any one of the self-assembled monolayers can be used as long as the reactor can be bonded to a substrate containing oxygen, hydrogen, nitrogen or fluorine. It is desirable to be able to bind to.
또한, 본 발명에 따른 콘택트 형성방법에 있어서, 원자층증착법 중 PE-ALD(Plasma Enhanced Atomic Layer Deposition)의 경우 플라즈마에 의해 자기조립 단분자막의 표면이 손상될 수 있어 선택성이 떨어질 수 있으므로, 열적 원자층증착법(thermal ALD)을 사용하는 것이 바람직하다.In addition, in the method for forming a contact according to the present invention, in the case of the plasma enhanced atomic layer deposition (PE-ALD) in the atomic layer deposition method, the surface of the self-assembled monolayer may be damaged by plasma and thus the selectivity may be deteriorated. Preference is given to using thermal ALD.
또한, 본 발명에 따른 콘택트 형성방법에 있어서, 상기 자기조립 단분자막은 다양한 종류의 것이 사용될 수 있으나, MOSFET 소자의 경우 산화물에의 선택성이 우수한 OTS는 그 바람직한 예이다.In addition, in the contact forming method according to the present invention, various kinds of the self-assembled monolayer may be used. However, in the case of MOSFET devices, OTS having excellent selectivity to oxide is a preferable example.
또한, 본 발명에 따른 콘택트 형성방법에 있어서, 상기 금속 박막은 전이금속으로 이루어지는 것이 바람직하며, 코발트, 니켈 또는 이의 합금으로 이루어진 것이 보다 바람직하다.In addition, in the contact forming method according to the present invention, the metal thin film is preferably made of a transition metal, more preferably made of cobalt, nickel or an alloy thereof.
또한, 본 발명에 따른 콘택트 형성방법에 있어서, 상기 금속 박막은, 전이금속 전구체를 투입하는 단계; 퍼징가스를 투입하여 미흡착물을 제거하는 단계; 암모니아를 투입하여 전이금속을 형성하는 단계; 및 및 퍼징가스를 투입하여 반응 잔류물을 제거하는 단계;로 이루어진 사이클을 반복 수행함으로써 형성되는 것을 특징으로 한다.In addition, in the contact forming method according to the invention, the metal thin film, the step of introducing a transition metal precursor; Inputting a purging gas to remove unadsorbed substances; Adding ammonia to form a transition metal; And removing a reaction residue by inputting a purging gas.
또한, 본 발명은 상기 다른 목적을 달성하기 위해, 전이금속 전구체를 투입 하는 단계; 퍼징가스를 투입하여 미흡착물을 제거하는 단계; 암모니아 가스를 투입하여 전이금속을 형성하는 단계; 및 퍼징가스를 투입하여 반응 잔류물을 제거하는 단계;로 이루어진 사이클을 반복 수행하는 것을 특징으로 하는 전이금속의 박막 형성방법을 제공한다.In addition, the present invention, to achieve the above another object, the step of introducing a transition metal precursor; Inputting a purging gas to remove unadsorbed substances; Adding ammonia gas to form a transition metal; And adding a purging gas to remove the reaction residues. The method provides a method for forming a thin film of transition metal, characterized by repeatedly performing a cycle.
본 발명에 따른 반도체 소자의 금속 실리사이드 콘택트 형성방법은 특정 표면에만 반응하는 자기조립 단분자막을 이용하여 반도체 소자 중에서 실리사이드를 형성하지 않는 표면만을 선택적으로 개질한 후에, 금속 박막을 증착하고 열처리만 하면 되기 때문에, 후속 에칭 공정이 필요 없게 되어 종래에 비해 공정이 간소화된다.In the method for forming a metal silicide contact of a semiconductor device according to the present invention, since only a surface of the semiconductor device which does not form silicide is selectively modified using a self-assembled monolayer that reacts only on a specific surface, a metal thin film may be deposited and heat treated. There is no need for a subsequent etching process, which simplifies the process as compared with the prior art.
또한, 본 발명에 따른 콘택트 형성방법은, 실리사이드 형성을 위한 열처리시에 자기조립 단분자막을 열분해하여 제거하기 때문에, 샐리사이드법의 누설전류 발생의 문제가 해결된다.Further, the contact forming method according to the present invention eliminates the self-assembled monomolecular film by thermal decomposition during heat treatment for silicide formation, thereby solving the problem of leakage current generation in the salicide method.
또한, 본 발명에 따른 콘택트 형성방법은, 금속 박막의 형성에 원자층 증착법을 사용하기 때문에 단차 피복성이 우수하다.In addition, the contact forming method according to the present invention is excellent in step coverage because the atomic layer deposition method is used to form the metal thin film.
또한, 본 발명은 종래 원자층 증착법으로 구현하기 어려웠던 전이금속 박막을 원자층 증착법을 통해 형성할 수 있어, 우수한 단차 피복성이 요구되는 박막의 형성에 용이하게 대응할 수 있다.In addition, the present invention can form a transition metal thin film, which has been difficult to implement in the conventional atomic layer deposition method through the atomic layer deposition method, it can easily cope with the formation of a thin film requiring excellent step coverage.
이하 첨부된 도면들을 참조하여 본 발명을 구체적으로 설명하나, 본 발명이 하기 설명에 의해 제한되는 것은 아니다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited by the following description.
본 발명의 실시예에서는 먼저 원자층 증착 공정을 통해 전이금속 실리사이드를 얻을 수 있는지를 체크하고, 자기조립 단분자막을 통한 선택적 증착이 가능한지 여부를 확인하였다.In the embodiment of the present invention, first, it is checked whether a transition metal silicide can be obtained through an atomic layer deposition process, and it is confirmed whether selective deposition through a self-assembled monolayer is possible.
전이금속 실리사이드 박막의 형성Formation of Transition Metal Silicide Thin Film
본 발명의 실시예에서 수행한 원자층 증착 공정은 실리콘 기판상에 코발트와 니켈을 증착하였으며, 기본적인 ALD공정은 4개의 단계로 이루어진 한 사이클을 기본으로 특정 사이클 동안 반복되어 진행된다. 상기 4개의 단계는 도 1에 도시된 바와 같이, 금속 전구체 투여, 알곤 가스 퍼지 (purge), 암모니아 가스 투여, 알곤 가스 퍼지 (purge)로 이루어진다.In the atomic layer deposition process performed in the embodiment of the present invention, cobalt and nickel were deposited on the silicon substrate, and the basic ALD process was repeated for a specific cycle based on one cycle consisting of four steps. The four steps consist of metal precursor administration, argon gas purge, ammonia gas administration and argon gas purge, as shown in FIG.
금속 전구체로는 코발트의 경우, bis(N,N'-diisopropylacetamidinato) cobalt(II)를 사용하였으며, 니켈은 bis(dimethylamino-2-methyl-2-butoxo)nickel을 사용하였다. 금속 전구체는 적당한 증기압을 얻기 위해 가열되어, 50 sccm의 알곤 캐리어 가스를 사용하여 3초 동안 투여해주었다. 알곤 퍼지는 1초간 실시하였으며, 암모니아 가스는 400 sccm의 양으로 1초간 투여해주었다. 증착 온도는 코발트의 경우 350℃로 하였고, 니켈은 300℃로 하였다. 코발트와 니켈의 원자층 증착시 전구체와 증착 온도를 제외한 다른 공정 조건은 변화시키지 않았다.As the metal precursor, bis (N, N'-diisopropylacetamidinato) cobalt (II) was used for cobalt, and bis (dimethylamino-2-methyl-2-butoxo) nickel was used for nickel. The metal precursor was heated to obtain the appropriate vapor pressure and administered for 3 seconds using an argon carrier gas of 50 sccm. Argon purge was performed for 1 second, and ammonia gas was administered for 1 second in an amount of 400 sccm. The deposition temperature was 350 ° C. for cobalt and 300 ° C. for nickel. The atomic layer deposition of cobalt and nickel did not change the process conditions except for the precursor and deposition temperature.
이와 같이 증착된 코발트 박막을 통해 코발트 실리사이드가 형성되는 것을 확인하기 위해, 코발트 박막 상에 타이타늄(Ti) 산화 방지막을 입힌 뒤에, 여러 온도범위에서 열처리를 하였다.In order to confirm that cobalt silicide is formed through the cobalt thin film deposited as described above, a titanium (Ti) anti-oxidation film was coated on the cobalt thin film, and then heat-treated at various temperature ranges.
도 2는 열처리한 뒤, 측정한 방사광 가속기 엑스레이 회절 피크의 결과이다. 도 2에서 확인되는 바와 같이, 열처리 온도 700℃ 이상에서부터 CoSi2 회절 피크가 관찰되었다. 따라서, Co ALD공정에 의해 증착된 코발트 박막으로부터 코발트 실리사이드를 얻을 수 있었다.Figure 2 is the result of the emission accelerator x-ray diffraction peak measured after the heat treatment. As confirmed in FIG. 2, CoSi 2 diffraction peaks were observed from the heat treatment temperature of 700 ° C. or higher. Therefore, cobalt silicide was obtained from the cobalt thin film deposited by the Co ALD process.
선택적 원자층 증착공정(Selective atomic layer deposition process AreaArea SelectiveSelective AtomicAtomic LayerLayer DepositionDeposition ))
자기조립 단분자막은 주어진 기질의 표면과 반응하여 자발적으로 규칙적으로 정렬되게 형성되는 유기 분자막으로, 기질과 결합하는 머리 부분의 반응기, 규칙적인 분자 막 형성을 가능하게 하는 몸통 부분의 긴 알칸 사슬, 그리고 형성된 유기 분자막의 기능을 좌우하는 꼬리 부분의 작용기로 나누어진다. 상기 작용기를 통해 다양한 표면 특성을 부여할 수 있다.Self-assembled monomolecular membranes are organic molecular membranes that form spontaneously and regularly aligned in response to the surface of a given substrate, including reactors in the head that bind to the substrate, long alkane chains in the body that enable regular molecular membrane formation, and It is divided into functional groups in the tail part that influence the function of the formed organic molecular membrane. The functional group can impart various surface properties.
본 발명의 실시예에서는 상기 자기조립 단분자막을 OTS (Octadecyltri chlorosilane) 기반 자기조립 단분자로 형성한다. 상기 OTS의 반응기는 산화막과 용이하게 반응하여 산화막 상에 단분자막을 용이하게 형성하게 하며, 분자막의 특성을 좌우하는 작용기는 CH3기로 되어 있어 분자막의 표면이 소수성 (hydrophobicity)을 갖도록 한다.In an embodiment of the present invention, the self-assembled monolayer is formed of OTS (Octadecyltri chlorosilane) based self-assembled single molecule. The OTS reactor easily reacts with the oxide film to easily form a monomolecular film on the oxide film, and the functional group that determines the properties of the molecular film is CH 3 group so that the surface of the molecular film has hydrophobicity.
자기조립 단분자막의 제조는 도 3에 도시된 바와 같은 공정 순서에 따라 수 행하였다.Preparation of the self-assembled monolayer was carried out according to the process sequence as shown in FIG.
먼저, 산화실리콘이 형성된 실리콘 기판 위에 사진 리소그라피방법을 이용하여 포토 레지스트(Photoresist; PR)를 패터닝 하였다. 패터닝된 기판은 OTS가 희석된 용액에 침지시켜 포토 레지스트가 피복되지 않은 산화 실리콘 위에서만 코팅이 이루어지도록 했다. 코팅 후, 포토 레지스트를 제거하게 되면 국부적으로 OTS가 코팅된 기판을 얻을 수 있다.First, a photoresist (PR) was patterned on a silicon substrate on which silicon oxide was formed using a photolithography method. The patterned substrate was immersed in a solution diluted with OTS so that the coating was only on silicon oxide that was not coated with photoresist. After coating, the photoresist is removed to obtain a substrate coated with OTS locally.
이 기판을 사용하여 상기한 원자층 증착공정을 통해 코발트 및 니켈을 증착하였다.This substrate was used to deposit cobalt and nickel through the atomic layer deposition process described above.
이와 같이 증착된 코발트 박막은 도 4의 AFM (atomic force microscopy)결과에서 확인할 수 있듯이, 포토 레지스트가 존재했던 부분 (넓이 3 μm의 라인 패턴) 위에서는 코발트가 증착되었으며, 포토 레지스트가 존재하지 않아 OTS가 코팅되어 있는 부분에는 코발트가 증착되지 않았다.As shown in the atomic force microscopy (AFM) result of FIG. 4, the cobalt thin film deposited as described above was cobalt deposited on the portion where the photoresist existed (a line pattern of 3 μm in width), and the photoresist did not exist. Cobalt was not deposited on the coated portion.
도 5는 각각의 코발트 라인의 전류 측정 결과이다. 하나의 코발트 라인을 택하여 전류를 흘리거나, 서로 다른 두 개의 코발트 라인을 택하여 전류를 흘려본 결과, 같은 라인 위에서는 전류가 흐르지만, 서로 다른 코발트 라인에서는 전류가 흐르지 않았다. 따라서 각각의 코발트 라인은 전기적으로 절연되어 있으며, 이것은 코발트가 완벽하게 선택적으로 포토 레지스트가 존재한 부분에만 증착되었음을 말해 준다.5 is a result of measuring current of each cobalt line. When one cobalt line is used to flow current, or two different cobalt lines are used to flow current, current flows on the same line, but no current flows on different cobalt lines. Thus, each cobalt line is electrically insulated, which indicates that cobalt is deposited only where the photoresist is completely selective.
같은 방법으로 니켈에 대해 적용한 결과, 도 6에 나타난 바와 같이, OTS가 코팅되지 않은 부분에만 니켈 라인이 증착되었으며, 도 7에서 확인되는 바와 같이, 각각의 니켈 라인은 전기적으로 절연되어 완벽한 선택적 증착이 이루어졌음을 확인할 수 있다.As applied to nickel in the same manner, as shown in FIG. 6, nickel lines were deposited only on the portion not coated with OTS, and as shown in FIG. 7, each nickel line was electrically insulated to provide a perfect selective deposition. You can see that it was done.
즉, 본 발명의 실시예에 따른 증착방법을 통해, 코발트나 니켈과 같은 전이금속을 원자층 증착공정을 통해 선택적으로 증착을 할 수 있음을 알 수 있다.That is, it can be seen that through the deposition method according to the embodiment of the present invention, a transition metal such as cobalt or nickel may be selectively deposited through an atomic layer deposition process.
MOSFETMOSFET 콘택트 제조공정 Contact manufacturing process
상기한 선택적 원자층 증착공정은 금속산화물 반도체 트랜지스터(MOSFET) 소자의 콘택트 제조에 적용할 경우 종래의 콘택트 제조 공정을 간소화할 있을 뿐 아니라, 신뢰성도 개선할 수 있다.The selective atomic layer deposition process described above can simplify not only the conventional contact manufacturing process but also the reliability when applied to contact manufacturing of a metal oxide semiconductor transistor (MOSFET) device.
MOSFET 소자의 게이트 양 옆에 배치된 스페이서는 통상 산화 실리콘으로 이루어져 있음에 반해, 소스, 드레인 및 게이트 영역은 실리콘으로 이루어져 있다. 따라서 산화물에만 선택적으로 결합하는 반응기를 갖는 OTS의 희석용액을 통해 코팅을 하게 되면, 도 8에 도시된 바와 같이, 산화 실리콘으로 이루어진 스페이서 부분에만 자기조립 단분자막이 형성되고, 이 막의 표면은 소수성을 띠게 된다.The spacers disposed next to the gate of the MOSFET device are usually made of silicon oxide, whereas the source, drain and gate regions are made of silicon. Therefore, when coating through the dilution solution of OTS having a reactor that selectively binds only to the oxide, as shown in Figure 8, the self-assembled monomolecular film is formed only in the spacer portion made of silicon oxide, the surface of the film is hydrophobic do.
이와 같이 소수성을 띠는 막의 표면에는 코발트나 니켈을 원자층 증착법으로 증착을 하게 되면, 상기 도 4 및 6에서 확인한 바와 같이, 자기조립 단분자막이 코팅되지 않은 실리콘으로 이루어진 소스, 드레인 및 게이트 영역에만 금속 박막이 형성된다.When the cobalt or nickel is deposited on the surface of the hydrophobic film by the atomic layer deposition method, as shown in FIGS. 4 and 6, only the source, drain, and gate regions of the silicon, which are not coated with the self-assembled monolayer, are metal. A thin film is formed.
따라서, 이 반도체 소자를 열처리하게 되면, 금속 박막이 형성된 부분은 실리사이드로 되고, 스페이서 부분에 코팅된 자기조립 유기막은 열분해되어 제거된 다.Therefore, when the semiconductor element is heat-treated, the portion where the metal thin film is formed becomes silicide, and the self-assembled organic film coated on the spacer portion is thermally decomposed and removed.
이러한 과정을 통해, 후속 에칭 공정 없이 선택적으로 형성되는 콘택트 구조를 얻을 수 있게 되며, 샐리사이드법에서 금속 박막의 불완전한 제거에 따른 누설전류의 발생 문제도 제거할 수 있게 된다.Through this process, it is possible to obtain a contact structure that is selectively formed without a subsequent etching process, it is possible to eliminate the problem of the leakage current caused by the incomplete removal of the metal thin film in the salicide method.
도 1은 전이금속 ALD공정의 순서도이다.1 is a flowchart of a transition metal ALD process.
도 2는 전이금속 ALD법에 의해 증착된 코발트 박막의 열처리 후, 방사광 가속기 엑스레이 회절 피크 결과이다.Figure 2 is a result of the radiation accelerator x-ray diffraction peak after heat treatment of the cobalt thin film deposited by the transition metal ALD method.
도 3은 자기조립 단분자막을 이용한 선택 증착 방법의 순서도이다.3 is a flowchart of a selective deposition method using a self-assembled monolayer.
도 4는 도 3의 자기조립 단분자막을 이용한 선택 증착 방법을 사용하여 증착된 코발트 라인 패턴의 AFM 결과이다.4 is an AFM result of a cobalt line pattern deposited using the selective deposition method using the self-assembled monolayer of FIG. 3.
도 5는 자기조립 단분자막을 이용한 선택 증착 방법을 사용하여 증착된 코발트 라인 패턴의 전류 측정 결과이다.5 is a current measurement result of a cobalt line pattern deposited using a selective deposition method using a self-assembled monolayer.
도 6은 자기조립 단분자막을 이용한 선택 증착 방법을 사용하여 증착된 니켈 라인 패턴의 AFM 결과이다.6 is an AFM result of a nickel line pattern deposited using a selective deposition method using a self-assembled monolayer.
도 7 자기조립 단분자막을 이용한 선택 증착 방법을 사용하여 증착된 니켈 라인 패턴의 전류 측정 결과이다.7 shows current measurement results of nickel line patterns deposited using a selective deposition method using self-assembled monolayers.
도 8은 자기조립 단분자막을 이용한 선택 증착 방법을 MOSFET 콘택트 형성 공정에 이용하기 위한 방법을 표시한 순서도이다.8 is a flowchart showing a method for using a selective deposition method using a self-assembled monomolecular film in a MOSFET contact formation process.
도 9는 종래의 샐리사이드법에 의해 콘택트를 형성하는 방법을 나타낸 순서도이다.9 is a flowchart showing a method of forming a contact by a conventional salicide method.
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