KR101059629B1 - Semiconductor Package Manufacturing Method - Google Patents

Semiconductor Package Manufacturing Method Download PDF

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KR101059629B1
KR101059629B1 KR1020090133354A KR20090133354A KR101059629B1 KR 101059629 B1 KR101059629 B1 KR 101059629B1 KR 1020090133354 A KR1020090133354 A KR 1020090133354A KR 20090133354 A KR20090133354 A KR 20090133354A KR 101059629 B1 KR101059629 B1 KR 101059629B1
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semiconductor chip
substrate
redistribution circuit
forming
via hole
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KR1020090133354A
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Korean (ko)
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KR20110076606A (en
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정진욱
강남규
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하나 마이크론(주)
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

반도체 패키지 제조방법을 제공한다. A semiconductor package manufacturing method is provided.

본 발명은 기판을 준비하는 단계 ; 상기 기판상에 반도체 칩을 다이본딩하는 단계; 상기 반도체 칩의 상부면에 형성된 다이패드를 외부노출시키면서 상기 반도체 칩을 보호하도록 에워싸는 보호부를 형성하도록 1차 인캡슐레이션하는 단계 ; 상기 다이패드와 전기적으로 연결되도록 상기 보호부의 상부면에 재배선회로를 형성하는 단계 ; 상기 기판에 형성된 연결패드가 외부노출되도록 상기 보호부에 비어홀을 형성하는 단계; 상기 재배선회로와 기판이 전기적으로 연결되도록 도전성 페이스트로서 상기 비어홀을 충진하는 단계 ; 상기 재배선회로와 반도체 칩의 상부면을 덮어 보호하는 보호층을 형성하도록 2차 인캡슐레이션하는 단계를 포함한다. The present invention comprises the steps of preparing a substrate; Die bonding a semiconductor chip onto the substrate; First encapsulating the outer surface of the die pad formed on the upper surface of the semiconductor chip to form a protection portion surrounding the semiconductor chip; Forming a redistribution circuit on an upper surface of the protection part to be electrically connected to the die pad; Forming a via hole in the protective part such that a connection pad formed on the substrate is exposed to the outside; Filling the via hole with a conductive paste to electrically connect the redistribution circuit and the substrate; And encapsulating a second layer to form a protective layer covering the redistribution circuit and the upper surface of the semiconductor chip.

반도체, 패키지, 다이패드, 기판, 연결패드, 보호부, 재배선회로, 보호층, 인캡슐레이션 Semiconductor, Package, Die Pad, Board, Connection Pad, Protection, Rewiring Circuit, Protection Layer, Encapsulation

Description

반도체 패키지 제조방법{Method For Fabricating Semiconductor Package} Manufacturing Method for Semiconductor Package {Method For Fabricating Semiconductor Package}

본 발명은 반도체 패키지를 제조하는 방법에 관한 것으로, 더욱 상세히는 와이어본딩 공정의 필요없이 반도체 칩을 기판상에 실장하면서 반도체 패키지의 높이를 줄여 반도체 패키지 제품의 박형화 및 소형화를 도모하고, 반도체 칩의 외부로 회로를 재배선하여 외부와 연결되는 본딩패드의 집적화율을 높일 수 있는 반도체 패키지 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to reduce the height of the semiconductor package while mounting the semiconductor chip on a substrate without the need for a wire bonding process, and to reduce the size and size of the semiconductor package product, The present invention relates to a semiconductor package manufacturing method capable of increasing the integration rate of a bonding pad connected to the outside by rewiring a circuit to the outside.

일반적으로 반도체 패키지는 각종 전자 회로 및 배선이 형성된 단일 소자, 집적 회로, 또는 하이브리드 회로 등과 같은 반도체 칩을 패키지의 캐비티내에 적어도 하나 이상 패키징함으로써, 주변의 가스, 온도 및 습도 등을 포함하는 외부환경에 민감하게 반응하는 반도체 칩이 보다 안정적으로 작동되도록 외부환경과 반도체칩을 서로 격리시킴과 동시에 제품의 소형화에 맞추어 패키지를 칩사이즈로 구성하는 것이다. In general, a semiconductor package is packaged with at least one semiconductor chip such as a single device, an integrated circuit, or a hybrid circuit formed with various electronic circuits and wirings in the cavity of the package, so that the semiconductor package can be used in an external environment including surrounding gas, temperature, and humidity. In order to operate the sensitive semiconductor chip more stably, the external environment and the semiconductor chip are isolated from each other and the package is configured in the chip size according to the miniaturization of the product.

이러한 반도체 패키지를 제조하는 기술 중 기판상에 반도체 칩을 탑재한 다음 상기 기판에 형성된 패턴회로와 반도체 칩의 입출력 패드사이를 전기적으로 연 결하는 와이어부재를 매개로 와이어본딩하여 패키징하는 기술이 개시되어 있다. Among technologies for manufacturing a semiconductor package, a technology is disclosed in which a semiconductor chip is mounted on a substrate, and then wire-bonded and packaged through a wire member that electrically connects a pattern circuit formed on the substrate and an input / output pad of the semiconductor chip. .

그러나 이러한 와이어 본딩방식을 채용하는 반도체 패키지 제조공정에서 와이이어부재는 일정한 루프를 형성해야 하고 몰딩부를 형성하기 위한 성형시 주입되는 에폭시몰드컴파운드에 의하여 와이어부재가 휘어지는 것을 예방하기 위하여 반도체 패키지는 추가적인 높이를 유지해야만 하기 때문에 반도체 패키지의 전체두께가 커져 전체 부피를 줄여 소형화하는데 제한적인 요소로 작용하였다. However, in the semiconductor package manufacturing process employing such a wire bonding method, the wire member must form a constant loop, and the semiconductor package has an additional height to prevent the wire member from being bent by the epoxy mold compound injected during molding to form the molding part. Since the overall thickness of the semiconductor package has to be maintained, it is a limiting factor in miniaturization by reducing the overall volume.

또한, 상기 반도체 칩과 기판을 와아이본딩하는 와이어부재를 사용하는 경우, 상기 와이어의 단부가 본딩되는 본딩패드의 피치가 충분히 넓게 확보되어야 하기 때문에 반도체 칩의 제한된 외부영역에서 본딩패드의 설치개수를 늘리지 못하는 원인이 되었다. In addition, in the case of using the wire member for back-ibonding the semiconductor chip and the substrate, the pitch of the bonding pad to which the end of the wire is bonded should be secured sufficiently wide so as to increase the number of installation of the bonding pad in the limited external area of the semiconductor chip. It did not cause.

최근들어 전자기기의 박형화·소형화 추세에 따라 반도체 소자를 탑재하는 패키징(packaging)기술도 고속, 고기능, 고밀도 실장이 요구되며, 이러한 요구에 부응하여 칩 스케일 패키지 형태의 플립칩 실장 기술이 등장하게 되었다. Recently, in accordance with the trend of thinning and miniaturization of electronic devices, packaging technology for mounting semiconductor devices also requires high-speed, high-performance, high-density mounting, and in response to this demand, chip-chip package flip chip mounting technology has emerged. .

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 그 목적은 와이어본딩 공정의 필요없이 반도체 칩을 기판상에 실장하면서 반도체 패키지의 높이를 줄여 반도체 패키지 제품의 박형화 및 소형화를 도모하고, 반도체 칩의 외부로 회로를 재배선하여 외부와 연결되는 본딩패드의 집적화율을 높일 수 있는 반도체 패키지 제조방법을 제공하고자 한다. Accordingly, the present invention is to solve the above problems, the object of the present invention is to reduce the height of the semiconductor package while mounting the semiconductor chip on the substrate without the need for a wire bonding process to reduce the size and size of the semiconductor package product, the semiconductor The present invention provides a method of manufacturing a semiconductor package capable of increasing the integration rate of a bonding pad connected to the outside by rewiring a circuit to an outside of the chip.

상기와 같은 목적을 달성하기 위한 구체적인 수단으로서, 본 발명은 기판을 준비하는 단계 ; 상기 기판상에 반도체 칩을 다이본딩하는 단계; 상기 반도체 칩의 상부면에 형성된 다이패드를 외부노출시키면서 상기 반도체 칩을 보호하도록 에워싸는 보호부를 형성하도록 1차 인캡슐레이션하는 단계 ; 상기 다이패드와 전기적으로 연결되도록 상기 보호부의 상부면에 재배선회로를 형성하는 단계 ; 상기 기판에 형성된 연결패드가 외부노출되도록 상기 보호부에 비어홀을 형성하는 단계; 상기 재배선회로와 기판이 전기적으로 연결되도록 도전성 페이스트로서 상기 비어홀을 충진하는 단계 ; 상기 재배선회로와 반도체 칩의 상부면을 덮어 보호하는 보호층을 형성하도록 2차 인캡슐레이션하는 단계를 포함하는 반도체 패키지 제조방법을 제공한다. As a specific means for achieving the above object, the present invention comprises the steps of preparing a substrate; Die bonding a semiconductor chip onto the substrate; First encapsulating the outer surface of the die pad formed on the upper surface of the semiconductor chip to form a protection portion surrounding the semiconductor chip; Forming a redistribution circuit on an upper surface of the protection part to be electrically connected to the die pad; Forming a via hole in the protective part such that a connection pad formed on the substrate is exposed to the outside; Filling the via hole with a conductive paste to electrically connect the redistribution circuit and the substrate; It provides a method of manufacturing a semiconductor package comprising a second encapsulation to form a protective layer covering the redistribution circuit and the upper surface of the semiconductor chip.

바람직하게, 상기 비어홀을 형성하는 단계 이전에 상기 재배선회로상에 솔더 레지스트인 절연층을 도포하고, 패턴대로 식각하여 상부 재배선 회로를 형성하 는 단계를 추가 포함한다. The method may further include applying an insulating layer, which is a solder resist, on the redistribution circuit and forming the upper redistribution circuit by etching the pattern before forming the via hole.

바람직하게, 상기 비어홀을 형성하는 단계이전에 상기 반도체 칩상에 접착제를 매개로 상부 반도체 칩을 다이본딩하고, 상기 반도체 칩의 다이패드가 외부로 노출되면서 상기 상부 반도체 칩을 감싸도록 상부 보호부를 형성하고, 상기 다이패드와 전기적으로 연결되는 상부 재배선회로를 형성하며, 상기 기판의 연결패드가 외부노출되도록 상기 재배선회로 및 상부 재배선회로와 대응하는 보호부에 일정깊이의 비어홀을 형성하고, 상기 비어홀에 도전성 페이스트를 충진하여 도전성 비어홀을 형성한 다음, 상기 상부 반도체 칩과 상부 재배선회로를 덮도록 보호층을 형성한다. Preferably, prior to forming the via hole, the upper semiconductor chip is die-bonded on the semiconductor chip through an adhesive, and the upper protection part is formed to surround the upper semiconductor chip while the die pad of the semiconductor chip is exposed to the outside. And forming an upper redistribution circuit electrically connected to the die pad, and forming a via hole having a predetermined depth in a protective part corresponding to the redistribution circuit and the upper redistribution circuit so that the connection pad of the substrate is exposed to the outside. A conductive paste is formed by filling a conductive hole in the via hole, and then a protective layer is formed to cover the upper semiconductor chip and the upper redistribution circuit.

바람직하게, 상기 1차 인캡슐레이션하는 단계는 상,하부 금형사이에 반도체 칩이 탑재된 기판을 고정배치한 다음 수지재를 주입하는 성형방식으로 성형하거나 절연성 필름을 기판상에 부착하는 방식으로 형성한다. Preferably, the first encapsulation step is formed by a method of fixing a substrate on which a semiconductor chip is mounted between upper and lower molds and then molding a molding method injecting a resin material or attaching an insulating film on the substrate. do.

바람직하게, 상기 2차 인캡슐레이션 하는 단계는 상,하부 금형사이에 반도체 칩이 탑재된 기판을 고정배치한 다음 수지재를 주입하는 성형방식으로 성형하거나 절연성 또는 내열성 필름을 상기 재배선회로와 보호부상에 부착하는 방식으로 형성한다. Preferably, the second encapsulation may include forming a substrate in which a semiconductor chip is mounted between upper and lower molds and then molding a molding method injecting a resin material or protecting an insulating or heat resistant film from the redistribution circuit. Form by attaching to a wound.

본 발명에 의하면, 기판상에 다이본딩된 반도체 칩을 감싸도록 형성되는 보호부의 상부면에 재배선회로를 패턴인쇄하고, 보호부에 형성되는 도전성 비어홀을 매개로 재배선회로와 연결패드를 서로 전기적으로 연결한 다음 반도체 칩상에 보호 층을 형성함으로써 와이어본딩 공정의 필요없이 반도체 칩의 다이패드와 기판의 연결패드를 서로 전기적으로 연결할 수 있기 때문에 반도체 패키지의 전체높이를 줄여 패키지 제품의 박형화 및 소형화 설계가 가능해지고, 반도체 칩의 외부로 회로를 재배선하여 외부와 연결되는 본딩패드의 집적화율을 높일 수 있는 한편 와이어 본딩방식으로 구현이 불가능한 패키지 구조도 설계가능하여 패키지 설계자유도를 높일 수 있는 효과가 얻어진다. According to the present invention, the redistribution circuit is pattern-printed on the upper surface of the protection part formed to surround the die-bonded semiconductor chip on the substrate, and the redistribution circuit and the connection pad are electrically connected to each other via the conductive via hole formed in the protection part. After forming the protective layer on the semiconductor chip, the die pad of the semiconductor chip and the connection pad of the board can be electrically connected to each other without the need for wire bonding process. Therefore, the overall height of the semiconductor package is reduced, thereby making the package product thinner and smaller. It is possible to increase the integration rate of the bonding pads connected to the outside by rewiring the circuit to the outside of the semiconductor chip, and also to design a package structure that cannot be implemented by wire bonding, thereby increasing the degree of freedom of package design. Obtained.

이하 본 발명의 바람직한 실시 예에 대해 첨부된 도면에 따라 더욱 상세히 설명한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 실시 예에 따른 반도체 패키지 제조방법에 의해서 제조되는 반도체 패키지를 도시한 종단면도이고, 도 2는 본 발명의 실시 예에 따른 반도체 패키지 제조방법을 도시한 공정 순서도이며, 도 3(a) 내지 도 3(g)는 본 발명의 실시 예에 따른 반도체 패키지 제조방법을 도시한 공정 흐름도이다. 1 is a longitudinal cross-sectional view illustrating a semiconductor package manufactured by a semiconductor package manufacturing method according to an embodiment of the present invention, FIG. 2 is a process flowchart illustrating a semiconductor package manufacturing method according to an embodiment of the present invention, and FIG. 3. 3A to 3G are process flowcharts illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

본 발명의 실시 예에 따른 반도체 패키지 제조방법은 도 1 내지 도 3(g)에 도시한 바와 같이, 기판을 준비하는 단계(S201), 반도체 칩을 다이본딩하는 단계(S202), 1차 인캡슐레이션하는 단계(S203), 재배선회로를 형성하는 단계(S204) , 비어홀을 형성하는 단계(S205), 비어홀을 충진하는 단계(S206) 및 2차 인캡슐레이션하는 단계(S207)을 포함하여 두께가 얇으면서 외부연결용 핀부의 집적율을 높일 수 있는 반도체 패키지(100)를 제조완성하는 것이다. In the method of manufacturing a semiconductor package according to an embodiment of the present invention, as shown in FIGS. 1 to 3 (g), a step of preparing a substrate (S201), a die bonding step of a semiconductor chip (S202), and a primary encapsulation Thickness (S203), forming a redistribution circuit (S204), forming a via hole (S205), filling a via hole (S206), and performing a second encapsulation step (S207). To manufacture a semiconductor package 100 that is thin and can increase the integration rate of the pin portion for external connection.

상기 기판(110)을 준비하는 단계(S201)는 도 3(a)에 도시한 바와 같이, 패턴회로가 인쇄되고, 상부면에 형성된 연결패드(114)와 하부면에 형성된 외부단자(116)사이를 연결하는 복수개의 비어홀(118)을 구비하는 웨이퍼(112)를 제공하는 것이다In the preparing of the substrate 110 (S201), as shown in FIG. 3A, a pattern circuit is printed, and is connected between a connection pad 114 formed on an upper surface and an external terminal 116 formed on a lower surface. It is to provide a wafer 112 having a plurality of via holes 118 for connecting the

. .

상기 반도체 칩(120)을 다이본딩하는 단계(S202)는 도 3(a)에 도시한 바와 같이 상부면에 복수개의 다이패드(122)를 갖는 반도체 칩(120)을 상기 기판(110)의 상부면에 에폭시 또는 접착필름과 같은 접착제(124)를 매개로 접합고정하여 다이본딩하는 것이다. Die bonding the semiconductor chip 120 (S202) includes a semiconductor chip 120 having a plurality of die pads 122 formed on an upper surface of the substrate 110, as shown in FIG. 3A. Bonding is fixed by bonding the adhesive 124, such as epoxy or an adhesive film on the surface.

상기 1차 인캡슐레이션하는 단계(S203)는 도 3(b)에 도시한 바와 같이, 상기 반도체 칩(120)이 다이본딩된 기판(110)의 상부면에 형성된 연결패드(114)를 덮으면서 상기 반도체 칩(120)에 형성된 다이패드(122)를 외부로 노출시키도록 상기 반도체 칩(120)의 외부를 감싸는 보호부(130)를 절연성 수지재로 형성하는 것이다. In the first encapsulation step (S203), as shown in FIG. 3B, the semiconductor chip 120 covers the connection pad 114 formed on the upper surface of the die-bonded substrate 110. The protective part 130 surrounding the outside of the semiconductor chip 120 is formed of an insulating resin material so as to expose the die pad 122 formed on the semiconductor chip 120 to the outside.

이러한 보호부(130)는 상,하부 금형사이에 반도체 칩이 탑재된 기판을 고정배치한 다음 수지재를 주입하는 성형방식으로 성형하거나 절연성 필름을 기판상에 부착하는 방식으로 형성할 수 있지만 이에 한정되는 것은 아니며, 절연성 수지재를 이용하여 다양한 방법으로 형성할 수 있다. The protection unit 130 may be formed by molding a substrate in which a semiconductor chip is mounted between upper and lower molds and then molding by injecting a resin material or by attaching an insulating film on the substrate. It does not become, and it can form by various methods using an insulating resin material.

상기 재배선회로를 형성하는 단계(S204)는 도 3(c)에 도시한 바와 같이, 상기 보호부(130)의 상부면에 외부노출되는 반도체 칩(120)의 다이패드(122)와 전기적으로 연결되도록 재배선회로(132, 134)를 상기 보호부(130)의 상부면에 패턴인쇄한다. The forming of the redistribution circuit (S204) is electrically performed with the die pad 122 of the semiconductor chip 120 that is externally exposed on the upper surface of the protection unit 130, as shown in FIG. 3C. The redistribution circuits 132 and 134 are pattern-printed on the upper surface of the protection unit 130 to be connected.

이러한 재배선회로(132,134)는 상기 기판(110)에 형성된 비어홀(118)과 대응하는 영역에 형성되는 것이 바람직하다. The redistribution circuits 132 and 134 may be formed in a region corresponding to the via hole 118 formed in the substrate 110.

상기 비어홀을 형성하는 단계(S205)는 도 3(d)에 도시한 바와 같이, 상기 기판(110)의 상부면에 형성된 연결패드(114)가 외부노출되도록 상기 재배선회로(132,134)와 대응하는 보호부(130)에 일정깊이의 비어홀(136)을 형성함에 따라, 상기 연결패드(114)는 상기 비어홀(36)의 바닥면에 외부노출된다.The forming of the via hole (S205) corresponds to the redistribution circuits 132 and 134 such that the connection pad 114 formed on the upper surface of the substrate 110 is externally exposed as shown in FIG. 3D. As the via hole 136 of a predetermined depth is formed in the protection unit 130, the connection pad 114 is exposed to the bottom surface of the via hole 36.

이러한 비어홀(136)은 레이저빔을 이용하는 레이저 공정 또는 기계식 드릴에 의한 드릴가공에 의해서 형성될 수 있다. The via hole 136 may be formed by a laser process using a laser beam or by drilling by a mechanical drill.

상기 비어홀을 충진하는 단계(S206)는 도 3(e)에 도시한 바와 같이, 상기 보호부(130)상에 패턴인쇄된 재배선회로(132,134)와 상기 기판(110)의 상부면에 패턴인쇄된 연결패드(114)를 서로 전기적으로 연결하도록 상기 비어홀(136)에 도전성 페이스트를 충진함으로써 상기 반도체칩(120)과 연결된 재배선회로(134)와 기판(110)을 서로 전기적으로 연결하는 도전성 비어홀(138)을 형성하게 된다. Filling the via hole (S206) is a pattern printing on the upper surface of the redistribution circuit 132, 134 and the substrate 110, the pattern printed on the protection unit 130, as shown in Figure 3e A conductive via hole for electrically connecting the redistribution circuit 134 and the substrate 110 connected to the semiconductor chip 120 to each other by filling a conductive paste into the via hole 136 to electrically connect the connected connection pads 114 to each other. And (138).

상기 2차 인캡슐레이션하는 단계(S207)는 도 3(f)에 도시한 바와 같이, 상기 재배선회로(132,134)와 반도체 칩(120)을 덮어 외부환경으로부터 보호하도록 적어도 1층이상의 보호층(140)을 형성하여 2차 인캡슐레이션하여 반도체 패키지(100)를 제조완성하게 된다. . As shown in FIG. 3 (f), the second encapsulation step includes covering at least one protective layer to cover the redistribution circuits 132 and 134 and the semiconductor chip 120 to protect from the external environment. 140 to form and encapsulate the semiconductor package 100 by secondary encapsulation. .

이러한 2차 인캡슐레이션 단계도 상기 1차 인캡슐레이션과 마찬가지로 상,하부 금형사이에 반도체 칩이 탑재된 기판을 고정배치한 다음 수지재를 주입하는 성형방식으로 성형하거나 절연성 필름 또는 내열성 필름을 상기 재배선회로(132,134)와 보호부(130)에 부착하는 방식으로 형성할 수 있다. Like the first encapsulation step, the second encapsulation step is performed by molding a substrate in which a semiconductor chip is mounted between upper and lower molds and then injecting a resin material or molding an insulating film or a heat resistant film. It can be formed by attaching to the redistribution circuit (132, 134) and the protection unit (130).

한편, 상기 반도체 패키지(100)는 도 3(g)에 도시한 바와 같이, 상기 기판(110)의 하부면에 형성된 외부단자(116)에 접하는 솔더볼(150)을 매개로 하여 미도시된 메인기판상에 플립칩본딩방식으로 탑재될 수 있다. On the other hand, the semiconductor package 100, as shown in Figure 3 (g), the main substrate not shown through the solder ball 150 in contact with the external terminal 116 formed on the lower surface of the substrate 110 It can be mounted on the flip chip bonding method.

또한, 상기 비어홀을 형성하는 단계(S205)이전에 도 4에 도시한 바와 같이, 상기 보호부(130)의 상부면에 패턴인쇄되는 재배선회로(132,134)를 형성한 상태에서 상기 재배선회로(132,134)상에 솔더 레지스트인 절연층(462)을 도포한 다음 패턴대로 식각하여 상부 재배선 회로(460)를 형성함으로써 상기 보호부(130)상에 2층 구조의 재배선회로를 형성한다. In addition, as shown in FIG. 4, before the forming of the via hole (S205), the redistribution circuit (132 and 134) may be formed on the upper surface of the protection unit 130. The two-layered redistribution circuit is formed on the protection part 130 by applying the insulating layer 462, which is a solder resist, on the 132 and 134 and then etching the pattern to form the upper redistribution circuit 460.

이어서, 상기 상부 재배선회로(460)와 재배선회로(132,134)를 관통하는 비어홀에 도전성 페이스트를 충진하여 도전성 비어홀을 형성함으로써 와이어본딩없이 상기 반도체칩(120)과 기판(110)사이를 전기적으로 연결하는 다른 형태의 반도체 패키지(400)를 제조할 수 있는 것이다. Subsequently, a conductive paste is formed in the via hole penetrating the upper redistribution circuit 460 and the redistribution circuits 132 and 134 to form a conductive via hole, thereby electrically connecting the semiconductor chip 120 and the substrate 110 without wire bonding. It is possible to manufacture another type of semiconductor package 400 to be connected.

그리고, 상기 비어홀을 형성하는 단계(S205)이전에 도 5에 도시한 바와 같이, 상기 반도체 칩(120)상에 접착제(152)를 매개로 하측에 배치된 반도체 칩과 서로 다른 기능을 갖는 상부 반도체 칩(520)을 다이본딩하고, 상측에 배치된 상부 반도체 칩(520)의 다이패드(522)가 외부로 노출되면서 상기 상부 반도체 칩(520)을 감싸도록 상부 보호부(530)를 형성하고, 상기 다이패드(522)와 전기적으로 연결되는 상부 재배선회로(532,534)를 형성하며, 상기 기판(110)의 연결패드(114)가 외부노출되도록 상기 재배선회로(132,134) 및 상부 재배선회로(532,534)와 대응하는 보호부(130)와 상부 보호부(530)에 상기 기판의 연결패드(114)가 외부노출되도록 일정깊이의 비어홀(536)을 형성하고, 상기 비어홀(536)에 도전성 페이스트를 충진하여 도전성 비어홀(138)을 형성한 다음, 상기 상부 반도체 칩(520)과 상부 재배선회로(532,534)를 덮도록 보호층(140)을 형성함으로써 서로 다른 기능을 갖는 복수개의 반도체 칩을 상하적층한 다른 형태의 스택형 반도체 패키지(500)를 제조할 수 있는 것이다. As shown in FIG. 5, before forming the via hole (S205), an upper semiconductor having a function different from that of a semiconductor chip disposed below the adhesive chip 152 on the semiconductor chip 120 is formed. Die-bonding the chip 520, and forms the upper protection unit 530 to surround the upper semiconductor chip 520 while the die pad 522 of the upper semiconductor chip 520 disposed on the upper side is exposed to the outside, Upper redistribution circuits 532 and 534 are electrically connected to the die pads 522, and the redistribution circuits 132 and 134 and upper redistribution circuits are formed so that the connection pads 114 of the substrate 110 are exposed to the outside. Vias 536 having a predetermined depth are formed in the protection part 130 and the upper protection part 530 corresponding to 532 and 534 so that the connection pad 114 of the substrate is exposed to the outside, and a conductive paste is formed in the via hole 536. Filled to form a conductive via hole 138, and then the upper semiconductor By forming the protective layer 140 to cover the chip 520 and the upper redistribution circuits 532 and 534, a stack type semiconductor package 500 having different types of semiconductor chips having different functions may be manufactured. It is.

본 발명은 특정한 실시 예에 관련하여 도시하고 설명하였지만, 이하의 특허청구범위에 의해 마련되는 본 발명의 정신이나 분야를 벗어나지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당 업계에서 통상의 지식을 가 진 자는 용이하게 알 수 있음을 밝혀두고자 한다.While the invention has been shown and described with respect to particular embodiments, it will be appreciated that the invention can be varied and modified without departing from the spirit or scope of the invention as set forth in the claims below. It is to be noted that those with ordinary knowledge can easily know.

도 1은 본 발명의 실시 예에 따른 반도체 패키지 제조방법에 의해서 제조되는 반도체 패키지를 도시한 종단면도이다. 1 is a longitudinal cross-sectional view illustrating a semiconductor package manufactured by a semiconductor package manufacturing method according to an embodiment of the present invention.

도 2는 본 발명의 실시 예에 따른 반도체 패키지 제조방법을 도시한 공정 순서도이다.2 is a process flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

도 3(a) 내지 도 3(g)는 본 발명의 실시 예에 따른 반도체 패키지 제조방법을 도시한 공정 흐름도이다. 3A to 3G are process flowcharts illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

도 4는 본 발명의 다른 실시 예에 따른 반도체 패키지 제조방법에 의해서 제조되는 반도체 패키지를 도시한 종단면도이다. 4 is a longitudinal cross-sectional view illustrating a semiconductor package manufactured by a method of manufacturing a semiconductor package according to another exemplary embodiment of the present disclosure.

도 5는 본 발명의 또 다른 실시 예에 따른 반도체 패키지 제조방법에 의해서 제조되는 반도체 패키지를 도시한 종단면도이다. 5 is a longitudinal cross-sectional view illustrating a semiconductor package manufactured by a method of manufacturing a semiconductor package according to still another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *  Explanation of symbols on the main parts of the drawings

110 : 반도체 패키지 114 : 연결패드110: semiconductor package 114: connection pad

116 : 외부단자 120 : 반도체 칩116: external terminal 120: semiconductor chip

122 : 다이패드 130 : 보호부122: die pad 130: protection unit

132,134 : 재배선 회로 136 : 비어홀132,134: redistribution circuit 136: via hole

138 : 도전성 비어홀 140 : 보호층138: conductive via hole 140: protective layer

Claims (5)

기판을 준비하는 단계 ;Preparing a substrate; 상기 기판상에 반도체 칩을 다이본딩하는 단계;Die bonding a semiconductor chip onto the substrate; 상기 반도체 칩의 상부면에 형성된 다이패드를 외부노출시키면서 상기 반도체 칩을 보호하도록 에워싸는 보호부를 형성하도록 1차 인캡슐레이션하는 단계 ;First encapsulating the outer surface of the die pad formed on the upper surface of the semiconductor chip to form a protection portion surrounding the semiconductor chip; 상기 다이패드와 전기적으로 연결되도록 상기 보호부의 상부면에 재배선회로를 형성하는 단계 ;Forming a redistribution circuit on an upper surface of the protection part to be electrically connected to the die pad; 상기 기판에 형성된 연결패드가 외부노출되도록 상기 보호부에 비어홀을 형성하는 단계;Forming a via hole in the protective part such that a connection pad formed on the substrate is exposed to the outside; 상기 재배선회로와 기판이 전기적으로 연결되도록 도전성 페이스트로서 상기 비어홀을 충진하는 단계 ;Filling the via hole with a conductive paste to electrically connect the redistribution circuit and the substrate; 상기 재배선회로와 반도체 칩의 상부면을 덮어 보호하는 보호층을 형성하도록 2차 인캡슐레이션하는 단계를 포함하는 반도체 패키지 제조방법. And encapsulating the second circuit to form a protective layer covering the redistribution circuit and the upper surface of the semiconductor chip. 제1항에 있어서,The method of claim 1, 상기 비어홀을 형성하는 단계 이전에 상기 재배선회로상에 솔더 레지스트인 절연층을 도포하고, 패턴대로 식각하여 상부 재배선 회로를 형성하는 단계를 추가 포함함을 특징으로 하는 반도체 패키지 제조방법. And forming an upper redistribution circuit by applying an insulating layer, which is a solder resist, on the redistribution circuit and etching the pattern before forming the via hole. 제1항에 있어서,The method of claim 1, 상기 비어홀을 형성하는 단계이전에 상기 반도체 칩상에 접착제를 매개로 상부 반도체 칩을 다이본딩하고, 상기 반도체 칩의 다이패드가 외부로 노출되면서 상기 상부 반도체 칩을 감싸도록 상부 보호부를 형성하고, 상기 다이패드와 전기적으로 연결되는 상부 재배선회로를 형성하며, 상기 기판의 연결패드가 외부노출되도록 상기 재배선회로 및 상부 재배선회로와 대응하는 보호부에 일정깊이의 비어홀을 형성하고, 상기 비어홀에 도전성 페이스트를 충진하여 도전성 비어홀을 형성한 다음, 상기 상부 반도체 칩과 상부 재배선회로를 덮도록 보호층을 형성함을 특징으로 하는 반도체 패키지 제조방법. Prior to forming the via hole, die bonding an upper semiconductor chip on the semiconductor chip through an adhesive, forming an upper protection portion to surround the upper semiconductor chip while the die pad of the semiconductor chip is exposed to the outside, and the die An upper redistribution circuit electrically connected to the pad, a via hole having a predetermined depth is formed in a protective part corresponding to the redistribution circuit and the upper redistribution circuit so that the connection pad of the substrate is exposed to the outside, and a conductive part is formed in the via hole Forming a conductive via hole by filling a paste, and then forming a protective layer to cover the upper semiconductor chip and the upper redistribution circuit. 제1항에 있어서, The method of claim 1, 상기 1차 인캡슐레이션하는 단계는 상,하부 금형사이에 반도체 칩이 탑재된 기판을 고정배치한 다음 수지재를 주입하는 성형방식으로 성형하거나 절연성 필름을 기판상에 부착하는 방식으로 형성함을 특징으로 하는 반도체 패키지 제조방법. The step of encapsulating the first step is to form a substrate in which the semiconductor chip is mounted between the upper and lower molds, and then molding by injection molding a resin material or by attaching an insulating film on the substrate. A semiconductor package manufacturing method. 제1항에 있어서,The method of claim 1, 상기 2차 인캡슐레이션 하는 단계는 상,하부 금형사이에 반도체 칩이 탑재된 기판을 고정배치한 다음 수지재를 주입하는 성형방식으로 성형하거나 절연성 또는 내열성 필름을 상기 재배선회로와 보호부상에 부착하는 방식으로 형성함을 특징으로 하는 반도체 패키지 제조방법. The second encapsulation may be performed by forming a semiconductor chip-mounted substrate between the upper and lower molds, and then molding the resin by injecting a resin material or attaching an insulating or heat-resistant film to the redistribution circuit and the protection part. Method for manufacturing a semiconductor package, characterized in that formed in the manner.
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