KR100859476B1 - Method for Forming Semiconductor Device - Google Patents

Method for Forming Semiconductor Device Download PDF

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KR100859476B1
KR100859476B1 KR1020060137307A KR20060137307A KR100859476B1 KR 100859476 B1 KR100859476 B1 KR 100859476B1 KR 1020060137307 A KR1020060137307 A KR 1020060137307A KR 20060137307 A KR20060137307 A KR 20060137307A KR 100859476 B1 KR100859476 B1 KR 100859476B1
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film
forming
semiconductor device
thickness
nitride film
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KR1020060137307A
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Korean (ko)
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KR20080062035A (en
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김태성
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 하부금속 배선을 구비한 반도체 기판 상면에 순차적으로 질화막, 제1 SiH4막, FSG막 및 제2 SiH4막을 형성한 후 상기 질화막의 일부가 노출되도록 다마신 공정을 수행하여 비아 홀 및 트렌치를 형성하는 단계와, 초음파를 이용하여 식각공정시 발생하는 파티클을 제거하는 스크러버를 수행하는 단계와, 식각 공정을 수행하여 상기 하부 금속배선의 일부가 노출되도록 상기 질화막을 선택적으로 제거하는 단계와, 상기 비아 홀 및 트렌치를 매립하는 금속막을 증착한 후 평탄화 공정을 수행하여 상부 금속배선을 형성하는 단계를 포함하는 반도체 소자 형성방법에 관한 것이다.The present invention sequentially forms a nitride film, a first SiH4 film, an FSG film, and a second SiH4 film on an upper surface of a semiconductor substrate having a lower metal wiring, and then performs a damascene process to expose a portion of the nitride film, thereby forming a via hole and a trench. Forming a scrubber to remove particles generated during an etching process using ultrasonic waves, and selectively removing the nitride film to expose a portion of the lower metal wiring by performing an etching process; A method of forming a semiconductor device includes depositing a metal layer filling a via hole and a trench, and then forming a top metal wiring by performing a planarization process.

파티클 particle

Description

반도체 소자 형성방법{Method for Forming Semiconductor Device}Method for Forming Semiconductor Device {Method for Forming Semiconductor Device}

도 1 a은 종래 기술에 따른 반도체 소자의 패턴 상부에 파티클을 ESM을 통해 촬영한 이미지.1A is an image of a particle photographed through an ESM on a pattern of a semiconductor device according to the related art.

도 1b는 종래 기술에 따른 반도체 소자에 파티클에 의한 단차를 ESM을 통해 촬영한 이미지.Figure 1b is an image of the step taken by the particle in the semiconductor device according to the prior art through the ESM.

도 2a 내지 도 2g는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도.2A to 2G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***

200 : 반도체 기판 201 : 하부 금속배선200: semiconductor substrate 201: lower metal wiring

202a : 질화막 패턴 205b: 제1 SiH4막 패턴202a: nitride film pattern 205b: first SiH4 film pattern

206b : FSG막 패턴 208b : 제2 SiH4막 패턴206b: FSG film pattern 208b: second SiH4 film pattern

222 : 상부 금속배선222: upper metal wiring

본 발명은 반도체 소자 형성방법에 관한 것으로, 특히, 식각공정 중에 발생하는 파티클(paticle)의 이물질을 제거하는 반도체 소자 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device for removing foreign substances in particles generated during an etching process.

하부 금속배선을 구비하는 반도체 기판상에 질화막 및 FSG막을 순차적으로 형성한 후 식각공정을 수행하여 트렌치 및 비아 홀을 형성한다. 이 후, 반도체 기판의 하부 금속배선과 상부 금속배선이 콘택될 수 있도록 식각공정을 재수행하여 질화막을 제거하고 패턴을 포함하는 반도체 기판 전면에 금속막을 증착한 후 화학기계적 연마(CMP:chemical mechanical planarization)공정으로 평탄화를 수행하여 상부 금속배선을 형성한다.After the nitride film and the FSG film are sequentially formed on the semiconductor substrate having the lower metal wiring, the etching process is performed to form trenches and via holes. After that, the etching process is performed again so that the lower metal wiring and the upper metal wiring of the semiconductor substrate may be contacted, the nitride film is removed, and the metal film is deposited on the entire surface of the semiconductor substrate including the pattern, followed by chemical mechanical planarization (CMP). The planarization is performed to form the upper metal wiring.

그러나, 도 1a에서 나타낸 바와 같이 식각공정을 수행하여 패턴을 형성하는 경우에 패턴 상부에 파티클(particle) 등의 이물질이 발생합니다.However, as shown in FIG. 1A, when an etching process is performed to form a pattern, foreign substances such as particles are generated on the upper part of the pattern.

또한, 도 1b에서 나타낸 바와 같이 패턴 상부에 파티클 등의 이물질이 형성된 상태에서 식각공정을 수행하여 질화막을 제거하는 경우에 파티클 등의 이물질에 의해 블록화(block)되어 반도체 소자에 단차가 생겨 질화막이 완전히 제거되지 않아 상부 금속배선과 하부 금속배선이 콘택되지 못하는 문제점이 있다.In addition, as shown in FIG. 1B, when the nitride film is removed by performing an etching process in a state where foreign substances such as particles are formed on the pattern, the nitride film is completely blocked due to foreign substances such as particles and a step is formed in the semiconductor device. There is a problem that the upper metal wiring and the lower metal wiring is not contacted because it is not removed.

본 발명은 상술한 바와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 식각공정 중에 형성되는 파티클(particle)과 같은 이물질을 제거하는 반도체 소자 형성방법을 제공하는 데 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, and an object of the present invention is to provide a method for forming a semiconductor device for removing foreign substances such as particles (particles) formed during the etching process.

전술한 목적을 달성하기 위한 본 발명의 특징은, 하부금속 배선을 구비한 반도체 기판 상면에 순차적으로 질화막, 제1 SiH4막, FSG막 및 제2 SiH4막을 형성한 후 상기 질화막의 일부가 노출되도록 다마신 공정을 수행하여 비아 홀 및 트렌치를 형성하는 단계와, 초음파를 이용하여 식각공정시 발생하는 파티클을 제거하는 스크러버를 수행하는 단계와, 식각 공정을 수행하여 상기 하부 금속배선의 일부가 노출되도록 상기 질화막을 선택적으로 제거하는 단계와, 상기 비아 홀 및 트렌치를 매립하는 금속막을 증착한 후 평탄화 공정을 수행하여 상부 금속배선을 형성하는 단계를 포함한다.A feature of the present invention for achieving the above object is that the nitride film, the first SiH4 film, the FSG film and the second SiH4 film are sequentially formed on the upper surface of the semiconductor substrate having the lower metal wiring so that a part of the nitride film is exposed. Forming a via hole and a trench by performing a drinking process; and performing a scrubber to remove particles generated during an etching process by using ultrasonic waves; and performing a etching process to expose a portion of the lower metal wiring. Selectively removing the nitride film, and depositing a metal film filling the via hole and the trench, and then forming a top metal wiring by performing a planarization process.

본 발명에서 상기 스크러버는, 상기 초음파와 함께 브러쉬를 이용하여 식각 공정시 발생하는 파티클을 제거하는 것을 특징으로 한다.In the present invention, the scrubber is characterized in that to remove the particles generated during the etching process by using a brush with the ultrasonic wave.

삭제delete

본 발명에서 상기 질화막의 두께는, 630Å 내지 770Å의 두께로 형성되는 것을 특징으로 한다.In the present invention, the nitride film has a thickness of 630 kPa to 770 kPa.

본 발명에서 상기 제1 SiH4막의 두께는, 450Å 내지 550Å의 두께로 형성되는 것을 특징으로 한다. In the present invention, the first SiH 4 film has a thickness of 450 kPa to 550 kPa.

본 발명에서 상기 FSG막의 두께는, 4300Å 내지 5300Å의 두께로 형성되는 것을 특징으로 한다.In the present invention, the FSG film has a thickness of 4300 kPa to 5300 kPa.

본 발명에서 상기 제2 SiH4막의 두께는, 2000Å 내지 3000Å의 두께로 형성되는 것을 특징으로 한다.In the present invention, the thickness of the second SiH 4 film is formed to a thickness of 2000 kPa to 3000 kPa.

본 발명에서 상기 평탄화 공정은, 에치백 또는 CMP 공정을 수행하는 것을 특징으로 한다.In the present invention, the planarization process is characterized by performing an etch back or CMP process.

이하에서 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자 형성방법에 대해서 상세히 설명한다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g은 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도들이다.2A to 2G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

먼저, 도 2a에서 나타낸 바와 같이, 하부 금속 배선(201)을 구비한 반도체 기판(200)상에 플라즈마 보강기상 증착(PECVD:Plasma enhanced CVD)방법을 이용하여 질화막(202), 제1 SiH4막(205), FSG막(206) 및 제2 SiH4막(208)을 순차적으로 형성한다.First, as shown in FIG. 2A, a nitride film 202 and a first SiH4 film (PECVD) are formed on a semiconductor substrate 200 having a lower metal wiring 201 by using a plasma enhanced CVD (PECVD) method. 205, FSG film 206, and second SiH4 film 208 are sequentially formed.

여기서, 질화막(202)은 630Å~770Å의 두께로 형성하고, 제1 SiH막(205)는 450Å~550Å의 두께로 형성하며, FSG막(206)은 4300Å~5300Å의 두께로 형성하고, 제2 SiH4막(208)은 2000Å~3000Å의 두께로 형성한다.Here, the nitride film 202 is formed to a thickness of 630 kPa to 770 kPa, the first SiH film 205 is formed to a thickness of 450 kPa to 550 kPa, the FSG film 206 is formed to a thickness of 4300 kPa to 5300 kPa, and the second The SiH 4 film 208 is formed to a thickness of 2000 kPa to 3000 kPa.

이 후, 제2 SiH막(208) 전면에 비아 홀을 형성하기 위하여 포토 레지스트 물질을 도포한 후 패터닝하여 제1 포토 레지스트 패턴(210)을 형성한다.Thereafter, a photoresist material is coated on the entire surface of the second SiH film 208 and then patterned to form a first photoresist pattern 210.

도 2b에서 나타낸 바와 같이, 제1 포토 레지스트 패턴(210)을 식각 마스크로 이용하는 식각공정 예컨대, RIE(Reactive Ion Etcher)공정을 수행하여 질화막(202)의 일부가 노출되도록 제2 SiH막(208), FSG막(206) 및 제1 SiH막(205)을 선택적으로 식각하여 비아 홀(212)을 형성한다. As shown in FIG. 2B, the second SiH film 208 is exposed so that a portion of the nitride film 202 is exposed by performing an etching process using the first photoresist pattern 210 as an etching mask, for example, a reactive ion etchant (RIE) process. The via hole 212 is formed by selectively etching the FSG film 206 and the first SiH film 205.

도 2c에서 나타낸 바와 같이, 에싱 및 세정공정을 수행하여 제1 포토 레지스트 패턴(210)을 제거하고 비아 홀(212)을 포함하는 반도체 기판(200) 전면에 포토 레지스트 물질을 도포하여 비아 홀(212)을 매립한 후 리세스 공정을 수행하여 제2 포토레지스트 패턴(214)을 형성한다.As shown in FIG. 2C, the first photoresist pattern 210 may be removed by an ashing and cleaning process, and the photoresist material may be coated on the entire surface of the semiconductor substrate 200 including the via holes 212 to form the via holes 212. ) And then the recess process is performed to form the second photoresist pattern 214.

도 2d에서 나타낸 바와 같이, 제2 포토 레지스트 패턴(214)을 포함하는 반도 체 기판(200) 전면에 트렌치를 형성하기 위하여 포토 레지스트 물질을 도포한 후 패터닝하여 제3 포토 레지스트 패턴(216)을 형성한다.As shown in FIG. 2D, a photoresist material is coated on the entire surface of the semiconductor substrate 200 including the second photoresist pattern 214 and then patterned to form a third photoresist pattern 216. do.

이 후, 제3 포토 레지스트 패턴(216)을 식각 마스크로 이용하는 식각공정 예컨대, RIE(Reactive Ion Etcher)공정을 수행하여 소정의 깊이 예컨대, 3500Å의 깊이로 제2 SiH막 패턴(208a) 및 FSG막 패턴(206a)을 선택적으로 식각하여 트렌치(218)를 형성한다.Thereafter, an etching process using the third photoresist pattern 216 as an etching mask is performed, for example, a reactive ion etchant (RIE) process, and the second SiH film pattern 208a and the FSG film are formed at a predetermined depth, for example, 3500 GPa. The pattern 206a is selectively etched to form the trench 218.

도 2e에서 나타낸 바와 같이, 에싱 및 세정공정을 수행하여 제3 포토 레지스트 패턴(216)을 제거하고 아울러, 제2 포토 레지스트 패턴(214a)을 제거하여 비아 홀(212a)을 형성한다.As shown in FIG. 2E, the third photoresist pattern 216 is removed by performing an ashing and cleaning process, and the second photoresist pattern 214a is removed to form the via hole 212a.

도 2f에서 나타낸 바와 같이, 디아이 워터(DIW:DI water) 및 스핀 드라이(spin dry)방법을 이용하여 식각 공정시 발생하는 파티클(220)과 같은 이물질을 제거한 후 식각 공정을 수행하여 하부금속배선(201)의 일부가 노출되도록 질화막(202)을 선택적으로 제거하여 질화막 패턴(202a)을 형성한다.As shown in FIG. 2F, a foreign material such as particles 220 generated during an etching process is removed using a DI water and a spin dry method, and then an etching process is performed to remove the foreign material such as particles. The nitride film 202 is selectively removed to expose a portion of the 201 to form the nitride film pattern 202a.

도 2g에서 나타낸 바와 같이, 비아 홀(212a) 및 트렌치(218)를 매립하는 금속막을 도포한 후 에치백 또는 CMP방법으로 평탄화하여 상부 금속막 배선(222)을 형성한다.As shown in FIG. 2G, the metal film filling the via hole 212a and the trench 218 is coated and then planarized by an etch back or CMP method to form the upper metal film wiring 222.

따라서, 식각공정 중에 발생하는 파티클과 같은 이물질을 스크러버를 이용하여 제거한 후 상부 금속배선과 하부 금속배선이 콘택할 수 있도록 질화막을 제거함으로써, 반도체의 수율을 향상시킬 수 있다.Therefore, by removing a foreign material such as particles generated during the etching process by using a scrubber, the nitride film is removed so that the upper metal wiring and the lower metal wiring can contact each other, thereby improving the yield of the semiconductor.

이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것이 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면, 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains can make various modifications and Modifications are possible.

그러므로, 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐만 아니라 이 특허 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자 형성방법은 스크러버를 이용하여 식각 공정시 발생하는 파티클과 같은 이물질을 제거함으로써, 질화막을 완전히 제거할 수 있어 상부 금속막 배선과 하부 금속막 배선이 콘택될 수 있도록 하여 수율을 향상시킬 수 있는 효과가 있다.As described above, in the method of forming a semiconductor device according to the present invention, by removing foreign substances such as particles generated during an etching process by using a scrubber, the nitride film can be completely removed, so that the upper metal film wiring and the lower metal film wiring are contacted. It can be effective to improve the yield.

Claims (8)

하부금속 배선을 구비한 반도체 기판 상면에 순차적으로 질화막, 제1 SiH4막, FSG막 및 제2 SiH4막을 형성한 후 상기 질화막의 일부가 노출되도록 다마신 공정을 수행하여 비아 홀 및 트렌치를 형성하는 단계와,Forming via holes and trenches by sequentially forming a nitride film, a first SiH4 film, an FSG film, and a second SiH4 film on a top surface of a semiconductor substrate having a lower metal wiring, and performing a damascene process to expose a portion of the nitride film. Wow, 초음파를 이용하여 식각공정시 발생하는 파티클을 제거하는 스크러버를 수행하는 단계와,Performing a scrubber to remove particles generated during an etching process using ultrasonic waves; 식각 공정을 수행하여 상기 하부 금속배선의 일부가 노출되도록 상기 질화막을 선택적으로 제거하는 단계와,Selectively removing the nitride film to expose a portion of the lower metal wiring by performing an etching process; 상기 비아 홀 및 트렌치를 매립하는 금속막을 증착한 후 평탄화 공정을 수행하여 상부 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성방법.And depositing a metal film filling the via hole and the trench, and then forming a top metal wiring by performing a planarization process. 삭제delete 제1항에 있어서,The method of claim 1, 상기 스크러버는,The scrubber is, 상기 초음파와 함께 브러쉬를 이용하여 식각 공정시 발생하는 파티클을 제거하는 것을 특징으로 하는 반도체 소자 형성방법.The method of forming a semiconductor device, characterized in that to remove the particles generated during the etching process by using a brush with the ultrasonic wave. 제1항에 있어서,The method of claim 1, 상기 질화막의 두께는,The thickness of the nitride film, 630Å 내지 770Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자 형성방법.A method of forming a semiconductor device, characterized in that formed to a thickness of 630kPa to 770kPa. 제1항에 있어서,The method of claim 1, 상기 제1 SiH4막의 두께는,The thickness of the first SiH 4 film is 450Å 내지 550Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자 형성방법. A method of forming a semiconductor device, characterized in that formed in a thickness of 450 ~ 550Å. 제1항에 있어서,The method of claim 1, 상기 FSG막의 두께는,The thickness of the FSG film, 4300Å 내지 5300Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자 형성방법.A method for forming a semiconductor device, characterized in that formed in the thickness of 4300Å to 5300Å. 제1항에 있어서,The method of claim 1, 상기 제2 SiH4막의 두께는,The thickness of the second SiH 4 film, 2000Å 내지 3000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자 형 성방법.A method of forming a semiconductor device, characterized in that formed in a thickness of 2000 kPa to 3000 kPa. 제1항에 있어서,The method of claim 1, 상기 평탄화 공정은,The planarization process, 에치백 또는 CMP 공정을 수행하는 것을 특징으로 하는 반도체 소자 형성방법.A method of forming a semiconductor device comprising performing an etch back or CMP process.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040049884A (en) * 2002-12-05 2004-06-14 아남반도체 주식회사 Formation method of trench in semiconductor device
KR20050069586A (en) * 2003-12-31 2005-07-05 동부아남반도체 주식회사 Method for fabricating dual damascene pattern
JP2006344749A (en) 2005-06-08 2006-12-21 Fujitsu Ltd Manufacturing method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040049884A (en) * 2002-12-05 2004-06-14 아남반도체 주식회사 Formation method of trench in semiconductor device
KR20050069586A (en) * 2003-12-31 2005-07-05 동부아남반도체 주식회사 Method for fabricating dual damascene pattern
JP2006344749A (en) 2005-06-08 2006-12-21 Fujitsu Ltd Manufacturing method of semiconductor device

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