KR100842496B1 - Method for matching overlay in a semiconductor exposure process - Google Patents

Method for matching overlay in a semiconductor exposure process Download PDF

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Publication number
KR100842496B1
KR100842496B1 KR1020060133489A KR20060133489A KR100842496B1 KR 100842496 B1 KR100842496 B1 KR 100842496B1 KR 1020060133489 A KR1020060133489 A KR 1020060133489A KR 20060133489 A KR20060133489 A KR 20060133489A KR 100842496 B1 KR100842496 B1 KR 100842496B1
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South Korea
Prior art keywords
overlay
matching
equipment
exposure process
image map
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KR1020060133489A
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Korean (ko)
Inventor
강경호
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동부일렉트로닉스 주식회사
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Priority to KR1020060133489A priority Critical patent/KR100842496B1/en
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The present invention relates to an overlay matching technique in a semiconductor exposure process, in which an overlay image map of a first device is stored in an overlay measurement facility, and when an overlay is measured after an exposure process in a second device, The degree of matching is checked based on the overlay image map, and the correction is performed according to the matching degree. According to the present invention, since the first pattern exposure in the first equipment is not required in the overlay matching check, there is no need for equipment arrangement time, and even when the reference value changes due to the equipment change point of the 1st progress equipment, It is based on an image map and is not affected at all.

Description

[0001] METHOD FOR MATCHING OVERLAY IN A SEMICONDUCTOR EXPOSURE PROCESS [0002]

1 is a diagram illustrating an overlay matching method according to the prior art,

2 is a flow chart showing an overlay matching procedure according to the prior art,

3 is a diagram illustrating a method of confirming an overlay value in an overlay facility according to the prior art;

4 is a diagram illustrating a first overlay pattern map according to a preferred embodiment of the present invention,

5 is a diagram illustrating a second overlay pattern map according to a preferred embodiment of the present invention,

6 is a flowchart showing a first overlay pattern proceeding procedure according to a preferred embodiment of the present invention,

7 is a flowchart illustrating a first overlay pattern proceeding procedure according to a preferred embodiment of the present invention,

8 is a diagram illustrating a comparison method between image maps according to a preferred embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overlay matching technique in an exposure process of a semiconductor device, and more particularly, to a method of overlay matching in a semiconductor exposure process suitable for performing overlay matching using an overlay image map.

Among the semiconductor equipment, the equipment corresponding to the exposure process is a stepper. In the case of a stepper, exposure is performed in as many devices as the number of progress layers. At this time, an offset variation of the equipment may occur, which is caused by a difference in reference value between the devices. An overlay matching method is used to minimize the difference between these reference values. There are various methods for such overlay matching, and there are advantages and disadvantages for each method.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a flowchart showing an overlay matching method according to the related art, FIG. 2 is a flowchart showing an overlay matching procedure according to the related art, and FIG. Fig.

When the overlay matching is performed in the conventional manner, the process proceeds in the same manner as in FIG. In step 202, the first equipment corresponding to the reference exposes a pattern that can confirm the degree of the overlay of the 1st layer. In step 204, X = 120 占 퐉 Y = 120 占 퐉 shift (shift degree is created based on the NIKON mask design (Mask R2205HA)) in the same pattern as the 1st equipment, Exposure is performed. In step 206, the wafer subjected to the exposure is checked for the overlapping degree of the two patterns on the overlay measurement equipment or the stepper equipment.

As to the confirmation of the degree of overlapping of the two patterns, as shown in Fig. 3, the shift degree value in the X direction can be confirmed by B-b, and the shift degree value in the Y direction can be confirmed by A-a.

At this time, almost the same data can be obtained only in the overlay measurement apparatus or the stepper in the method of checking by the overlay measuring apparatus, and the result can be regarded as the difference between the reference value between the 1st equipment and the 2nd equipment. If the average value + 3 delta is less than 0.060 nm in Step 208, the correction is not necessary since it is within the error range. If the average value + 3 delta is larger than 0.060 nm, In step 204, the overlay input offset between the two devices is matched through offset correction on the second device. In addition, the first equipment in step 202 performs the calibration check.

The confirmation of the degree of matching as described above is usually confirmed at the time of preventive maintenance, and the correction is performed. If there is no matching check and calibration process for the overlay, the overlay input value will vary depending on the equipment being driven, even if it is the same device and layer. If the input values are different, there is a high possibility of miss-operation of user carelessness due to the difference between the equipments, which may result in an increase in reworking performance.

In addition, the first and second calibration and confirmation work must be performed according to the time required for the confirmation operation, so that the arrangement time for the 1st progress equipment is further added.

Also, the above-mentioned overlay matching method has a problem in that, even if a 1st pattern corresponding to a reference device has a 1st pattern exposure change point due to a specific reason, it is impossible to check it, resulting in overlay input variation of a progress layer .

SUMMARY OF THE INVENTION The present invention overcomes the limitations of the prior art described above and provides an overlay matching method in a semiconductor exposure process that can perform overlay matching using a reference overlay image map stored in an overlay measurement facility .

It is another object of the present invention to provide an overlay matching method in a semiconductor exposure process which can immediately check the degree of matching based on an image map stored in an overlay device.

According to another aspect of the present invention, there is provided an overlay matching method in a semiconductor exposure process, comprising the steps of: storing an overlay image map of a first device in an overlay measurement facility; A step of checking a degree of matching based on the overlay image map stored in the overlay measuring equipment, and a step of performing a correction according to the matching degree.

Hereinafter, the operation principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

The present invention stores an overlay image map of a reference in an overlay measurement facility and exposes the facility, and then measures the degree of matching with the reference equipment during overlay measurement by directly exposing the same to a conventional method It is possible to directly check the degree of matching based on the image map stored in the overlay device. In order to confirm the matching, it is possible to save time by omitting the 1st exposure process in the reference device, It is possible to eliminate confusion as the reference shifts.

FIG. 4 is a diagram illustrating a first overlay pattern map according to a preferred embodiment of the present invention, and FIG. 5 is a diagram illustrating a second overlay pattern map according to a preferred embodiment of the present invention.

First, referring to FIG. 4, the box mark center coordinates of the overlay 1st pattern are stored as the absolute coordinates of the wafer reference on the overlay measuring equipment. The data of each shot confirmed when overlay matching the center values of the first box marks of the multiple shots is stored as a wafer image map of the 1st pattern on the basis of the absolute coordinates.

In the overlay matching confirmation, only the 2nd layer is exposed in the 2nd progressing equipment without exposure of the 1st equipment, so that the overlay shift degree can be confirmed by calculating only the center of the small box mark of the 2nd layer in the overlay measuring equipment as shown in FIG.

6 is a flowchart illustrating a first overlay pattern proceeding procedure according to a preferred embodiment of the present invention.

Referring to FIG. 6, the first layer of the first equipment is exposed in step 602, and the overlay is measured in step 604. At this time, an image map is formed around the box mark of the first pattern. That is, the image map of the overlay measuring equipment is used as the reference in the 1st progress facility. In addition, after the 1st pattern progress and the overlay measurement, the 1st pattern map of each shot is stored, and the degree of wafer deformation by each layer and the data of the wafer deformation type (shift degree / morphology change) Can

7 is a flowchart illustrating a first overlay pattern proceeding procedure according to a preferred embodiment of the present invention.

Referring to FIG. 7, in step 702, the second device performs exposure on the second layer, and when the overlay is measured in step 704, it compares the first image map and the second image map constructed from the first equipment. Similarly, a comparison between image maps is performed.

If the comparative average value + 3 delta is less than 0.060 nm in step 706, it indicates the overlay value within the error range. Therefore, if the average value + 3 delta is larger than 0.060 nm, correction must be performed. Input the overlay offset value with the equipment to perform the correction.

As described above, the present invention performs overlay matching using the reference overlay image map stored in the overlay measurement facility.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, and equivalents thereof.

In the present invention that operates as described in detail above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

Since the first pattern exposure in the first equipment is not required in the overlay matching check, the present invention does not require time for arranging the equipment, and even when the reference value fluctuates due to the equipment change point of the 1st progress equipment, Since it is based on an image map, there is an effect that is not affected at all.

Claims (3)

delete As an overlay matching method in a semiconductor exposure process, Performing a layer exposure process on the first equipment, An overlay measuring process for forming an overlay image map around a box mark of an overlaid pattern through the exposure process; A step of storing the overlay image map configured in the first maintenance in an overlay measurement facility Confirming a degree of matching based on the overlay image map stored in the overlay measuring equipment when the overlay is measured after performing the exposure process in the second equipment; The process of performing the correction according to the degree of matching Wherein the overlay matching step comprises: 3. The method of claim 2, Wherein after the overlay measurement in the overlay measurement facility, a pattern map of each shot is stored so as to enable verification of subsequent wafer deformation type data.
KR1020060133489A 2006-12-26 2006-12-26 Method for matching overlay in a semiconductor exposure process KR100842496B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8930011B2 (en) 2010-06-25 2015-01-06 Samsung Electronics Co., Ltd. Method of measuring an overlay of an object

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09115817A (en) * 1995-10-13 1997-05-02 Nikon Corp Aligner and aligning method
JPH11340121A (en) 1998-05-26 1999-12-10 Ushio Inc Aligner
KR20040106003A (en) * 2003-06-10 2004-12-17 삼성전자주식회사 Method of Exposure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09115817A (en) * 1995-10-13 1997-05-02 Nikon Corp Aligner and aligning method
KR970022573A (en) * 1995-10-13 1997-05-30 오노 시게오 Exposure method and device
JPH11340121A (en) 1998-05-26 1999-12-10 Ushio Inc Aligner
KR20040106003A (en) * 2003-06-10 2004-12-17 삼성전자주식회사 Method of Exposure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8930011B2 (en) 2010-06-25 2015-01-06 Samsung Electronics Co., Ltd. Method of measuring an overlay of an object

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