KR100836645B1 - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
KR100836645B1
KR100836645B1 KR1020070022047A KR20070022047A KR100836645B1 KR 100836645 B1 KR100836645 B1 KR 100836645B1 KR 1020070022047 A KR1020070022047 A KR 1020070022047A KR 20070022047 A KR20070022047 A KR 20070022047A KR 100836645 B1 KR100836645 B1 KR 100836645B1
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South Korea
Prior art keywords
semiconductor chip
build
package
insulating material
layer
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KR1020070022047A
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Korean (ko)
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백종환
이성
도재천
강준석
김선경
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삼성전기주식회사
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Priority to KR1020070022047A priority Critical patent/KR100836645B1/en
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Publication of KR100836645B1 publication Critical patent/KR100836645B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An electronic package and a manufacturing method thereof are provided to form a micro pattern which can connect electric contact points of semiconductor chips by forming a build-up layer, thereby enhancing reliability of a CSP(chip scale package). A semiconductor chip having an electrical contact point is mounted(100). The semiconductor chip is encapsulated by coating an insulating member(110). A via which is connected with the electrical contact point is formed by punching the insulating member(120). A unit package including the semiconductor chip, the insulating member and via is stacked repeatedly by repeating the semiconductor mounting process and the via forming process during the predetermined number of times, so that the semiconductor chip can realize a stack structure(130). A bump which is connected with the via electrically is joined(150).

Description

전자 패키지 및 그 제조방법{Electronic package and manufacturing method thereof}Electronic package and manufacturing method thereof

도 1은 종래기술에 따른 전자 패키지를 나타낸 단면도.1 is a cross-sectional view showing an electronic package according to the prior art.

도 2는 종래기술에 따른 전자 패키지를 나타낸 개략도.2 is a schematic view showing an electronic package according to the prior art.

도 3은 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조방법을 나타낸 순서도.3 is a flow chart showing a method of manufacturing an electronic package according to an embodiment of the present invention.

도 4는 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조방법을 나타낸 흐름도.4 is a flowchart illustrating a method of manufacturing an electronic package according to an embodiment of the present invention.

도 5는 본 발명의 바람직한 일 실시예에 따른 전자 패키지를 나타낸 단면도.5 is a cross-sectional view showing an electronic package according to an embodiment of the present invention.

도 6은 본 발명의 바람직한 다른 실시예에 따른 전자 패키지를 나타낸 단면도.6 is a cross-sectional view showing an electronic package according to another preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

10 : 방열판 11 : 접착제10: heat sink 11: adhesive

12a,12b : 반도체 칩 13a, 13b : 전기접점 12a, 12b: semiconductor chip 13a, 13b: electrical contact

14 : 제1 비아 15 : 제2 비아 14: first via 15: second via

14a, 15a : 비아홀 17 : 관통비아14a, 15a: Via hole 17: Through via

17a : 관통홀 20 : 절연재17a: through hole 20: insulating material

30a, 30b : 빌드업층 40 : 범프30a, 30b: buildup layer 40: bump

100 : 제1 패키지 200 : 제2 패키지100: first package 200: second package

본 발명은 전자 패키지 및 그 제조방법에 관한 것이다.The present invention relates to an electronic package and a method of manufacturing the same.

최근에 반도체 산업의 발전과 사용자의 요구에 따라 전자 기기는 더욱 소형화 및 경량화가 요구되고 있다. 이에 따라, 개발된 기술 중의 하나가 용량과 실장밀도의 증가를 위하여 여러 개의 단위 반도체 소자 또는 단위 반도체 칩 패키지를 적층시킨 형태의 3차원 적층 기술이다.Recently, in accordance with the development of the semiconductor industry and the needs of users, electronic devices are required to be more compact and lighter. Accordingly, one of the developed technologies is a three-dimensional stacking technology in which a plurality of unit semiconductor devices or unit semiconductor chip packages are stacked in order to increase capacity and mounting density.

이러한 3차원 패키지 기술은 고집적도를 구현할 수 있다는 장점 외에도 전체적인 상호연결의 길이를 감소시킴으로써 전기적 특성 향상 및 저전력 소비 등의 장점이 있다.In addition to the high integration, the three-dimensional package technology has advantages such as improved electrical characteristics and low power consumption by reducing the overall interconnect length.

현재의 COC(Chip On Chip)구조에 있어서 칩(chip) 스택(stack)을 다층으로 하는 구조는 칩을 스택하고 와이어 본딩(Wire bonding)을 이용하는 기술이 있다. 이러한 와이어 본딩 기술을 이용한 전자 패키지가 도 1에 도시되어 있다. 이러한 기술은 패키지(Package)의 사이즈를 최소화하는 데 있어 한계가 존재하며, 와이어(Wire)를 사용함에 따라 I/O(input/output)수 또한 한계가 존재할 수 밖에 없다.In a current chip on chip (COC) structure, a chip stack having a multilayer structure has a technology of stacking chips and using wire bonding. An electronic package using this wire bonding technique is shown in FIG. 1. This technology has a limit in minimizing the size of a package, and the number of input / output (I / O) also has a limit as wires are used.

이러한 I/O 수의 한계나, 패키지 사이즈를 극복하기 위해 칩에 비아(via)를 만들고 스택하여 제작하는 방법을 이용한 전자 패키지가 도 2에 도시되어 있다. 그 러나, 이러한 구조 또한 칩에 비아를 만듦에 있어 한계가 존재하고, 칩을 정밀하게 스택하지 않을 경우 불량발생의 소지가 높은 문제점을 발생한다. An electronic package using a method of making, stacking and manufacturing vias on a chip to overcome the limitation of the I / O number or the package size is shown in FIG. 2. However, such a structure also has limitations in making vias in the chip, and if the chips are not stacked precisely, there is a high possibility of defects.

본 발명은 사이즈에 있어서 최소화가 가능한 SIP(System In Package) 구조를 구현할 수 있고, 반도체 칩의 전기접점을 연결할 수 있는 미세패턴을 형성할 수 있는 전자 패키지 및 그 제조방법을 제공하는 것이다.The present invention provides an electronic package and a method of manufacturing the same, which can implement a SIP (System In Package) structure that can be minimized in size, and can form a micropattern that can connect an electrical contact of a semiconductor chip.

본 발명의 일 측면에 따르면, 일면에 전기접점이 형성된 반도체 칩(chip)을 실장하는 단계, 절연재를 도포하여 반도체 칩을 인캡슐레이팅(encapsulating)하는 단계,According to an aspect of the invention, the steps of mounting a semiconductor chip (chip) having an electrical contact formed on one surface, encapsulating the semiconductor chip by applying an insulating material,

절연재를 천공하여 전기접점과 전기적으로 연결되는 비아(via)를 형성하는 단계, 실장 단계 내지 비아 형성 단계를 소정 횟수 반복하는 단계 및 비아와 전기적으로 연결되는 범프를 결합하는 단계를 포함하는 전자 패키지 제조방법이 제공된다.Fabricating an electronic package comprising perforating insulating material to form vias electrically connected to electrical contacts, repeating mounting and forming vias a predetermined number of times, and coupling bumps electrically connected to vias A method is provided.

실장 단계 이전에, 반도체 칩이 실장되는 방열판(heat spreader)을 제공할 수 있고, 실장 단계에서, 반도체 칩과 방열판 사이에 접착제(adhesive)를 개재시켜 반도체 칩을 방열판에 접착시킬 수 있다.Before the mounting step, a heat spreader on which the semiconductor chip is mounted may be provided, and in the mounting step, the semiconductor chip may be adhered to the heat sink by interposing an adhesive between the semiconductor chip and the heat sink.

인캡슐레이팅 단계는, 반도체 칩을 커버하도록 방열판에 액상의 수지를 도포하고 소성(curing)시키는 단계를 포함할 수 있다.The encapsulating step may include applying a liquid resin to the heat sink to cover the semiconductor chip and firing the liquid.

비아 형성 단계는, (a) 전기접점이 노출되도록 절연재를 드릴링(drilling)하여 비아홀(via hole)을 천공하는 단계 및 (b) 비아홀의 표면을 도금(plating)하여 제1 비아를 형성하는 단계를 포함할 수 있다.The via forming step includes the steps of (a) drilling an insulating material to expose the electrical contact and drilling the via hole and (b) plating the surface of the via hole to form a first via. It may include.

단계 (b) 이후에, 절연재에 빌드업(build-up)층을 적층하고 빌드업층을 천공하여 제1 비아와 전기적으로 연결되는 제2 비아를 가공하는 빌드업 단계를 더 포함할 수 있는데, 빌드업층은 복수로 적층되고, 제2 비아는 복수의 빌드업층에 각각 가공될 수있다.After step (b), the method may further include a build-up step of stacking a build-up layer on the insulating material and drilling the build-up layer to process a second via electrically connected to the first via. The up layer may be stacked in plural, and the second via may be processed in the plurality of build up layers, respectively.

반복 단계는, 반도체 칩이 스택된 구조를 이루도록 수행될 수 있는데, 반도체 칩은 접착제를 개재하여 절연재에 접착될 수 있고, 반복 단계와 범프 결합하는 단계 사이에, 복수의 비아를 전기적으로 연결하는 관통비아를 형성할 수 있는데, 관통비아의 형성은, 절연재를 천공하여 관통홀을 형성한 후, 관통홀 내에 도전성 페이스트를 충전하여 형성할 수 있다.The repetition step may be performed such that the semiconductor chip has a stacked structure, wherein the semiconductor chip may be adhered to the insulating material through an adhesive, and between the repetition step and the bump coupling step, through the electrically connecting the plurality of vias. Vias may be formed, which may be formed by forming a through hole by drilling an insulating material, and then filling a conductive paste into the through hole.

또한, 본 발명의 다른 측면에 따르면, 방열판(Heat spreader) 상에 복수로 스택(stack)되는 단위 패키지를 포함하는 전자 패키지로서, 단위 패키지는, 전기접점이 형성된 일면이 윗쪽을 향하도록 실장되는 반도체 칩(chip)과, 반도체 칩을 인캡슐레이팅(encapsulating)하는 절연재와, 절연재에 관삽되어 전기접점과 전기적으로 연결되는 제1 비아(via)를 포함하는 것을 특징으로 하는 전자 패키지가 제공된다.In addition, according to another aspect of the present invention, an electronic package including a unit package stacked in a plurality on a heat spreader (Heat spreader), the unit package, a semiconductor is mounted so that one surface formed with an electrical contact is facing upwards An electronic package is provided that includes a chip, an insulating material encapsulating a semiconductor chip, and a first via inserted into the insulating material and electrically connected to an electrical contact.

절연재를 관통하여 형성되며, 복수의 제1 비아를 전기적으로 연결하는 관통비아를 형성할 수 있고, 전자 패키지의 표면에 결합되며, 관통비아와 전기적으로 연결되는 도전성 범프(bump)를 형성할 수 있다.It may be formed through the insulating material, and may form a through via that electrically connects the plurality of first vias, and may form a conductive bump that is coupled to the surface of the electronic package and electrically connected to the through via. .

단위 패키지는, 절연재에 적층되는 빌드업층과, 빌드업층에 관삽되어 제1 비아와 전기적으로 연결되는 제2 비아를 더 포함할 수 있고, 빌드업층은 복수로 적층되고, 제2 비아는 복수의 빌드업층에 각각 가공되어 서로 전기적으로 연결되도록 복수로 형성될 수 있다.The unit package may further include a buildup layer stacked on an insulating material and a second via inserted into the buildup layer and electrically connected to the first via, wherein the buildup layer is stacked in plural, and the second via is formed of a plurality of builds. Each of the up layers may be formed in plural to be electrically connected to each other.

전술한 것 외의 다른 측면, 특징, 잇점이 이하의 도면, 특허청구범위 및 발명의 상세한 설명으로부터 명확해질 것이다.Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

이하, 본 발명에 따른 전자 패키지 및 그 제조방법의 바람직한 실시예를 첨부도면을 참조하여 상세히 설명하기로 하며, 첨부 도면을 참조하여 설명함에 있어, 동일하거나 대응하는 구성 요소는 동일한 도면번호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다.Hereinafter, a preferred embodiment of an electronic package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and Duplicate description thereof will be omitted.

도 3은 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조방법을 나타낸 순서도이고, 도 4는 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조방법을 나타낸 흐름도이다. 도 4를 참조하면, 방열판(10), 접착제(11), 반도체 칩(12a, 12b), 전기접점(13a, 13b), 제1 비아(14), 비아홀(14a, 15a), 제2 비아(15), 관통비아(17), 관통홀(17a), 절연재(20), 빌드업층(30a, 30b), 범프(40), 제1 패키지(100), 제2 패키지(200)가 도시되어 있다.3 is a flowchart illustrating a method of manufacturing an electronic package according to an exemplary embodiment of the present invention, and FIG. 4 is a flowchart illustrating a method of manufacturing an electronic package according to an exemplary embodiment of the present invention. Referring to FIG. 4, the heat sink 10, the adhesive 11, the semiconductor chips 12a and 12b, the electrical contacts 13a and 13b, the first via 14, the via holes 14a and 15a, and the second via ( 15, through vias 17, through holes 17a, insulation 20, buildup layers 30a and 30b, bumps 40, first package 100, and second package 200 are shown. .

본 발명은 반도체 칩 패턴 상부로부터 금속의 배선으로 빌드업(build-up) 기술을 사용하여 패키지(package)를 만들고, 그 상부에 반도체 칩을 실장한 후, 빌드 업을 반복함으로써 사이즈의 최소화 가능한 SIP(System In Package) 구조를 구현한 것이다.According to the present invention, a SIP can be minimized by making a package by using a build-up technique with a wiring of metal from the upper part of the semiconductor chip pattern, mounting the semiconductor chip thereon, and repeating the build up. This is an implementation of the (System In Package) structure.

즉, 본 실시예에 따라 전자 패키지를 제조하기 위해서는 먼저 일면에 전기접점(13a)이 형성된 반도체 칩(12a)을 실장한다(100). 실장공정은 도 4의 (a)에 도시된 것처럼 이루어지는데, 반도체 칩(12a)과 방열판(10) 사이에 접착제(11)를 개재시켜 반도체 칩(12a)을 방열판(10)에 접착시킨다.That is, in order to manufacture the electronic package according to the present exemplary embodiment, the semiconductor chip 12a having the electrical contact 13a formed on one surface thereof is first mounted (100). The mounting process is performed as shown in FIG. 4A, wherein the semiconductor chip 12a is adhered to the heat sink 10 via an adhesive 11 between the semiconductor chip 12a and the heat sink 10.

반도체 칩(12a)의 일면에 전기접점(13a)이 형성되어 있으며, 후술하는 것과 같이 빌드업 기술을 적용하여 전기접점(13a)에 대한 전기적 연결을 구현하기 위해 도 4의 (b)와 같이 전기접점(13a)이 형성된 면이 노출되도록, 즉 전기접점(13a)이 형성되지 않은 면을 방열판(10)에 접합한다. 반도체 칩(12a)의 하부에 방열판(Heat spreader)(10)이 부착되어 있어 반도체 칩(12a)으로부터 발생되는 열을 보다 효율적으로 방출시킬 수 있다.An electrical contact 13a is formed on one surface of the semiconductor chip 12a, and as shown in FIG. 4 (b) to implement an electrical connection to the electrical contact 13a by applying a build-up technique as described below. The surface on which the contact 13a is formed is exposed, that is, the surface on which the electrical contact 13a is not formed is bonded to the heat sink 10. Since a heat spreader 10 is attached to the lower portion of the semiconductor chip 12a, heat generated from the semiconductor chip 12a may be more efficiently discharged.

또한, 방열판(10)에 반도체 칩(12a) 실장 공정은 반도체 칩의 실장을 위한 복잡한 공정 대신 단순히 접착제(11)를 사용하여 칩을 접합하는 공정으로 수행될 수 있어 저렴하고 신속하게 진행될 수 있다.In addition, the mounting process of the semiconductor chip 12a on the heat sink 10 may be performed by simply bonding the chip using the adhesive 11 instead of the complicated process for mounting the semiconductor chip, and thus may be inexpensively and quickly performed.

다음으로, 도 4의 (c)에 도시된 바와 같이, 방열판(10)에 절연재(20)를 코팅하여 반도체 칩(12a)을 절연재(20) 내에 수용시켜 커버하는 인캡슐레이팅(encapsulating) 공정을 진행한다(110). 반도체 칩(12a)의 몰딩은 EMC(Epoxy molding compound) 등 기존의 몰딩재로 인캡슐레이팅할 수도 있으며 후술할 빌드업층(30a, 30b)의 재질과 동일한 PI 레진 등을 사용하면 반도체 칩 인캡슐레이팅 공 정과 빌드업 공정을 동일한 프로세스로 진행할 수 있어 공정이 단순하고, 재료 간의 물성차이로 인한 패키지의 에러를 방지할 수 있다.Next, as shown in FIG. 4C, an encapsulating process of coating the insulating material 20 on the heat sink 10 to accommodate and cover the semiconductor chip 12a in the insulating material 20 is performed. Proceed 110. The molding of the semiconductor chip 12a may be encapsulated with an existing molding material such as an epoxy molding compound (EMC), and encapsulating the semiconductor chip using the same PI resin as the material of the build-up layers 30a and 30b to be described later. The process and build-up process can be carried out in the same process, which simplifies the process and prevents package errors due to material differences between materials.

본 실시예에서는 반도체 칩(12a)을 커버하도록 방열판(10)에 빌드업층(30a, 30b)의 재질과 동일한 액상의 수지를 도포하고 이를 소성(curing)시키는 공정으로 진행될 수 있다(112). In the present exemplary embodiment, the process may be performed by applying a resin having the same liquid resin as that of the build-up layers 30a and 30b to the heat sink 10 so as to cover the semiconductor chip 12a and baking the same.

절연재(20)가 경화된 후에는 절연재(20)를 천공하여 전기접점(13a)과 전기적으로 연결되는 비아(14)를 형성한다(120). 비아(14)는 내장된 반도체 칩(12a)의 전기접점(13a)이 외부와 전기적으로 연결될 수 있게 하는 역할을 하며, 후술할 최종 전자 패키지 제조 완료 후, 각 단위 패키지 간의 반도체 칩을 관통비아(17)를 통하여 전기적으로 연결할 수 있도록 한다. After the insulating material 20 is cured, the insulating material 20 is drilled to form a via 14 electrically connected to the electrical contact 13a (120). The via 14 serves to allow the electrical contact 13a of the embedded semiconductor chip 12a to be electrically connected to the outside. After completion of manufacturing of the final electronic package, which will be described later, the via 14 passes through the semiconductor chip between the unit packages. 17) to be electrically connected.

본 발명에서'비아'는 후술할 절연재(20)에 형성될 제1 비아(14)와 빌드업층(30a)에 형성될 제2 비아(15)를 통칭하는 의미이고, 특정 위치에 형성되는 경우에는 제1 또는 제2 비아로 설명하며, 절연층 또는 빌드업층에 관삽되는 전기접점과의 전기적 연결통로를 통칭하여 '비아'로 설명한다.In the present invention, the term 'via' refers to the first via 14 to be formed in the insulating material 20 to be described later and the second via 15 to be formed in the buildup layer 30a. The first or second vias will be described, and the electrical connection paths with electrical contacts inserted into the insulating layer or the buildup layer will be collectively described as 'vias'.

비아(14) 형성단계는 도 4의 (d)에 도시된 바와 같이, 반도체 칩(12a)의 전기접점이(13a) 노출되도록 절연재(20)를 드릴링(drilling)하여 비아홀(14a)을 천공하고(122), 도 4의 (e)와 같이, 표면에 Cu 스퍼터링(sputtering), 도전성 페이스트 충전 등의 공정을 적용하여 도금층이 형성되도록 함으로써 제1 비아(14)를 형성한다(124). 이로써, 내장된 반도체 칩(12a)의 전기접점(13a)이 외부와 전기적으로 연결될 수 있게 된다. 비아홀(14a)의 천공에 사용되는 드릴링 공정 및 비아홀(14a)을 전기적으로 도통시키기 위한 도금 공정이 전술한 실시예에 한정되지 않음은 물론이다.In the forming of the via 14, as shown in FIG. 4D, the insulating material 20 is drilled to expose the electrical contact 13a of the semiconductor chip 12a to drill the via hole 14a. 4, the first via 14 is formed by applying a process such as Cu sputtering, conductive paste filling, or the like to the surface to form a plating layer (124). As a result, the electrical contact 13a of the embedded semiconductor chip 12a may be electrically connected to the outside. It goes without saying that the drilling process used for drilling the via hole 14a and the plating process for electrically conducting the via hole 14a are not limited to the above-described embodiment.

다음으로, 절연재(20)에 빌드업층(30a)을 적층하고 빌드업층(30a)을 천공하여 제1 비아(14)와 전기적으로 연결되는 제2 비아(15)를 가공한다(126). 제2 비아(15)를 형성하는 공정으로 먼저, 도 4의 (f)에 도시된 바와 같이, 절연재(20)에 첫번째 빌드업층(30a)을 적층한다. 빌드업층(30a)은 절연성 재질로 이루어지며, 절연재(20)와 동일한 재료인 액상 PI를 도포하여 경화시키거나, PI 필름을 적층하여 구현할 수 있다.Next, the build-up layer 30a is stacked on the insulating material 20, and the build-up layer 30a is drilled to process the second via 15 electrically connected to the first via 14 (126). In the process of forming the second via 15, first, as shown in FIG. 4F, the first build-up layer 30a is laminated on the insulating material 20. The build-up layer 30a may be made of an insulating material, and may be formed by applying liquid PI, which is the same material as the insulating material 20, to be cured, or by stacking PI films.

다음으로, 도 4의 (g)에 도시된 바와 같이, 제1 비아(14)의 위치에서 첫번째 빌드업층(30a)을 드릴링하여 비아홀(15a)을 천공하고, 도 4의 (h)와 같이 비아홀(15a) 내면을 도금하여 제2 비아(15)를 형성한다. 이로써 반도체 칩(12a)의 전기접점(13a)으로부터의 전기적 연결 통로가 구현되는 비아를 형성할 수 있다.Next, as shown in FIG. 4G, the first build-up layer 30a is drilled at the position of the first via 14 to drill the via hole 15a, and the via hole is shown in FIG. 4H. An inner surface of the layer 15a is plated to form a second via 15. As a result, it is possible to form a via in which an electrical connection path from the electrical contact 13a of the semiconductor chip 12a is implemented.

이때, 빌드업층(30a)은 복수로 적층될 수 있으며, 제2 비아(15)는 복수의 빌드업층(30a)에 각각 가공되어 반도체 칩(12a)의 전기접점(13a)을 전기적으로 연결시킬 수 있다. 본 발명에서는 한층의 빌드업층(30a)에 제2 비아(15)를 형성하는 것을 실시예로 한다.In this case, the build-up layer 30a may be stacked in plural, and the second via 15 may be respectively processed in the plurality of build-up layers 30a to electrically connect the electrical contacts 13a of the semiconductor chip 12a. have. In the present invention, the second via 15 is formed in one build-up layer 30a.

다음으로, 도 4의 (i)에 도시된 바와 같이, 제2 비아(15)가 형성된 첫번째 빌드업층(30a)에 두번째 빌드업층(30b)을 적층시킨다. 두번째 빌드업층(30b)의 재질은 절연재(20) 및 첫번째 빌드업층(30a)의 재질과 동일한 재질이다. Next, as shown in FIG. 4I, the second buildup layer 30b is stacked on the first buildup layer 30a on which the second via 15 is formed. The material of the second build-up layer 30b is the same material as that of the insulating material 20 and the first build-up layer 30a.

반도체 칩(12a)상의 전기접점(13a)으로부터의 전기적 연결통로를 제1 비 아(14)를 통하여 구현하고, 빌드업층(30a)에 제2 비아(15)를 형성하여 제1 비아(14)와 제2 비아(15)가 전기적으로 연결된다. 따라서, 반도체 칩(12a)의 전기접점(13a)과 제2 비아(15)가 전기적으로 연결되는 제1 패키지(100)를 형성할 수 있다. An electrical connection path from the electrical contact 13a on the semiconductor chip 12a is realized through the first via 14, and a second via 15 is formed in the buildup layer 30a to form the first via 14. And the second via 15 are electrically connected. Accordingly, the first package 100 may be formed to electrically connect the electrical contact 13a of the semiconductor chip 12a and the second via 15 to each other.

다음으로, 반도체 칩 실장, 인캡슐레이팅 및 비아 형성을 소정 횟수 반복하여 반도체 칩이 스택된 구조를 이루도록 수행한다(130). 따라서, 반도체 칩 패턴 상부로부터 금속의 배선으로 빌드업(build-up) 기술을 사용하여 패키지(package)를 만들고, 그 상부에 반도체 칩을 실장한 후, 빌드업을 반복함으로써 사이즈의 최소화 가능한 NEW SIP(System In Package) 구조를 구현할 수 있다.Next, semiconductor chip mounting, encapsulation, and via formation are repeated a predetermined number of times to form a stacked structure of semiconductor chips (130). Therefore, a NEW SIP that can be minimized by making a package by using a build-up technique from the upper part of the semiconductor chip pattern by using a build-up technique, mounting the semiconductor chip on the upper part, and repeating the build up. (System In Package) structure can be implemented.

여기서, 본 발명에서의 '스택된'의 의미는 반도체 칩이 수직방향으로 쌓여 있는 구조임을 의미한다.Here, the term 'stacked' in the present invention means that the semiconductor chips are stacked in the vertical direction.

이와 같은 공정을 수행하기 위해, 먼저 도 4의 (j)와 같이, 제1 패키지(100)상의 두번째 빌드업층(30b)에 접착제(11)를 개재시켜 반도체 칩(12b)을 실장한다. 이때, 반도체 칩(12b)의 일면에 전기접점(13b)이 형성되는데, 전기접점(13b)이 없는 타면을 두번째 빌드업층(30b)에 접착시켜, 빌드업 기술을 적용한 전기접점(13a)의 전기적 연결을 구현 할 수 있다.In order to perform such a process, first, as shown in FIG. 4J, the semiconductor chip 12b is mounted on the second build-up layer 30b on the first package 100 with the adhesive 11 interposed therebetween. At this time, an electrical contact 13b is formed on one surface of the semiconductor chip 12b, and the other surface without the electrical contact 13b is adhered to the second buildup layer 30b to electrically connect the electrical contact 13a to which the buildup technology is applied. The connection can be implemented.

도 4의 (k)와 같이, 접착제(11)와 반도체 칩(12b)을 커버하도록 절연재(20)를 인캡슐레이팅하고, 도 4의 (l)과 같이 반도체 칩(12b)의 전기접점(13b)이 노출되도록 절연재(20)를 천공하여 비아홀(14a)을 가공한다. 이때, 절연재(20)의 재질은 상술한 반도체 칩(12a)을 인캡슐레이팅한 절연재(20)와 동일한 재질의 절연 재(20)이고, 비아홀(14a)의 가공 방법 또한 제1 패키지(100)의 비아홀(14a,15a)가공 방법과 동일하다.As shown in (k) of FIG. 4, the insulating material 20 is encapsulated to cover the adhesive 11 and the semiconductor chip 12b, and the electrical contact 13b of the semiconductor chip 12b as shown in FIG. The via hole 14a is processed by drilling the insulating material 20 so as to be exposed. In this case, the material of the insulating material 20 is an insulating material 20 of the same material as the insulating material 20 encapsulating the semiconductor chip 12a described above, and the processing method of the via hole 14a is also the first package 100. The via holes 14a and 15a are the same as the processing method.

다음으로, 도 4의 (m)과 같이, 비아홀(14a)의 내면을 도금하여 반도체 칩(12b)과 전기적으로 연결되는 통로를 구현할 수 있다. Next, as shown in (m) of FIG. 4, the inner surface of the via hole 14a may be plated to implement a passage electrically connected to the semiconductor chip 12b.

그 다음으로, 도 4의 (n)과 같이 반도체 칩(12b)과 전기적으로 연결되는 제1 비아(14)에 세번째 빌드업층(30a)을 적층하고, 도 4의 (o)에 도시된 바와 같이, 제1 비아(14)의 위치에서 비아홀(15a)을 천공한 후, 도 4의 (p)와 같이, 비아홀(15a)의 내면을 도금하여 제2 비아(15)를 형성한다. 따라서, 제1 비아(14)와 전기적으로 연결되는 제2 비아(15)를 구현할 수 있으며, 결과적으로 반도체 칩(12b)의 전기접점(13b)과 제2 비아(15)를 전기적으로 연결하는 제2 패키지(200)를 구현할 수 있다. Next, as shown in FIG. 4 (o), a third build-up layer 30a is stacked on the first via 14 electrically connected to the semiconductor chip 12b as shown in FIG. 4 (n). After the via hole 15a is drilled at the position of the first via 14, the inner surface of the via hole 15a is plated to form the second via 15 as shown in FIG. Accordingly, the second via 15 electrically connected to the first via 14 may be implemented. As a result, the second via 15 may be electrically connected to the electrical contact 13b of the semiconductor chip 12b and the second via 15. 2 package 200 may be implemented.

다음으로 도 4의 (q)와 같이 제2 비아(15)에 네번째 빌드업층(30b)을 적층할 수 있으며, 상술한 바와 같이, 복수의 빌드업층을 적층할 수 있으나, 본 발명에서는 한층의 빌드업층(30d)을 적층하는 것을 실시예로 한다. 하지만, 네번째 빌드업층(30b)에도 비아를 형성하여 복수의 빌드업층을 구현할 수 있음은 물론이다.Next, as shown in FIG. 4 (q), a fourth build-up layer 30b may be stacked on the second via 15. As described above, a plurality of build-up layers may be stacked, but in the present invention, a single build-up layer may be stacked. It is set as an example to laminate up layer 30d. However, it is a matter of course that a plurality of buildup layers may be implemented by forming vias in the fourth buildup layer 30b.

또한, 본 발명에서는 제1 패키지(100)와 제2 패키지(200)를 실시예로 설명하였으나, 두 층 이상의 패키지를 수직으로 스택 할 수 있음은 물론이다.In addition, in the present invention, the first package 100 and the second package 200 have been described as embodiments, but two or more packages may be stacked vertically.

제1 패키지(100)와 제2 패키지(200)가 형성되면, 제1 패키지(100)의 두번째 빌드업층(30b)에 형성된 제2 비아(15)와 제2 패키지(200)의 네번째 빌드업층(30b)에 형성된 제2 비아(15)를 전기적으로 연결시키는 관통비아(17)를 형성할 수 있 다(140). When the first package 100 and the second package 200 are formed, the second via 15 formed in the second buildup layer 30b of the first package 100 and the fourth buildup layer of the second package 200 ( Through-vias 17 for electrically connecting the second vias 15 formed in 30b) may be formed (140).

관통비아(17)를 형성하는 공정으로, 먼저 절연재(20)를 레이저 드릴링하여 천공한 후 관통홀(17a)을 형성한다(142). 이때, 도 4의 (r)과 같이 제1 패키지(100)와 제2 패키지(200)를 스택한 후, 한꺼번에 관통홀(17a)을 천공할 수 있으며, 각각의 제1 패키지(100)와 제2 패키지(200)의 관통홀(17a)을 천공한 후, 두 패키지를 스택 할 수도 있음은 물론이다. In the process of forming the through-vias 17, the through-hole 17a is formed by first drilling and drilling the insulating material 20 (142). In this case, after stacking the first package 100 and the second package 200 as shown in FIG. 4 (r), the through holes 17a may be drilled at a time, and each of the first package 100 and the first package 100 may be formed. After drilling the through hole 17a of the two packages 200, the two packages may be stacked, of course.

다음으로, 도 4의 (s)와 같이, 천공된 관통홀(17a)내에 도전성 페이스트로 충전하여 비아(14,15)간의 전기적 연결을 구현하는 관통비아(17)를 형성할 수 있다(144). 따라서, 제1 패키지(100)의 반도체 칩(12a)과 제2 패키지(200)의 반도체 칩(12b)간의 전기적 도통을 구현할 수 있는 전자 패키지를 형성할 수 있다. Next, as shown in (s) of FIG. 4, through holes 17a may be filled with conductive paste to form through vias 17 for electrical connection between vias 14 and 15 (144). . Therefore, an electronic package capable of implementing electrical conduction between the semiconductor chip 12a of the first package 100 and the semiconductor chip 12b of the second package 200 may be formed.

이로써, 빌드업 공법 및 패키지 스택을 통한 NEW SIP(system in package) 구조를 실현할 수 있으며, 빌드업 구조를 통한 CSP(chip scale package)의 신뢰도를 향상 시킬 수 있다.As a result, a new SIP (system in package) structure can be realized through a buildup method and a package stack, and reliability of a chip scale package (CSP) can be improved through the buildup structure.

마지막으로, 관통비아(17)와 전기적으로 연결되는 범프(40)를 형성한다(150). 그 공정으로, 도 4의 (t)에 도시된 바와 같이, 제2 패키지(200)의 빌드업층(30b)에 노출되는 관통비아(17)의 표면에 솔더볼(solder ball) 등의 도전성 범프(40)를 결합하여 전자 패키지와 외부 장치와의 전기적 연결을 위한 접점을 형성한다.Finally, the bump 40 is formed to be electrically connected to the through via 17 (150). In the process, as illustrated in FIG. 4T, conductive bumps such as solder balls 40 are formed on the surface of the through via 17 exposed to the buildup layer 30b of the second package 200. ) To form contacts for electrical connection between the electronic package and the external device.

도 5는 본 발명의 바람직한 일 실시예에 따른 전자 패키지를 나타낸 단면도 이다. 도 5를 참조하면, 방열판(10), 접착제(11), 반도체 칩(12a, 12b), 전기접점(13a, 13b), 제1 비아(14), 비아홀(14a, 15a), 제2 비아(15), 관통비아(17), 관통홀(17a), 절연재(20), 빌드업층(30a, 30b), 범프(40), 제1 패키지(100), 제2 패키지(200)가 도시되어 있다.5 is a cross-sectional view illustrating an electronic package according to an exemplary embodiment of the present invention. Referring to FIG. 5, the heat sink 10, the adhesive 11, the semiconductor chips 12a and 12b, the electrical contacts 13a and 13b, the first via 14, the via holes 14a and 15a, and the second via ( 15, through vias 17, through holes 17a, insulation 20, buildup layers 30a and 30b, bumps 40, first package 100, and second package 200 are shown. .

본 발명은 방열판(10) 상에 복수로 스택되는 단위 패키지를 포함하는 전자 패키지로서, 단위 패키지(100, 200)는 반도체 칩(12a, 12b)과 절연재(20) 및 제1 비아(14)를 포함한다. The present invention provides an electronic package including a plurality of unit packages stacked on the heat sink 10, and the unit packages 100 and 200 may include the semiconductor chips 12a and 12b, the insulating material 20, and the first vias 14. Include.

반도체 칩(12a)은 전기접점(13a)이 형성된 일면이 윗쪽을 향하도록 방열판(10)에 실장되는데, 다시 말해서, 반도체 칩(12a)의 타면이 방열판(10)에 실장된다. 또한, 반도체 칩(12a)과 방열판(10) 사이에 접착제(11)를 개재시켜 접착시킨다. The semiconductor chip 12a is mounted on the heat sink 10 so that one surface on which the electrical contact 13a is formed faces upward. In other words, the other surface of the semiconductor chip 12a is mounted on the heat sink 10. Further, the adhesive 11 is bonded between the semiconductor chip 12a and the heat sink 10 with the adhesive 11 interposed therebetween.

반도체 칩(12a)의 하부에 방열판(Heat spreader)(10)이 부착되어 있어 반도체 칩(12a)으로부터 발생되는 열을 보다 효율적으로 방출시킬 수 있으며, 방열판(10)에 반도체 칩(12a) 실장 및 빌드업층(30a, 30b)에 반도체 칩(12b)을 스택하는 공정은 반도체 칩의 실장을 위한 복잡한 공정 대신 단순히 접착제(11)를 사용하여 칩을 접합하는 공정으로 수행될 수 있어 저렴하고 신속하게 진행될 수 있다.The heat spreader 10 is attached to the lower portion of the semiconductor chip 12a, so that heat generated from the semiconductor chip 12a can be more efficiently discharged, and the semiconductor chip 12a is mounted on the heat sink 10 and The stacking process of the semiconductor chip 12b on the buildup layers 30a and 30b may be performed by simply bonding the chip using the adhesive 11 instead of the complicated process for mounting the semiconductor chip. Can be.

절연재(20)는 방열판(10)에 도포되며, 반도체 칩(12a, 12b)에 액상의 PI 레진(resin)을 도포하여 인캡슐레이팅 할 수 있다. 반도체 칩(12a)의 몰딩은 EMC(Epoxy molding compound) 등 기존의 몰딩재로 인캡슐레이팅할 수도 있으며 빌드업층(30a, 30b)의 재질과 동일한 PI 레진 등을 사용하면 반도체 칩 인캡슐레이팅 공정과 빌드업 공정을 동일한 프로세스로 진행할 수 있어 공정이 단순하고, 재료 간의 물성차이로 인한 패키지의 에러를 방지할 수 있다.The insulating material 20 is applied to the heat sink 10, and can be encapsulated by applying a liquid PI resin (resin) to the semiconductor chips 12a and 12b. The molding of the semiconductor chip 12a may be encapsulated with an existing molding material such as an epoxy molding compound (EMC). If the same PI resin is used as the material of the buildup layers 30a and 30b, the semiconductor chip 12a may be encapsulated. The build-up process can be carried out in the same process, so the process is simple and the package can be prevented due to material differences between materials.

제1 비아(14)는 절연재(20)에 관삽되어 전기접점(13a)과 전기적으로 연결될 수 있다. 한편, 제1 비아(14)의 가공방법은 상술한 바와 같다. 따라서, 반도체 칩(12a)의 일면에 형성된 전기접점(13a)과 전기적으로 연결되는 제1 비아(14)를 포함하는 제1 패키지(100)를 형성할 수 있다.The first via 14 may be inserted into the insulating material 20 to be electrically connected to the electrical contact 13a. In addition, the processing method of the 1st via 14 is as above-mentioned. Accordingly, the first package 100 including the first via 14 electrically connected to the electrical contact 13a formed on one surface of the semiconductor chip 12a may be formed.

또한, 단위 패키지(100, 200)는 절연재(20)에 적층되는 빌드업층(30a)과, 빌드업층(30a)에 관삽되어 제1 비아(14)와 전기적으로 연결되는 제2 비아(15)를 포함할 수 있다. 이로써, 반도체 칩(12a)으로부터의 전기적 연결통로(electrical path)는 반도체 칩(12a)의 전기접점(13a)으로부터 빌드업 공정을 진행하여 구현되므로 보다 미세한 피치의 구현이 가능하다.In addition, the unit packages 100 and 200 may include a buildup layer 30a stacked on the insulating material 20 and a second via 15 inserted into the buildup layer 30a and electrically connected to the first via 14. It may include. As a result, the electrical path from the semiconductor chip 12a is implemented by performing a build-up process from the electrical contact 13a of the semiconductor chip 12a, thereby enabling a finer pitch.

이때, 빌드업층(30a)는 복수로 적층될 수 있으며, 제2 비아(15)는 복수의 빌드업층(30a)에 각각 가공되어 서로 전기적으로 연결되도록 복수로 형성될 수 있다.In this case, the build-up layer 30a may be stacked in plural, and the second via 15 may be formed in plural to be processed in the plurality of build-up layers 30a and electrically connected to each other.

보다 구체적으로, 제1 패키지(100)에 반도체 칩(12b)의 타면이 수직으로 스택되며, 반도체 칩(12b)의 일면에 형성된 전기접점(13b)과 전기적으로 연결되는 제2 비아(15)를 포함하는 제2 패키지(200)를 형성할 수 있다. More specifically, the other surface of the semiconductor chip 12b is vertically stacked on the first package 100, and the second via 15 is electrically connected to the electrical contact 13b formed on one surface of the semiconductor chip 12b. The second package 200 may be included.

따라서, 본 실시예에 따른 전자 패키지는 방열판(10)에 반도체 칩(12a)이 적층되고, 제1 패키지(100)에 반도체 칩(12b)이 순차적으로 적층되어 반도체 칩(12a, 12b)이 수직으로 스택된 구조를 이룰 수 있다. Therefore, in the electronic package according to the present exemplary embodiment, the semiconductor chips 12a are stacked on the heat sink 10, and the semiconductor chips 12b are sequentially stacked on the first package 100 so that the semiconductor chips 12a and 12b are vertical. A stacked structure can be achieved.

이로써, 본 발명은 종래 빌드업 공법을 적용한 SIP에서 복수의 칩을 실장할 때 수평 정렬 방식으로 실장해야 함으로써 패턴 사이즈를 최소화하기 곤란하다는 문제를 극복할 수 있다.Thus, the present invention can overcome the problem that it is difficult to minimize the pattern size by mounting in a horizontal alignment method when mounting a plurality of chips in SIP to which the conventional build-up method.

본 발명에 따른 전자 패키지의 실시예는 먼저, 제1 비아(14)에 빌드업층(30a)을 적층하고, 빌드업층(30a)을 천공함으로써 제1 비아(14)와 전기적으로 연결되는 제2 비아(15)를 구현하는 제1 패키지(100)를 형성한다. In an embodiment of the electronic package according to the present invention, first, the build-up layer 30a is stacked on the first via 14, and the second via is electrically connected to the first via 14 by drilling the build-up layer 30a. The first package 100 implementing the (15) is formed.

다음으로, 제1 패키지(100)에 제1 패키지(100)와 동일한 방법으로 제조된 제2 패키지(200)를 수직으로 스택하고, 절연재(20)를 관통함으로써, 복수의 제1 비아(14)를 전기적으로 연결하는 관통비아(17)를 형성할 수 있다. Next, the second package 200 manufactured by the same method as the first package 100 is vertically stacked on the first package 100, and the plurality of first vias 14 are penetrated through the insulating material 20. Through vias 17 may be formed to electrically connect the vias.

또한, 제2 패키지(200)의 표면에 결합되며, 관통비아(17)와 전기적으로 연결되는 도전성 범프(40)를 더 포함할 수 있다. 즉, 전자 패키지를 외부 장치에 SMT(surface mount technology) 실장 등을 통해 연결하기 위해 빌드업층(30b)의 표면에 솔더볼 등의 도전성 범프(40)를 결합한다. 도전성 범프(40)는 빌드업층(30b)에 형성된 제2 비아(15)와 전기적으로 연결되어 전자 패키지와 외부 장치 간의 전기적 연결을 위한 접점을 이루게 된다.In addition, the semiconductor package may further include a conductive bump 40 coupled to the surface of the second package 200 and electrically connected to the through via 17. That is, the conductive bumps 40 such as solder balls are coupled to the surface of the build-up layer 30b to connect the electronic package to an external device through surface mount technology (SMT) mounting. The conductive bumps 40 are electrically connected to the second vias 15 formed in the buildup layer 30b to form contacts for electrical connection between the electronic package and the external device.

도 6은 본 발명의 바람직한 다른 실시예에 따른 전자 패키지를 나타낸 단면도이다. 도 6을 참조하면, 방열판(10), 접착제(11), 반도체 칩(12a, 12b), 전기접점(13a, 13b), 제1 비아(14), 비아홀(14a, 15a), 제2 비아(15), 관통비아(17), 관통홀(17a), 절연재(20), 빌드업층(30a, 30b), 범프(40), 제1 패키지(100), 제2 패키지(200)가 도시되어 있다.6 is a cross-sectional view illustrating an electronic package according to another exemplary embodiment of the present invention. Referring to FIG. 6, the heat sink 10, the adhesive 11, the semiconductor chips 12a and 12b, the electrical contacts 13a and 13b, the first via 14, the via holes 14a and 15a, and the second via ( 15, through vias 17, through holes 17a, insulation 20, buildup layers 30a and 30b, bumps 40, first package 100, and second package 200 are shown. .

도 6을 참조하면, 도 5의 전자 패키지를 수직방향으로 다섯 층 스택하여 구성된 전자 패키지를 나타낸 것이다. 본 실시예에 따르면, 반도체 칩(12a, 12b)을 수직으로 스택한 구조이므로 종래 수평방식으로 반도체 칩을 실장할 때 보다 패턴 사이즈를 줄일 수 있다. 또한, 빌드업층을 형성함으로써, 반도체 칩의 전기접점을 연결할 수 있는 미세패턴을 형성할 수 있어, CSP의 신뢰도를 향상시킬 수 있다.Referring to FIG. 6, an electronic package configured by stacking the electronic package of FIG. 5 in a vertical direction is illustrated. According to the present exemplary embodiment, since the semiconductor chips 12a and 12b are stacked vertically, the pattern size can be reduced compared to when the semiconductor chip is mounted in a conventional horizontal method. In addition, by forming the build-up layer, it is possible to form a fine pattern that can connect the electrical contact of the semiconductor chip, it is possible to improve the reliability of the CSP.

또한, 패키지(100, 200)간의 전기적 연결을 구현하는 통로인 관통비아(17)는 각 패키지에 관통비아(17)를 형성한 후 스택 할 수 있을 뿐만 아니라, 전체 패키지에 관통비아(17)를 형성하여 전기적 연결을 구현할 수 도 있다. 또한, 중간 부분의 패키지만을 전기적으로 연결하는 부분 관통비아를 형성할 수 있음은 물론이다. In addition, the through via 17, which is a passage for implementing an electrical connection between the packages 100 and 200, may not only be stacked after forming the through vias 17 in each package, but also the through vias 17 may be formed in the entire package. It can also be formed to implement the electrical connection. In addition, it is of course possible to form a partial through via for electrically connecting only the package of the intermediate portion.

전술한 실시예 외의 많은 실시예들이 본 발명의 특허청구범위 내에 존재한다.Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

상술한 바와 같이 본 발명의 바람직한 실시예에 따르면, 반도체 칩을 수직으로 스택한 구조이므로 종래 수평방식으로 반도체 칩을 실장할 때 보다 패턴 사이즈의 최소화 가능한 NEW SIP(System In Package) 구조를 구현할 수 있다. 또한, 빌드업층을 형성함으로써, 반도체 칩의 전기접점을 연결할 수 있는 미세패턴을 형성할 수 있어, CSP(chip scale package)의 신뢰도를 향상시킬 수 있다.As described above, according to the preferred embodiment of the present invention, since the semiconductor chips are stacked vertically, a NEW SIP (System In Package) structure capable of minimizing the pattern size can be realized when mounting the semiconductor chips in a conventional horizontal method. . In addition, by forming the build-up layer, it is possible to form a fine pattern that can connect the electrical contact of the semiconductor chip, it is possible to improve the reliability of the chip scale package (CSP).

Claims (16)

일면에 전기접점이 형성된 반도체 칩(chip)을 실장하는 단계;Mounting a semiconductor chip having an electrical contact formed on one surface thereof; 절연재를 도포하여 상기 반도체 칩을 인캡슐레이팅(encapsulating)하는 단계; Encapsulating the semiconductor chip by applying an insulating material; 상기 절연재를 천공하여 상기 전기접점과 전기적으로 연결되는 비아(via)를 형성하는 단계; Perforating the insulation to form vias electrically connected to the electrical contacts; 상기 반도체 칩이 스택된 구조를 이루도록, 상기 실장 단계 내지 상기 비아 형성 단계를 소정 횟수 반복하여 상기 반도체 칩과 상기 절연재와 상기 비아를 포함하는 단위패키지를 복수로 스택하는 단계; 및Stacking a plurality of unit packages including the semiconductor chip, the insulating material, and the via by repeating the mounting step to the via forming step a predetermined number of times to form a stacked structure of the semiconductor chip; And 상기 비아와 전기적으로 연결되는 범프를 결합하는 단계를 포함하는 전자 패키지 제조방법.Coupling the bumps electrically connected to the vias. 제1항에 있어서,The method of claim 1, 상기 실장 단계 이전에, 상기 반도체 칩이 실장되는 방열판(heat spreader)을 제공하는 단계를 더 포함하는 전자 패키지 제조방법.And providing a heat spreader on which the semiconductor chip is mounted before the mounting step. 제2항에 있어서,The method of claim 2, 상기 실장 단계는, 상기 반도체 칩과 상기 방열판 사이에 접착제(adhesive)를 개재시켜 상기 반도체 칩을 상기 방열판에 접착시키는 단계를 포함하는 것을 특 징으로 하는 전자 패키지 제조방법.The mounting step of the electronic package manufacturing method comprising the step of adhering the semiconductor chip to the heat sink through the adhesive (adhesive) between the semiconductor chip and the heat sink. 제1항에 있어서,The method of claim 1, 상기 인캡슐레이팅 단계는, 상기 반도체 칩을 커버하도록 상기 방열판에 액상의 수지를 도포하고 소성(curing)시키는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.The encapsulating step includes the step of applying a liquid resin to the heat sink to cover the semiconductor chip and baking (curing). 제1항에 있어서,The method of claim 1, 상기 비아 형성 단계는,The via forming step, (a) 상기 전기접점이 노출되도록 상기 절연재를 드릴링(drilling)하여 비아홀(via hole)을 천공하는 단계; 및(a) drilling a via hole by drilling the insulation to expose the electrical contact; And (b) 상기 비아홀의 표면을 도금(plating)하여 제1 비아를 형성하는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.(b) forming a first via by plating the surface of the via hole. 제5항에 있어서,The method of claim 5, 상기 단계 (b) 이후에,After step (b), 상기 절연재에 빌드업(build-up)층을 적층하고 상기 빌드업층을 천공하여 상 기 제1 비아와 전기적으로 연결되는 제2 비아를 가공하는 빌드업 단계를 더 포함하는 것을 특징으로 하는 전자 패키지 제조방법.Lay-up build-up (Layer-up) layer on the insulating material and perforated the build-up layer further comprises a build-up step of processing a second via electrically connected to the first via Way. 제6항에 있어서,The method of claim 6, 상기 빌드업층은 복수로 적층되고, 상기 제2 비아는 복수의 상기 빌드업층에 각각 가공되는 것을 특징으로 하는 전자 패키지 제조방법.The build-up layer is stacked in plural, the second via is a method for manufacturing an electronic package, characterized in that each of the plurality of build-up layer is processed. 삭제delete 제1항에 있어서,The method of claim 1, 상기 반도체 칩은 접착제를 개재하여 상기 절연재에 접착되는 것을 특징으로 하는 전자 패키지 제조방법.The semiconductor chip manufacturing method of the electronic package, characterized in that bonded to the insulating material via an adhesive. 제1항에 있어서,The method of claim 1, 상기 반복 단계와 상기 범프 결합하는 단계 사이에,Between the repeating step and the step of bump coupling, 복수의 상기 비아를 전기적으로 연결하는 관통비아를 형성하는 단계를 더 포함하는 전자 패키지 제조방법.And forming through vias electrically connecting the plurality of vias. 제10항에 있어서,The method of claim 10, 상기 관통비아 형성 단계는,The through via forming step, 상기 절연재를 천공하여 관통홀을 형성하는 단계; 및Drilling the insulating material to form a through hole; And 상기 관통홀 내에 도전성 페이스트를 충전하는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.And filling a conductive paste into the through hole. 단위 패키지는,Unit package, 전기접점이 형성된 일면이 윗쪽을 향하도록 실장되는 반도체 칩(chip)과;A semiconductor chip mounted on one surface of which an electrical contact is formed to face upward; 상기 반도체 칩을 인캡슐레이팅(encapsulating)하는 절연재; 및An insulating material encapsulating the semiconductor chip; And 상기 절연재에 관삽되어 상기 전기접점과 전기적으로 연결되는 제1 비아(via)를 포함하며,A first via inserted into the insulating material and electrically connected to the electrical contact, 상기 단위 패키지는, 방열판(Heat spreader) 상에 복수로 스택(stack)되는 것을 특징으로 하는 전자 패키지.The unit package is stacked on a heat spreader (Heat spreader) characterized in that the stack (stack) a plurality. 제12항에 있어서,The method of claim 12, 상기 절연재를 관통하여 형성되며, 복수의 상기 제1 비아를 전기적으로 연결하는 관통비아를 더 포함하는 전자 패키지.And a through via formed through the insulating material and electrically connecting the plurality of first vias. 제13항에 있어서,The method of claim 13, 상기 전자 패키지의 표면에 결합되며, 상기 관통비아와 전기적으로 연결되는 도전성 범프(bump)를 더 포함하는 전자 패키지.And a conductive bump coupled to a surface of the electronic package and electrically connected to the through via. 제12항에 있어서,The method of claim 12, 상기 단위 패키지는,The unit package, 상기 절연재에 적층되는 빌드업층과;A buildup layer laminated on the insulating material; 상기 빌드업층에 관삽되어 상기 제1 비아와 전기적으로 연결되는 제2 비아를 더 포함하는 것을 특징으로 하는 전자 패키지.And a second via inserted into the build up layer and electrically connected to the first via. 제15항에 있어서,The method of claim 15, 상기 빌드업층은 복수로 적층되고, 상기 제2 비아는 복수의 상기 빌드업층에 각각 가공되어 서로 전기적으로 연결되도록 복수로 형성되는 것을 특징으로 하는 전자 패키지.The build-up layer is stacked in plural, the second via is a plurality of electronic packages, characterized in that formed in plurality to be processed in each of the build-up layer and electrically connected to each other.
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