KR100800760B1 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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KR100800760B1
KR100800760B1 KR1020060130625A KR20060130625A KR100800760B1 KR 100800760 B1 KR100800760 B1 KR 100800760B1 KR 1020060130625 A KR1020060130625 A KR 1020060130625A KR 20060130625 A KR20060130625 A KR 20060130625A KR 100800760 B1 KR100800760 B1 KR 100800760B1
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gate electrode
silicide
semiconductor device
manufacturing
sidewall spacer
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KR1020060130625A
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Korean (ko)
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정민호
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to prevent generation of a bridge inducing a short between a gate electrode and a source/drain impurity diffusion region by performing a silicide annealing process after nitrogen ions are implanted. A transistor is formed on a semiconductor substrate(101). The transistor is configured with a gate electrode(104) and a source/drain impurity diffusion region(107). A sidewall spacer(106) is formed on the gate electrode. Nitrogen ions are implanted into the sidewall spacer, and then a silicide annealing process is performed on the sidewall spacer to transform a silicide in the sidewall spacer into a nitride. An implantation angle of the nitrogen ion is tilted. The nitride on the sidewall spacer is removed by using H2SO4. The nitrogen ion is implanted into 40 Å to 60 Å deep from a surface of the sidewall spacer.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

도 1a 내지 도 1g는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

101 : 반도체 기판 102 : 소자 격리막101 semiconductor substrate 102 device isolation film

103 : 게이트 절연막 104 : 게이트 전극103: gate insulating film 104: gate electrode

105 : LDD 영역 106 : 절연막 측벽105: LDD region 106: insulating film sidewall

107 : 소오스/드레인 불순물 확산영역 108 : 금속 실리사이드막107 source / drain impurity diffusion region 108 metal silicide film

109 : 층간 절연막 110 : 콘택홀109: interlayer insulating film 110: contact hole

111 : 베리어 금속막 111: barrier metal film

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는 게이트 전극의 측벽 스페이서에 잔존하는 실리사이드를 제거함으로써 게이트 전극과 소스/드레인간의 쇼트(short)를 방지하는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device which prevents short between gate electrode and source / drain by removing silicide remaining in the sidewall spacer of the gate electrode. .

일반적으로, 반도체 소자를 제조하기 위한 공정에서 반도체 기판상에 게이트 전극을 형성 후 게이트 전극 양측면에 측벽 스페이서(side wall spacer 또는 side wall nitride)를 형성한다.In general, a gate electrode is formed on a semiconductor substrate in a process for manufacturing a semiconductor device, and sidewall spacers or side wall nitrides are formed on both sides of the gate electrode.

반도체 소자 제조공정에서 콘택 저항을 낮추기 위해서 콘택(contact)이 형성될 곳에 메탈을 증착한 후 어닐(anneal) 등의 후속 공정을 진행하여 실리사이드를 형성하게 되는데, 이 때 측벽 스페이서의 실리콘(Si)과 메탈 원자의 결합으로 인해서 실리사이드(silicide)가 미세하게 형성하게 된다.In the semiconductor device manufacturing process, in order to lower contact resistance, metal is deposited at a place where a contact is to be formed, and then a silicide is formed by a subsequent process such as annealing, wherein silicon (Si) of the sidewall spacer and Due to the bonding of the metal atoms, silicide is finely formed.

한편, 반도체 소자의 집적도 향상과 전력소모를 줄이기 위한 인가 전압의 감소로 인하여 게이트 전극의 두께가 점점 감소되고 있다.On the other hand, the thickness of the gate electrode is gradually reduced due to the reduction of the applied voltage for improving the integration density and power consumption of the semiconductor device.

그러나, 이와 같이, 게이트 전극의 두께가 감소할수록 측벽 스페이서에 잔존하는 실리사이드(silicide)가 게이트 전극과 소스(source)/드레인(drain) 영역간의 쇼트(short)를 유발하는 브릿지를 형성하게 됨으로써 반도체 소자의 결함을 유발시키는 문제점을 발생시킨다. However, as the thickness of the gate electrode decreases, the silicide remaining in the sidewall spacer forms a bridge that causes a short between the gate electrode and the source / drain region. Causes a problem that causes a defect.

본 발명은 상술한 종래의 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 게이트 전극의 측벽 스페이서에 잔존하는 실리사이드를 제거함으로써 게이트 전극과 소스/드레인간의 쇼트(short)를 유발하는 브릿지의 형성을 차단시키며, 이로 인해 반도체 소자의 결함을 방지하는 반도체 소자의 제조방법을 제공하는데 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to remove the silicide remaining in the sidewall spacers of the gate electrode, thereby preventing the formation of a bridge causing short between the gate electrode and the source / drain. The present invention provides a method of manufacturing a semiconductor device that prevents defects of the semiconductor device.

이와 같은 목적을 실현하기 위한 본 발명은, 반도체 소자의 제조방법에 있어서, 반도체 기판에 게이트 전극과 소오스/드레인 불순물 확산영역을 포함하여 이루어지는 트랜지스터를 형성하는 단계와, 게이트 전극에 형성되는 측벽 스페이서에 질소 이온을 주입한 다음, 실리사이드 어닐(silicide anneal)을 실시함으로써 측벽 스페이서에 존재하는 실리사이드를 나이트라이드화하는 단계와, 측벽 스페이서에 존재하는 나이트라이드(nitride)를 황산(H2SO4)을 이용하여 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising: forming a transistor including a gate electrode and a source / drain impurity diffusion region in a semiconductor substrate; Injecting nitrogen ions, and then performing a silicide anneal to nitride the silicides present in the sidewall spacers, and to the nitrides present in the sidewall spacers using sulfuric acid (H 2 SO 4 ). It characterized in that it comprises a step of removing.

이하, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 본 발명의 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 더욱 상세히 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

도 1a 내지 도 1g는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다. 도시된 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판에 게이트 전극과 소오스 및 드레인 불순물 확산 영역을 포함하여 이루어지는 트랜지스터를 형성하는 단계와, 게이트 전극의 측벽 스페이서(side wall spacer)에 질소 이온을 주입함과 아울러 실리사이드 어닐(silicide anneal)을 실시하여 실리사이드(silicide)를 나이트라이드(nitride)화 하는 단계와, 측벽 스페이서에 존재하는 나이트라이드(nitride)를 황산(H2SO4)으로 제거하는 단계를 포함한다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention. As shown, the method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a transistor comprising a gate electrode and a source and drain impurity diffusion regions in a semiconductor substrate, and nitrogen in the side wall spacers of the gate electrode; Injecting ions and performing silicide anneal to nitride the silicide, and remove the nitride present in the sidewall spacer with sulfuric acid (H 2 SO 4 ). It includes a step.

반도체 기판에 트랜지스터를 형성하는 단계는 도 1a 내지 도 1c에 도시된 바와 같으며, 이를 상세히 설명하면 다음과 같다.Forming the transistor on the semiconductor substrate is as shown in Figures 1a to 1c, described in detail as follows.

도 1a에 도시한 바와 같이, 반도체 기판(101)의 소정영역에 STI(Shallow Trench Isolation) 구조를 갖는 소자분리막(102)을 형성한다. 여기서 소자분리 막(102)은 반도체 기판에 소정깊이를 갖는 트랜치를 형성한 후, 트랜치 내부에 갭-필(Gap-fill) 물질을 매립하여 형성한다.As shown in FIG. 1A, an isolation layer 102 having a shallow trench isolation (STI) structure is formed in a predetermined region of the semiconductor substrate 101. The device isolation layer 102 is formed by forming a trench having a predetermined depth in the semiconductor substrate and then filling a gap-fill material in the trench.

그런 다음, 소자분리막(102)을 포함한 반도체 기판(101)의 전면에 게이트 절연막(103)을 형성하고, 게이트 절연막(103)상에 폴리 실리콘층(도시되지 않음)을 형성한다.Then, a gate insulating film 103 is formed on the entire surface of the semiconductor substrate 101 including the device isolation film 102, and a polysilicon layer (not shown) is formed on the gate insulating film 103.

이러한 폴리 실리콘층 및 게이트 절연막(103)에 사진석판술 및 식각공정을 실시하여 선택적으로 패터닝함으로써 소자분리막(102)사이의 반도체 기판(101)상에 게이트 전극(104)을 형성한다.Photolithography and etching are performed on the polysilicon layer and the gate insulating layer 103 to selectively pattern the gate electrode 104 on the semiconductor substrate 101 between the device isolation layers 102.

도 1b에 도시한 바와 같이, 게이트 전극(104)을 마스크로 이용하여 반도체 기판(101)의 전면에 저농도 불순물 이온을 주입하여 게이트 전극(104) 양측의 반도체 기판(101) 표면내에 LDD(Lightly Doped Drain)영역(105)을 형성한다.As shown in FIG. 1B, low concentration impurity ions are implanted into the entire surface of the semiconductor substrate 101 using the gate electrode 104 as a mask to lightly doped the surface of the semiconductor substrate 101 on both sides of the gate electrode 104. Drain) region 105 is formed.

그런 다음, 게이트 전극(104)을 포함한 반도체 기판(101)의 전면에 절연막을 형성한다. 여기서, 절연막은 실리콘 산화막 또는 실리콘 질화막을 사용한다.Then, an insulating film is formed on the entire surface of the semiconductor substrate 101 including the gate electrode 104. Here, the insulating film uses a silicon oxide film or a silicon nitride film.

그리고, 절연막의 전면에 에치백(etch back) 공정을 실시하여 게이트 전극(104)의 양측면에 측벽 스페이서(106)를 형성한다.Then, an etch back process is performed on the entire surface of the insulating film to form sidewall spacers 106 on both sides of the gate electrode 104.

그런 다음, 측벽 스페이서(106) 및 게이트 전극(104)을 마스크로 이용하여 반도체 기판(101)의 전면에 소오스/드레인용 불순물 이온을 주입하여 게이트 전극(104) 양측의 반도체 기판(101) 표면내에 LDD영역(105)과 연결되는 소오스/드레인 불순물 확산영역(107)을 형성한다.Then, source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 101 using the sidewall spacers 106 and the gate electrode 104 as masks, so as to be in the surface of the semiconductor substrate 101 on both sides of the gate electrode 104. A source / drain impurity diffusion region 107 connected to the LDD region 105 is formed.

도 1c에 도시한 바와 같이, 게이트 전극(104)을 포함한 반도체 기판(101)의 전면에 Ti, Co 등의 고융점 금속을 증착한 후, 전면에 500도씨에서 30초정도 RTA 열처리 공정을 실시하여 게이트 전극(104)과 소오스/드레인 불순물 확산영역(107)의 표면에 Ti, Co 등의 금속 실리사이드막(108)을 형성한다.As shown in FIG. 1C, after depositing a high melting point metal such as Ti or Co on the entire surface of the semiconductor substrate 101 including the gate electrode 104, an RTA heat treatment process is performed on the entire surface at 500 ° C. for about 30 seconds. Metal silicide films 108 such as Ti and Co are formed on the surfaces of the gate electrode 104 and the source / drain impurity diffusion region 107.

게이트 전극의 측벽 스페이서(side wall spacer)에 존재하는 실리사이드(silicide)를 나이트라이드(nitride)화 하는 단계는 도 1d에 도시한 바와 같이, 일정 에너지, 바람직하게는 10KeV의 에너지로 질소 이온을 주입하고, 870도씨에서 30초정도 RTA 실리사이드 어닐(silicide anneal)을 실시하여, TiSi2, CoSi2 등의 실리사이드(S)를 TiN, CoN 등의 나이드라이드로 변화시킨다.Nitriding the silicide present in the side wall spacers of the gate electrode is performed by implanting nitrogen ions at a constant energy, preferably 10 KeV, as shown in FIG. , RTA silicide anneal for about 30 seconds at 870 ° C. to change silicides (S) such as TiSi 2 and CoSi 2 to nitrides such as TiN and CoN.

한편, 실리사이드를 나이트라이드화하는 단계에서 질소 이온의 주입시 질소 이온의 주입 각도가 틸트(tilt)되도록 함이 바람직하다. 따라서, 질소 이온이 경사지게 형성되는 측벽 스페이서(106) 전체에 걸쳐서 균일하게 주입되도록 한다.On the other hand, in the step of nitriding the silicide, the injection angle of the nitrogen ions during the injection of the nitrogen ions is preferably such that the tilt (tilt). Therefore, the nitrogen ions are uniformly injected throughout the sidewall spacers 106 formed to be inclined.

또한, 실리사이드를 나이트라이드화하는 단계에서 질소 이온을 주입시 측벽 스페이서(106)의 표면으로부터 40Å 내지 60Å까지, 바람직하게는 50Å까지 질소 이온이 주입되도록 함이 바람직하다. 따라서, 측벽 스페이서(106)에 영향을 최소화하면서 측벽 스페이서(106)에 존재하는 실리사이드(S)에 질소 이온이 깊숙이 주입되도록 한다.In addition, in the step of nitriding the silicide, it is preferable to inject nitrogen ions to 40 kPa to 60 kPa, preferably 50 kPa from the surface of the sidewall spacer 106 when the nitrogen ions are implanted. Therefore, nitrogen ions are deeply implanted into the silicide S present in the sidewall spacers 106 while minimizing the influence on the sidewall spacers 106.

나이트라이드(nitride)를 황산(H2SO4)으로 제거하는 단계는 황산 용액을 이용하여 측벽 스페이서(106)에 부착된 나이트라이드를 제거하여 도 1e에 도시된 바와 같이, 측벽 스페이서(106)의 표면에 잔류물이 존재하지 않도록 하며, 이 때, 게 이트 전극(104)과 소오스/드레인 불순물 확산영역(107)에 존재하는 적은 양의 나이트라이드도 제거하게 된다. Removing the nitride with sulfuric acid (H 2 SO 4 ) may be performed by removing the nitride attached to the side wall spacer 106 using a sulfuric acid solution, as shown in FIG. 1E. Residue does not exist on the surface, and a small amount of nitride present in the gate electrode 104 and the source / drain impurity diffusion region 107 is removed.

측벽 스페이서(106)에 부착된 나이트라이드화된 실리사이드를 제거하면, 도 1f에 도시된 바와 같이, 반도체 기판(101)의 전면에 층간 절연막(109)을 형성한다. 여기서, 층간 절연막(109)은 USG(Undoped Silicate Glass) 또는 BPSG와 같은 옥사이드 또는 나이트라이드를 사용한다.When the nitrided silicide attached to the sidewall spacers 106 is removed, an interlayer insulating film 109 is formed on the entire surface of the semiconductor substrate 101 as shown in FIG. 1F. Here, the interlayer insulating film 109 uses an oxide or nitride such as USG (Undoped Silicate Glass) or BPSG.

그런 다음, 소오스 및 드레인 불순물 확산영역(107)의 표면이 소정부분 노출되도록 층간 절연막(109)을 선택적으로 제거하여 콘택홀(110)을 형성한다.Thereafter, the interlayer insulating layer 109 is selectively removed so that the surfaces of the source and drain impurity diffusion regions 107 are partially exposed to form the contact holes 110.

도 1e에 도시한 바와 같이, 콘택홀(110)을 포함한 반도체 기판(101)의 전면에 물리기상증착법이나 화학기상증착법으로 TiN, Ta, TaN, WNX, TiAl(N) 등을 10 내지 1000Å의 두께를 갖는 베리어 금속막(111)을 형성한다.As illustrated in FIG. 1E, the TiN, Ta, TaN, WNX, TiAl (N), etc. are formed on the entire surface of the semiconductor substrate 101 including the contact hole 110 by a physical vapor deposition method or a chemical vapor deposition method. A barrier metal film 111 having a film is formed.

이후 공정을 도시하지 않았지만, 베리어 금속막(111)상에 금속막을 증착한 후 선택적으로 패터닝하여 금속배선을 형성한다. After the process is not shown, a metal film is deposited on the barrier metal film 111 and then selectively patterned to form a metal wiring.

이상과 같이 본 발명의 바람직한 실시예에 따르면, 게이트 전극(104)의 측벽 스페이서(106)에 잔존하는 실리사이드를 질소 이온의 주입 후 실리사이드 어닐을 실시함으로써 나이트라이드화하고, 측벽 스페이서(106)에 실리사이드로부터 변화된 나이트라이드를 황산을 사용하여 제거함으로써 게이트 전극(104)과 소스/드레인 불순물 확산영역(107)간의 쇼트(short)를 유발시키는 브릿지의 형성을 차단시키며, 이로 인해 반도체 소자의 결함을 방지한다.As described above, according to the exemplary embodiment of the present invention, the silicide remaining in the sidewall spacer 106 of the gate electrode 104 is nitrided by silicide annealing after the injection of nitrogen ions, and the silicide is formed on the sidewall spacer 106. By removing sulfuric acid, which is changed from sulfuric acid, the formation of a bridge that causes a short between the gate electrode 104 and the source / drain impurity diffusion region 107 is prevented, thereby preventing defects in the semiconductor device. .

상술한 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 게이트 전극의 측벽 스페이서에 잔존하는 실리사이드를 제거함으로써 게이트 전극과 소스/드레인간의 쇼트(short)를 유발하는 브릿지의 형성을 차단시키며, 이로 인해 반도체 소자의 결함을 방지하는 효과를 가지고 있다. As described above, the method of manufacturing a semiconductor device according to the present invention prevents the formation of a bridge that causes a short between the gate electrode and the source / drain by removing the silicide remaining in the sidewall spacer of the gate electrode. It has the effect of preventing the defect of a semiconductor element.

이상에서 설명한 것은 본 발명에 따른 반도체 소자의 제조방법을 실시하기 위한 하나의 실시예에 불과한 것으로서, 본 발명은 상기한 실시예에 한정되지 않고, 이하의 특허청구범위에서 청구하는 바와 같이 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능한 범위까지 본 발명의 기술적 정신이 있다고 할 것이다.What has been described above is only one embodiment for carrying out the method of manufacturing a semiconductor device according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims of the present invention Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (3)

반도체 소자의 제조방법에 있어서,In the manufacturing method of a semiconductor device, 반도체 기판에 게이트 전극과 소오스/드레인 불순물 확산영역을 포함하여 이루어지는 트랜지스터를 형성하는 단계와,Forming a transistor comprising a gate electrode and a source / drain impurity diffusion region in a semiconductor substrate; 상기 게이트 전극에 형성되는 측벽 스페이서에 질소 이온을 주입한 다음, 실리사이드 어닐(silicide anneal)을 실시함으로써 상기 측벽 스페이서에 존재하는 실리사이드를 나이트라이드화하는 단계와,Injecting nitrogen ions into the sidewall spacers formed in the gate electrode and then performing silicide anneal to nitride the silicide present in the sidewall spacers; 상기 측벽 스페이서에 존재하는 나이트라이드(nitride)를 황산(H2SO4)을 이용하여 제거하는 단계Removing the nitride present in the sidewall spacer using sulfuric acid (H 2 SO 4 ) 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 실리사이드를 나이트라이드화하는 단계는,Nitriding the silicide, 질소 이온의 주입시 주입 각도가 틸트되도록 하는 것For implantation angle to tilt when implanting nitrogen ions 을 특징으로 하는 반도체 소자의 제조방법. Method for manufacturing a semiconductor device, characterized in that. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 실리사이드를 나이트라이드화하는 단계는,Nitriding the silicide, 질소 이온을 주입시 상기 측벽 스페이서의 표면으로부터 40Å 내지 60Å까지 질소 이온을 주입시키는 것Implanting nitrogen ions from 40 to 60 microns from the surface of the sidewall spacer when the nitrogen ions are implanted 을 특징으로 하는 반도체 소자의 제조방법.Method for manufacturing a semiconductor device, characterized in that.
KR1020060130625A 2006-12-20 2006-12-20 Method for manufacturing a semiconductor device KR100800760B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990078303A (en) * 1998-03-30 1999-10-25 가네꼬 히사시 Manufacturing method of semiconductor device
KR20030018779A (en) * 2001-08-31 2003-03-06 동부전자 주식회사 Method for manufacturing a silicide layer of semiconductor device
KR20070070988A (en) * 2005-12-29 2007-07-04 동부일렉트로닉스 주식회사 Method for forming silicide in semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990078303A (en) * 1998-03-30 1999-10-25 가네꼬 히사시 Manufacturing method of semiconductor device
KR20030018779A (en) * 2001-08-31 2003-03-06 동부전자 주식회사 Method for manufacturing a silicide layer of semiconductor device
KR20070070988A (en) * 2005-12-29 2007-07-04 동부일렉트로닉스 주식회사 Method for forming silicide in semiconductor device

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