KR100781445B1 - Method for manufacturing metal layer in semiconductor device - Google Patents

Method for manufacturing metal layer in semiconductor device Download PDF

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KR100781445B1
KR100781445B1 KR1020060083874A KR20060083874A KR100781445B1 KR 100781445 B1 KR100781445 B1 KR 100781445B1 KR 1020060083874 A KR1020060083874 A KR 1020060083874A KR 20060083874 A KR20060083874 A KR 20060083874A KR 100781445 B1 KR100781445 B1 KR 100781445B1
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metal layer
etching
metal
semiconductor device
forming
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KR1020060083874A
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Korean (ko)
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김백원
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for manufacturing metal lines in a semiconductor device is provided to improve the yield of elements by preventing metal line bridges in the edge of a wafer. A metal layer(202) for forming metal lines is deposited on an interlayer dielectric(200) on a semiconductor substrate. An anti-reflective coating(204) is formed on an upper portion of the metal layer. A photoresist film is coated on the upper portion of the metal layer and a photoresist film pattern(206) is formed by using a mask for forming metal lines. Some parts of exposed reflection film and metal layer are etched by etchants including Ar based gas. Then, the rest of the metal layer and some parts of the interlayer dielectric are removed.

Description

반도체 소자의 금속 배선 형성 방법{METHOD FOR MANUFACTURING METAL LAYER IN SEMICONDUCTOR DEVICE}METHOD FOR MANUFACTURING METAL LAYER IN SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래 반도체 소자의 금속 배선 형성 방법을 설명하는 공정 단면도,1A to 1D are cross-sectional views illustrating a method of forming a metal wiring of a conventional semiconductor device;

도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하는 공정 단면도.2A to 2C are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention.

본 발명은 반도체 소자 형성 기술에 관한 것으로, 특히 웨이퍼 에지(edge) 영역에서의 식각 균일도(etch-rate uniformity)를 유지하는데 적합한 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device formation techniques, and more particularly to a method for forming metal wirings in semiconductor devices suitable for maintaining etch-rate uniformity in the wafer edge region.

일반적으로, 반도체 소자는 여러 단계의 공정 과정을 거쳐 형성되는데, 그 중 포토리소그래피 공정은 포토레지스트층 상부에 소정 부분만을 선택적으로 노광할 수 있도록 패터닝된 마스크 패턴을 개재하여 포토레지스트층에 선택적으로 광을 조사한 후 현상하여 레지스트 패턴을 형성하고, 이 레지스트 패턴을 기반으로 레지스트 패턴 하부에 위치한 금속층을 식각하여 각종 배선, 전극 등에 필요한 패턴을 형성하는 공정을 일컫는다.In general, a semiconductor device is formed through a multi-step process, wherein a photolithography process selectively selectively lights a photoresist layer through a patterned mask pattern so as to selectively expose only a predetermined portion over the photoresist layer. After the irradiation, the resist pattern is developed to form a resist pattern, and the metal layer under the resist pattern is etched based on the resist pattern to form a pattern required for various wirings, electrodes, and the like.

이와 같은 반도체 소자의 제조에서 금속 배선은 반도체 기판 상에 형성된 개별 소자들을 전기적으로 접속하여 회로를 형성함으로써 반도체 소자가 동작하도록 하는 것이다.In the manufacture of such a semiconductor device, the metal wiring is to allow the semiconductor device to operate by electrically connecting individual devices formed on the semiconductor substrate to form a circuit.

이러한 반도체 소자의 금속 배선 제조 공정에서 반도체 소자의 미세화에 따라 금속 배선의 미세한 패턴을 높은 해상도로 형성하기 위하여 금속 배선 형성을 위한 금속층의 증착 이후 금속층 식각시 반사 방지막, 예컨대 SiON, SiO2 등의 하드마스크를 형성함으로써 포토리소그래피에 의한 노광 공정 진행시 금속층에서의 광의 반사를 방지하도록 한다.In order to form a fine pattern of the metal wiring at a high resolution according to the miniaturization of the semiconductor device in the manufacturing process of the metal wiring of the semiconductor device, after the deposition of the metal layer for forming the metal wiring, the anti-reflection film such as SiON, SiO 2, etc. The mask is formed to prevent reflection of light from the metal layer during the exposure process by photolithography.

도 1a 내지 도 1d는 이와 같은 반사 방지막을 포함하는 종래 반도체 소자의 금속 배선 형성 방법을 설명하는 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a metal wiring of a conventional semiconductor device including such an antireflection film.

먼저, 도 1a에 도시한 바와 같이, 반도체 기판에 형성된 소자의 전극과 금속 배선층을 전기적으로 접속하기 위한 콘택(도시 생략됨) 또는 금속 배선과 금속 배선을 전기적으로 접속하기 위한 비아(도시 생략됨) 등의 접촉구가 형성된 층간 절연막(100) 상에 금속 배선층 형성을 위한 금속층(102)을 증착한다. 이때, 금속층(102)은 층간 절연막이 형성된 반도체 기판을 챔버로 장입하여 스퍼터링 방법에 형성하는 것이 바람직하다.First, as shown in FIG. 1A, a contact (not shown) for electrically connecting the electrode of the element formed on the semiconductor substrate and the metal wiring layer (not shown) or a via (not shown) for electrically connecting the metal wiring and the metal wiring is shown. The metal layer 102 for forming the metal wiring layer is deposited on the interlayer insulating film 100 having the contact holes such as the above. At this time, the metal layer 102 is preferably formed in the sputtering method by charging the semiconductor substrate with the interlayer insulating film formed in the chamber.

그리고 금속층(102) 상부 전면에 SiON, SiO2 등의 하드마스크 형태의 반사 방지막(104)을 형성한다. 반사 방지막(104)의 형성은 금속층(102)이 형성된 반도 체 기판을 챔버에 장입하여 PECVD(plasma enhanced chemical vapor deposition) 등의 CVD 방법으로 증착하는 것이 바람직하다.In addition, an anti-reflection film 104 in the form of a hard mask, such as SiON or SiO 2 , is formed on the entire upper surface of the metal layer 102. The anti-reflection film 104 may be formed by depositing a semiconductor substrate on which the metal layer 102 is formed, and depositing the same by a CVD method such as plasma enhanced chemical vapor deposition (PECVD).

이후, 이러한 반사 방지막(104) 상부에 감광막(도시 생략됨)을 도포한 후, 상기 감광막을 금속 배선 형성을 위한 마스크로 노광 현상하여 감광막 패턴(106)을 형성한다.Thereafter, a photoresist film (not shown) is coated on the anti-reflection film 104, and then the photoresist film is exposed and developed using a mask for forming metal wiring to form a photoresist pattern 106.

그런 다음, 도 1b 및 도 1c로 진행하여 상기 감광막 패턴(106)을 마스크로 드러난 반사 방지막(104)과 금속층(102)을 1차 식각한다. 여기서, 반사 방지막(104)과 금속층(102)의 식각액(etchant)으로서, 예를 들면 Cl2, BCl3 등의 가스가 적용될 수 있다.1B and 1C, the anti-reflection film 104 and the metal layer 102 having the photoresist pattern 106 as a mask are firstly etched. Here, as an etchant of the anti-reflection film 104 and the metal layer 102, for example, a gas such as Cl 2 , BCl 3 may be applied.

이때, 도 1b는 웨이퍼의 센터 영역을 예시한 것으로서, 반사 방지막(104)과 금속층(102)의 일부에 대한 식각이 진행되었음을 알 수 있다.In this case, FIG. 1B illustrates a center region of the wafer, and it can be seen that etching of the anti-reflection film 104 and a part of the metal layer 102 has been performed.

반면, 도 1c는 웨이퍼의 에지 영역을 예시한 것으로서, 반사 방지막(104)의 두께로 인해 방사 방지막(104)이 언더-식각(under-etch)되어 금속층(102)이 전혀 식각되지 않음을 알 수 있다.On the other hand, Figure 1c illustrates the edge region of the wafer, it can be seen that due to the thickness of the anti-reflection film 104 the anti-reflection film 104 is under-etched so that the metal layer 102 is not etched at all. have.

이는, 금속층(Al)과 산화막의 식각 선택비 차이에 의한 것으로, 통상적인 금속 식각에 사용되는 식각액이 적용되기 때문이다.This is due to the difference in etching selectivity between the metal layer Al and the oxide film, and is used because an etchant used for conventional metal etching is applied.

이후, 도 1d에서는 금속층(102) 상부의 감광막 패턴(106)을 제거하여 2차 식각을 진행한다. 이와 같은 2차 식각도 상술한 1차 식각과 마찬가지로 동일한 식각액을 사용한다.Subsequently, in FIG. 1D, the second etching is performed by removing the photoresist pattern 106 on the metal layer 102. This secondary etching also uses the same etching solution as the above-described primary etching.

만일, 도 1b와 같은 1차 식각 완료된 웨이퍼 센터 영역에 대해 2차 식각을 진행하는 경우에는 PR 마진이 양호한 결과를 얻을 수 있으나, 도 1c와 같은 1차 식각 완료된 웨이퍼 에지 영역에 대해 2차 식각을 진행하는 경우에는 도 1d에 나타난 바와 같이 PR 마진이 양호하지 못한 결과를 얻게 된다.If secondary etching is performed on the first etching-completed wafer center region as shown in FIG. 1B, a PR margin may be obtained. However, secondary etching may be performed on the first etching-completed wafer edge region as shown in FIG. 1C. In the case of progress, as shown in FIG. 1D, the PR margin is not good.

이와 같이, 종래의 반도체 금속 배선 형성 방법에서는, 금속의 반사율을 감소시키기 위해 두꺼운 하드마스크를 사용하고 있기 때문에, 이러한 막질을 식각하는 동안에 웨이퍼 내 식각 불균일성에 의한 웨이퍼 센터/에지간 산화막 손실 차이가 발생할 수 있다.As described above, in the conventional method of forming a semiconductor metal wiring, since a thick hard mask is used to reduce the reflectance of the metal, a difference in oxide loss between wafer centers and edges may occur due to etch inhomogeneity in the wafer during etching of the film. have.

이는, 웨이퍼 에지 영역에서의 금속 라인 브리지(metal line bridge)를 발생시켜 소자의 단락에 의한 수율 감소 등의 심각한 문제를 야기한다. 실제 패터닝시 PR의 두께를 높일 수는 없는 상황이므로 식각 시간을 증가시키는 것으로는 이러한 문제를 해결할 수 없다는 한계가 있다.This causes a metal line bridge in the wafer edge region, causing serious problems such as reduced yield due to short circuit of the device. Since the thickness of the PR cannot be increased during the actual patterning, increasing the etching time does not solve this problem.

본 발명은 상술한 종래 기술의 한계를 극복하기 위한 것으로, 반도체 소자의 금속 배선 식각시의 식각액을 Ar 계열의 가스를 적용함으로써 웨이퍼 센터 및 에지 영역에서의 식각 균일도를 유지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.The present invention is to overcome the above-mentioned limitations of the prior art, the metal wiring of the semiconductor device that can maintain the etching uniformity in the wafer center and the edge region by applying the Ar-based gas to the etching liquid during the metal wiring etching of the semiconductor device The purpose is to provide a formation method.

이러한 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따르면, 반도체 소자의 금속 배선 형성 방법으로서, 반도체 기판에 형성된 층간 절연막 상에 금속 배선 형성을 위한 금속층을 증착하는 단계와, 상기 금속층 상부면에 반사 방지막을 형성하는 단계와, 상기 반사 방지막 상부에 감광막 도포한 후 상기 감광막을 금속 배선 형성을 위한 마스크로 노광 현상하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 드러난 반사 방지막과 금속층의 일부를 Ar 기반의 가스가 적용되는 식각액을 사용하여 1차 식각하는 단계와, 상기 금속층 상부의 감광막 패턴을 제거한 후 2차 식각을 진행하여 상기 금속층의 나머지 및 층간 절연막의 일부를 제거하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법을 제공한다.According to a preferred embodiment of the present invention for achieving the above object, as a method of forming a metal wiring of the semiconductor device, the step of depositing a metal layer for forming the metal wiring on the interlayer insulating film formed on the semiconductor substrate, and the reflection on the upper surface of the metal layer Forming a photoresist film, applying a photoresist film on the antireflection film, and then exposing and developing the photoresist film with a mask for forming a metal wiring to form a photoresist pattern; and a portion of the antireflection film and the metal layer having the photoresist pattern exposed as a mask. Performing first etching using an etching solution to which an Ar-based gas is applied, and removing the photoresist pattern on the metal layer, and performing second etching to remove the remaining portion of the metal layer and a part of the interlayer insulating film. Provided is a method for forming metal wirings in a semiconductor device.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 2a 및 도 2c는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속 배선 형성 과정을 도시한 공정 단면도이다.2A and 2C are cross-sectional views illustrating a process of forming metal wirings in a semiconductor device according to an exemplary embodiment of the present invention.

먼저, 도 2a에 도시한 바와 같이, 반도체 기판에 형성된 소자의 전극과 금속 배선을 전기적으로 접속하기 위한 콘택(도시 생략됨) 또는 금속 배선과 금속 배선을 전기적으로 접속하기 위한 비아(도시 생략됨) 등의 접촉구가 형성된 층간 절연막(200) 상에 금속 배선 형성을 위한 금속층(202)을 증착한다. 이때, 금속층(202)은 층간 절연막이 형성된 반도체 기판을 챔버로 장입하여 스퍼터링 방법에 형성하는 것이 바람직하다.First, as shown in FIG. 2A, a contact (not shown) for electrically connecting the electrode and the metal wiring of the element formed on the semiconductor substrate (not shown) or a via (not shown) for electrically connecting the metal wiring and the metal wiring (not shown). The metal layer 202 for forming metal wirings is deposited on the interlayer insulating film 200 on which contact holes such as the back and the like are formed. At this time, the metal layer 202 is preferably formed in the sputtering method by charging the semiconductor substrate with the interlayer insulating film formed in the chamber.

그리고 금속층(202) 상부 전면에 반사 방지막(204)을 형성한다. 이와 같은 반사 방지막(204)은, 예를 들면 SiON, SiO2 등의 하드마스크 형태의 막으로서, 반사 방지막(204)의 형성은 금속층(202)이 형성된 반도체 기판을 챔버에 장입하여 PECVD(plasma enhanced chemical vapor deposition) 등의 CVD 방법에 의해 증착하는 것이 바람직하다.An anti-reflection film 204 is formed on the entire upper surface of the metal layer 202. Such an anti-reflection film 204 is a hard mask type film such as SiON, SiO 2, etc., and the formation of the anti-reflection film 204 is performed by inserting a semiconductor substrate on which the metal layer 202 is formed into a chamber, and thereby enhancing plasma enhanced PECVD. It is preferable to deposit by CVD methods, such as chemical vapor deposition.

이후, 이러한 반사 방지막(204) 상부에 감광막(도시 생략됨)을 도포한 후, 상기 감광막을 금속 배선 형성을 위한 마스크로 노광 현상하여 감광막 패턴(206)을 형성한다.Thereafter, a photoresist film (not shown) is coated on the anti-reflection film 204, and then the photoresist film is exposed and developed using a mask for forming a metal wiring to form a photoresist pattern 206.

그런 다음, 도 2b로 진행하여 상기 감광막 패턴(206)을 마스크로 드러난 반사 방지막(204)과 금속층(202)을 1차 식각한다.2B, the anti-reflection film 204 and the metal layer 202 having the photoresist pattern 206 as a mask are firstly etched.

이때, 본 실시예에서는 상기 반사 방지막(204)과 금속층(202)의 식각액(etchant)으로서, 바람직하게는 Ar 기반의 가스, 보다 바람직하게는 Ar 및 CHF3가 조합된 가스가 적용될 수 있다.In this embodiment, as the etchant of the anti-reflection film 204 and the metal layer 202, an Ar-based gas, more preferably, a gas in which Ar and CHF 3 are combined may be applied.

본 실시예에 따르면, 웨이퍼의 센터 영역과 에지 영역에서 모두 반사 방지막(204)과 금속층(202)의 일부에 대한 식각이 진행되었음을 알 수 있다.According to the present exemplary embodiment, it can be seen that etching of the anti-reflection film 204 and a part of the metal layer 202 has been performed in both the center region and the edge region of the wafer.

이는, 금속층(Al)과 산화막의 식각 선택비 차이에 의한 것으로, 본 실시예에 따른 금속 식각에 사용되는 식각액(Ar 기반의 가스 또는 Ar 및 CHF3가 조합된 가스)이 적용되기 때문이다.This is due to the difference in the etching selectivity between the metal layer Al and the oxide film, because an etching solution (Ar-based gas or a combination of Ar and CHF 3 ) used for metal etching according to the present embodiment is applied.

이후, 도 2c에서는 반사 방지막(204) 상부의 감광막 패턴(206)을 제거한 후 2차 식각을 진행하여 상기 금속층(202)의 나머지 및 층간 절연막(200)의 일부를 제거한다. 이와 같은 2차 식각도 상술한 1차 식각과 마찬가지로 동일한 식각액을 사용하며, 도 2c에서 도면부호 200a, 202a는 각각 식각 완료된 층간 절연막 및 금속층을 나타낸 것이다.Subsequently, in FIG. 2C, after removing the photoresist pattern 206 on the anti-reflection film 204, the second etching is performed to remove the rest of the metal layer 202 and a part of the interlayer insulating film 200. Such secondary etching also uses the same etching liquid as in the above-described primary etching, and reference numerals 200a and 202a in FIG. 2c represent etched interlayer insulating films and metal layers, respectively.

본 실시예에 따르면, 도 2b와 같은 1차 식각 완료된 웨이퍼 센터 및 에지 영역에 대해 2차 식각을 진행하는 경우에 PR 마진이 양호한 결과를 얻을 수 있다.According to the present exemplary embodiment, when the secondary etching is performed on the wafer center and the edge area of the primary etched surface as shown in FIG. 2B, a good PR margin may be obtained.

이상 설명한 바와 같이, 본 발명은 반도체 소자의 금속 배선 식각시의 식각액을 Ar 계열의 가스를 적용함으로써 웨이퍼 센터 및 에지 영역에서의 식각 균일도를 유지하도록 구현한 것이다.As described above, the present invention is implemented to maintain the etching uniformity in the wafer center and the edge region by applying an Ar-based gas to the etching liquid during the etching of the metal wiring of the semiconductor device.

본 발명에 의하면, 반도체 소자의 금속 배선 식각시의 식각액을 Ar 계열의 가스를 적용함으로써 웨이퍼 센터 및 에지 영역에서의 식각 균일도를 유지할 수 있다. 이로 인해, 웨이퍼 에지 영역에서의 금속 라인 브리지(metal line bridge) 발생을 방지하여 소자의 수율을 개선할 수 있다.According to the present invention, the etching uniformity in the wafer center and the edge region can be maintained by applying an Ar-based gas to the etchant at the time of etching the metal wiring of the semiconductor device. As a result, the generation of metal line bridges in the wafer edge region can be prevented to improve device yield.

이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 후술하는 특허청구범위의 기술적 사상과 범주 내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was demonstrated concretely based on the Example, this invention is not limited to such an Example, Of course, various deformation | transformation are possible for it within the technical idea and the scope of a claim mentioned later.

Claims (5)

반도체 소자의 금속 배선 형성 방법으로서,As a metal wiring formation method of a semiconductor element, 반도체 기판에 형성된 층간 절연막 상에 금속 배선 형성을 위한 금속층을 증착하는 단계와,Depositing a metal layer for forming metal wiring on the interlayer insulating film formed on the semiconductor substrate; 상기 금속층 상부면에 반사 방지막을 형성하는 단계와,Forming an anti-reflection film on the upper surface of the metal layer; 상기 반사 방지막 상부에 감광막을 도포한 후 상기 감광막을 금속 배선 형성을 위한 마스크로 노광 현상하여 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern by coating the photoresist on the anti-reflection layer and exposing and developing the photoresist with a mask for forming a metal wiring; 상기 감광막 패턴을 마스크로 드러난 반사 방지막과 금속층의 일부를 Ar 기반의 가스가 적용되는 식각액을 사용하여 1차 식각하는 단계와,Firstly etching a portion of the anti-reflection film and the metal layer exposed using the photoresist pattern as a mask using an etchant to which an Ar-based gas is applied; 상기 반사 방지막 상부의 감광막 패턴을 제거한 후 2차 식각을 진행하여 상기 금속층의 나머지 및 층간 절연막의 일부를 제거하는 단계Removing the photoresist pattern on the anti-reflection film and performing secondary etching to remove the rest of the metal layer and a part of the interlayer insulating film 를 포함하는 반도체 소자의 금속 배선 형성 방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 반사 방지막은, 하드마스크 형태의 막인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The anti-reflection film is a hard mask film. 제 1 항에 있어서,The method of claim 1, 상기 Ar 기반의 가스는, Ar 및 CHF3가 조합된 가스인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The Ar-based gas is a metal wiring formation method of a semiconductor device, characterized in that the combination of Ar and CHF 3 gas. 제 1 항에 있어서,The method of claim 1, 상기 1차 식각은, 웨이퍼의 센터 영역과 에지 영역에서 균일하게 식각이 진행되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The first etching method, the metal wire forming method of the semiconductor device, characterized in that the etching proceeds uniformly in the center region and the edge region of the wafer. 제 1 항에 있어서,The method of claim 1, 상기 2차 식각은 상기 1차 식각시의 식각액과 동일한 식각액이 사용되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The second etching method is a metal wiring forming method of the semiconductor device, characterized in that the same etching solution as the etching solution used in the first etching.
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KR980012018A (en) * 1996-07-29 1998-04-30 김광호 Silicon nitride film etching method of semiconductor device
KR20000044926A (en) 1998-12-30 2000-07-15 김영환 Method for forming via hole of semiconductor device
KR20030012108A (en) 2001-07-30 2003-02-12 주식회사 하이닉스반도체 Method of forming a thin film on the semiconductor devices
KR20040006459A (en) * 2002-07-12 2004-01-24 주식회사 하이닉스반도체 Method for improvement etching of hard mask
KR100577604B1 (en) * 2000-09-07 2006-05-08 삼성전자주식회사 Method for Manufacturing Semiconductor Device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980012018A (en) * 1996-07-29 1998-04-30 김광호 Silicon nitride film etching method of semiconductor device
KR20000044926A (en) 1998-12-30 2000-07-15 김영환 Method for forming via hole of semiconductor device
KR100577604B1 (en) * 2000-09-07 2006-05-08 삼성전자주식회사 Method for Manufacturing Semiconductor Device
KR20030012108A (en) 2001-07-30 2003-02-12 주식회사 하이닉스반도체 Method of forming a thin film on the semiconductor devices
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