KR100754305B1 - Low-GIDL MOSFET structure and method for fabrication - Google Patents
Low-GIDL MOSFET structure and method for fabrication Download PDFInfo
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Abstract
저-GIRL 전류를 제공하는 저-GIRL 전류 MOSFET 장치(90) 구조 및 그 제조 방법이 제공된다. MOSFET 장치 구조는 에지가 소스/드레인 확산부(88, 88)와 약간 중첩할 수 있는 중앙 게이트 도체(10), 및 박형 절연 및 확산 장벽층(50, 52)에 의해 중앙 게이트 도체로부터 분리되는 좌우측 사이드 윙 게이트 도체(70, 70)를 포함한다.A low-GIRL current MOSFET device 90 structure providing a low-GIRL current and a method of manufacturing the same are provided. The MOSFET device structure is left and right separated from the center gate conductor by a center gate conductor 10 whose edges may slightly overlap with the source / drain diffusions 88 and 88, and thin insulating and diffusion barrier layers 50 and 52. Side wing gate conductors 70 and 70.
저-GIDL 전류, 중앙 게이트 도체, 사이드 윙 게이트 도체, 금속 측벽 스페이서, 오프셋 막 Low-GIDL Current, Center Gate Conductor, Side Wing Gate Conductor, Metal Sidewall Spacer, Offset Membrane
Description
본 발명은 일반적으로 저(low)-GIDL(Gate-Induced Drain Leakage: 게이트 유도 드레인 누설) 전류 MOSFET 장치의 구조 및 그 제조 방법에 관한 것이다.FIELD OF THE INVENTION The present invention generally relates to structures of low-gate induced drain leakage (GIDL) current MOSFET devices and methods of fabricating the same.
장치 크기가 축소됨에 따라, 게이트 유도 드레인 누설(GIDL) 전류로 인해 신뢰성 문제가 생기고, 이로 인해 최상의 장치 성능을 위해 요구된 것보다 낮은 전압에서 장치를 동작시킬 수밖에 없다.As device sizes shrink, gate induced drain leakage (GIDL) current introduces reliability issues, which forces the device to operate at voltages lower than required for best device performance.
NMOSFET에서 드레인 전위가 게이트 전위보다 더 큰(+1V보다 큰) 플러스 전위로 되도록 장치가 바이어스될 때 그리고 PMOSFET에서 게이트 전위가 드레인 전위보다 더 큰(+1V보다 큰) 플러스 전위일 때, 게이트 도체가 드레인 확산 영역과 중첩하는 영역을 따라 전계 효과 트랜지스터의 표면 드레인 공핍 영역에서 전자-홀 쌍들이 생성되고 이에 의해 GIDL 전류가 발생된다.When the device is biased such that the drain potential in the NMOSFET is a positive potential that is greater than the gate potential (greater than + 1V) and when the gate potential is greater than the drain potential (greater than + 1V) in the PMOSFET, the gate conductor Electron-hole pairs are generated in the surface drain depletion region of the field effect transistor along the region overlapping the drain diffusion region, thereby generating a GIDL current.
본 발명은 저-GIDL 전류 MOSFET 장치 구조 및 저-GIDL 전류 MOSFET 장치의 제조 방법을 제공하는데, 이러한 저-GIDL 전류 MOSFET 장치는 종래의 MOSFET 장치에 비해 감소된 저-GIDL 전류를 제공한다. MOSFET 장치 구조는 에지가 소스/드레인 확산부와 약간 중첩할 수 있는 중앙 게이트 도체 및 박형 절연 및 확산 장벽층에 의해 중앙 게이트 도체로부터 분리되는 사이드 윙(side wing) 게이트 도체를 포함한다.The present invention provides a low-GIDL current MOSFET device structure and a method of manufacturing a low-GIDL current MOSFET device, which provide a reduced low-GIDL current compared to conventional MOSFET devices. The MOSFET device structure includes a center gate conductor whose edge may slightly overlap with the source / drain diffusion and a side wing gate conductor separated from the center gate conductor by a thin insulating and diffusion barrier layer.
NMOSFET 장치의 경우, 사이드 윙 게이트 도체는 양호하게 N+ 폴리실리콘으로 만들어지고, PMOSFET 장치의 경우, 사이드 윙 게이트 도체는 양호하게 P+ 폴리실리콘으로 만들어진다. 중앙 게이트 도체 영역은, (DRAM 애플리케이션에서와 같이) 고-Vt(임계 전압) NMOSFET이 요구되는 경우 P+ 폴리실리콘일 수 있고 또는 향상된 성능을 위해 저-Vt NMOSFET가 요구되는 경우라면 N+ 폴리실리콘일 수 있다(PFET는 상보적인 도핑을 사용할 수 있다). 사이드 윙 게이트 도체 및 중앙 게이트 도체는 위에 놓여있는 금속 측벽 도전층에 의해 함께 스트랩(strap)된다. 더욱이, 중앙 게이트 도체 아래 및 사이드 윙 도체 아래의 게이트 절연체 두께는 독립적으로 지정가능하다. 이로 인해 사이드 도체 아래의 게이트 절연체가 중앙 도체 아래의 게이트 절연체보다 양호하게 더 두껍게 될 수 있다.For NMOSFET devices, the side wing gate conductors are preferably made of N + polysilicon, and for PMOSFET devices, the side wing gate conductors are preferably made of P + polysilicon. The central gate conductor region can be P + polysilicon if a high-Vt (threshold voltage) NMOSFET is required (as in DRAM applications) or N + polysilicon if a low-Vt NMOSFET is required for improved performance. (PFETs may use complementary doping). The side wing gate conductor and the center gate conductor are strapped together by a metal sidewall conductive layer lying thereon. Moreover, the gate insulator thickness below the center gate conductor and below the side wing conductor is independently assignable. This can make the gate insulator under the side conductors better thicker than the gate insulator under the center conductor.
저-GIDL MOSFET 및 그 제조 방법에 관한 본 발명의 상기 목적 및 장점은 몇몇 실시예에 관한 다음의 상세한 설명을 첨부된 도면과 함께 참조함으로써 본 분야에 숙련된 기술자에 의해 더욱 쉽게 이해될 수 있으며, 도면에서 유사한 구성요소들은 동일한 참조번호로 표시된다.The above objects and advantages of the present invention with respect to low-GIDL MOSFETs and methods of manufacturing the same can be more readily understood by those skilled in the art by referring to the following detailed description of some embodiments in conjunction with the accompanying drawings, Like elements in the figures are designated by like reference numerals.
도 1 내지 9는 본 발명의 교시에 따른 저-GIDL MOSFET 장치의 제조 방법을 도시한 도면.1-9 illustrate a method of fabricating a low-GIDL MOSFET device in accordance with the teachings of the present invention.
도 1은 MOSFET 게이트 전극 폴리실리콘 증착이 표준 리소그래피 및 RIE 프로세스에 의해 패터닝된 후의 장치를 도시한 도면.1 shows an apparatus after MOSFET gate electrode polysilicon deposition is patterned by standard lithography and RIE processes.
도 2는 HDP와 같은 이방성 유전체 증착이 수평면 상에 오프셋 막을 형성하기 위해 사용된 후의 장치를 도시한 도면.FIG. 2 shows the apparatus after anisotropic dielectric deposition, such as HDP, has been used to form an offset film on a horizontal plane.
도 3은 도전성 확산 장벽(즉, WN, TiN)이 증착되고, CVD W/WN 스페이서와 같은 금속 스페이서가 PC의 측벽을 따라 형성된 후의 장치를 도시한 도면.FIG. 3 shows the apparatus after conductive diffusion barriers (ie, WN, TiN) are deposited and metal spacers such as CVD W / WN spacers are formed along the sidewalls of the PC.
도 4는 오프셋 막 HDP 유전체가 행잉(hanging) 스페이서를 형성하기 위해 스트립(strip)된 후의 장치를 도시한 도면.4 shows the apparatus after the offset film HDP dielectric has been stripped to form a hanging spacer.
도 5는 폴리실리콘 및 실리콘 기판이 W 금속 스페이서에 대해 선택적으로 산화된 후의 장치를 도시한 도면.FIG. 5 shows the device after the polysilicon and silicon substrates have been selectively oxidized to the W metal spacer.
도 6은 박형 LPCVD 폴리실리콘이 W 스페이서 아래의 언더컷(undercut) 영역에 의해 형성된 디보트(divot)를 채우기 위해 증착된 후의 장치를 도시한 도면.FIG. 6 shows the apparatus after thin LPCVD polysilicon has been deposited to fill a divert formed by an undercut region under the W spacer.
도 7은 박형 LPCVD 실리콘이 (스트랩 에칭과 같은) 등방성 에칭에 의해 필드 영역으로부터 제거된 후(박형 LPCVD 실리콘이 측벽 디보트 내에는 남아있음)의 장치를 도시한 도면.FIG. 7 shows the apparatus after thin LPCVD silicon is removed from the field region by an isotropic etch (such as strap etch) (thin LPCVD silicon remains in the sidewall dibot).
도 8은 S/D 확장부/헤일로(halo) 및 스페이서가 이온 주입과 같은 종래의 프로세스에 의해 형성된 후의 장치를 도시한 도면.FIG. 8 shows the apparatus after S / D extensions / halos and spacers have been formed by conventional processes such as ion implantation.
도 9는 살리사이드(salicide)가 종래의 프로세스에 의해 형성된 후의 장치를 도시한 도면.Figure 9 shows the apparatus after salicide is formed by a conventional process.
도 1 내지 9는 본 발명의 교시에 따른 저-GIDL MOSFET(금속 산화물 반도체 전계 효과 트랜지스터) 장치의 제조 방법을 도시한 것이다.1-9 illustrate a method of fabricating a low-GIDL MOSFET (metal oxide semiconductor field effect transistor) device in accordance with the teachings of the present invention.
도 1은 MOSFET 일차/주 중앙 게이트 전극 폴리실리콘 증착부(10)가 게이트 산화물 유전체 절연체(14)에 의해 덮여진 기판(12) 상에서 표준 리소그래피 및 RIE(반응성 이온 에칭) 프로세스에 의해 패터닝된 후의 장치를 도시한 것이다.1 shows an apparatus after MOSFET primary / main center gate
게이트 PC(폴리 크리스탈) 폴리는 에칭 이전에 선택적으로 도핑될 수 있다. 도시된 실시예에서, 게이트(10)는 고-Vt(임계 전압) 표면 채널 NFET 또는 저-Vt 매립 채널 NFET를 생성하기 위해 P형 불순물로 도핑된다.Gate PC (poly crystal) poly may be selectively doped prior to etching. In the illustrated embodiment,
도 2는 HDP(고밀도 플라즈마), 양호하게 산화물과 같은 비등방성 유전체 증착부(20)가 수평면 상에 이산화 실리콘과 같은 오프셋 막을 형성하기 위해 사용된 후의 장치를 도시한 것이다.Figure 2 shows the apparatus after HDP (high density plasma), preferably anisotropic
도 3은 도전성 확산 장벽(30)(즉, 측벽 금속과 게이트 폴리 사이의 반응을 방지하기 위한 WN(텅스텐/질화 텅스텐), TiN)이 증착되고, CVD(화학 증착) 텅스텐/질화 텅스텐 스페이서와 같은 금속 스페이서(금속 측벽 스페이서)(32)가 CVD 및 비등방성 RIE를 사용하여 PC의 측벽을 따라 형성된 후의 장치를 도시한 것이다.3 shows a conductive diffusion barrier 30 (i.e., WN (tungsten / tungsten nitride), TiN) deposited to prevent reaction between sidewall metal and gate poly, and a CVD (chemical vapor deposition) tungsten / tungsten nitride spacer, such as The device after metal spacers (metal sidewall spacers) 32 are formed along the sidewalls of the PC using CVD and anisotropic RIE.
금속 측벽 스페이서는 게이트 전극 폴리실리콘과 후속적으로 형성된 측벽 디보트 폴리실리콘 게이트 확장부(사이드 윙 게이트 도체)(70) 사이에 정류 접합(rectifying junction)이 형성되지 않게 한다.The metal sidewall spacer prevents a rectifying junction from being formed between the gate electrode polysilicon and the subsequently formed sidewall devoted polysilicon gate extension (side wing gate conductor) 70.
도 4는 비등방성 유전체 증착부(20)인 오프셋 막 HDP 유전체(20)가 언더컷 영역(40) 위에 행잉 스페이서(32)를 형성하기 위해 스트립된 후의 장치를 도시한 것이다.FIG. 4 shows the apparatus after the offset film HDP dielectric 20, anisotropic
도 5는 폴리실리콘 및 실리콘 기판이 W 금속 스페이서에 대해 선택적으로 참조번호(50)에서 산화된 후의 장치를 도시한 것이다(예를 들어, S. Iwata 등 저의 IEEE Trans. Electron Devices, ED-31, p.1174(1984) 참조). 노출된 폴리실리콘 게이트 전극의 측벽(52)은 산화되고, 산화물 장벽은 n+ 게이트 사이드 윙 게이트 도체와 p+ 중앙 게이트 도체 폴리의 상이한 일 함수로 인해 접합이 생성되지 않도록 박형 절연 및 확산 장벽층을 제공한다.FIG. 5 shows the device after polysilicon and silicon substrates are optionally oxidized at 50 for W metal spacers (see, for example, S. Iwata et al., IEEE Trans. Electron Devices, ED-31, p. 1174 (1984). The
도 6은 박형 LPCVD(저압 화학 증착) 폴리실리콘(60)이 W 스페이서 아래의 언더컷 영역에 의해 형성된 디보트를 채우기 위해 증착된 후의 장치를 도시한 것이다.FIG. 6 shows the apparatus after thin LPCVD (Low Pressure Chemical Vapor Deposition) polysilicon 60 has been deposited to fill the divert formed by the undercut region under the W spacer.
박형 LPCVD 폴리실리콘은 도핑 또는 비도핑으로 증착될 수 있다. 도핑되면, 그 도핑 극성은 S/D 확산부의 극성과 반대이다. 비도핑 증착되면, 박형 LPCVD 폴리는 저 에너지 앵글드(angled) 이온 주입, 플라즈마 침적(immersion), 기체상(gas phase) 도핑 또는 고체 소스 도핑과 같은 공지된 방법 중의 어느 하나, 또는 그것의 조합을 사용하여 도핑될 수 있다. 모든 도핑 기술은 NFET와 PFET 사이를 구별하기 위해 리소그래피로 정의된 블록 마스킹 층(산화물 또는 질화물)을 이용할 수 있다.Thin LPCVD polysilicon may be deposited by doping or undoping. If doped, its doping polarity is opposite to that of the S / D diffusion. Once undoped deposited, the thin LPCVD poly may be subjected to any one of known methods, such as low energy angled ion implantation, plasma immersion, gas phase doping or solid source doping, or a combination thereof. Can be doped using. All doping techniques can use a lithographically defined block masking layer (oxide or nitride) to distinguish between NFETs and PFETs.
도 7은 박형 LPCVD 실리콘이 (스트랩 에칭과 같은) F1 또는 C1 라디컬을 사용하는 화학 건식 에칭(CDE)과 같은 등방성 에칭에 의해 필드 영역으로부터 제거된 후(박형 LPCVD 실리콘(70)이 측벽 디보트 내에는 남아있음)의 장치를 도시한 것이다.7 shows thin LPCVD silicon removed from the field region by isotropic etching, such as chemical dry etching (CDE) using F1 or C1 radicals (such as strap etch) (
도 8은 S/D 확장부/헤일로(84) 및 스페이서(86)가 명명된 그리고 명명되지 않은 이온 주입을 포함하는 종래의 프로세스에 의해 형성된 후의 장치를 도시한 것이다. 소스 및 드레인 영역(88)은 농후하게 도핑된 영역인 반면, 확장부/헤일로 영역(84)은 희박하게 도핑되고, 제1 실시예에서는 참조번호(80)에서의 사이드 윙 게이트 도체와 약간 중첩하고, 제2 실시예에서는 참조번호(82)에서의 중앙 게이트 도체와 약간 중첩한다.FIG. 8 shows the apparatus after the S / D extension / halo 84 and the spacer 86 are formed by a conventional process involving named and unnamed ion implantation. The source and
도 9는 살리사이드(92)가 종래의 프로세스에 의해 형성된 후의 저-GIDL 전류 MOSFET 장치(90)를 도시한 것이다.9 shows a low-GIDL current MOSFET device 90 after salicide 92 is formed by a conventional process.
설명된 제조 방법은 에지가 소스/드레인 확산부와 약간 중첩할 수 있는 중앙 게이트 도체, 및 박형 절연 및 확산 장벽층에 의해 중앙 게이트 도체로부터 분리된 사이드 윙 게이트 도체를 갖는 저-GIDL 전류 MOSFET 장치를 생성한다.The fabrication method described is a low-GIDL current MOSFET device having a center gate conductor whose edges may slightly overlap with the source / drain diffusions, and a side wing gate conductor separated from the center gate conductor by a thin insulating and diffusion barrier layer. Create
NMOSFET 장치의 경우, 사이드 윙 게이트 도체는 양호하게 N+ 폴리실리콘으로 만들어지고, PMOSFET 장치의 경우, 사이드 윙 게이트 도체는 양호하게 P+ 폴리시리콘으로 만들어진다. 중앙 게이트 도체 영역은, 고-Vt(임계 전압) NMOSFET가 (DRAM 애플리케이션에서와 같이) 요구되면 P+ 폴리실리콘일 수 있고, 또는 저-Vt NMOSFET가 향상된 성능을 위해 요구되면 N+ 폴리실리콘일 수 있다(PFET는 상보적인 도핑을 사용할 수 있다).For NMOSFET devices, the side wing gate conductors are preferably made of N + polysilicon, and for PMOSFET devices, the side wing gate conductors are preferably made of P + polysilicon. The central gate conductor region may be P + polysilicon if a high-Vt (threshold voltage) NMOSFET is required (as in DRAM applications), or may be N + polysilicon if a low-Vt NMOSFET is required for improved performance ( PFETs may use complementary doping).
사이드 윙 게이트 도체 및 중앙 게이트 도체는 위에 놓여있는 금속 측벽 도전층에 의해 함께 스트랩된다. 더욱이, 중앙 게이트 도체 아래 및 사이드 윙 도체 아래의 게이트 절연체 GI 두께는 독립적으로 지정가능하다. 이것은 사이드 도체 아래의 게이트 절연체가 중앙 도체 아래의 게이트 절연체보다 양호하게 더 두껍게 될 수 있게 한다.The side wing gate conductor and the center gate conductor are strapped together by a metal sidewall conductive layer lying thereon. Moreover, the gate insulator GI thickness below the center gate conductor and below the side wing conductor is independently assignable. This allows the gate insulator under the side conductors to become thicker than the gate insulator under the center conductors.
게이트 전극의 에지에서 반대로 도핑된 LPCVD 디보트 영역들 사이의 내부확산 및 게이트 전극 도핑은 측벽 산화물 장벽에 의해 억제된다. 반대로 도핑된 디보트와 게이트 전극 사이의 전기적 접촉은 금속 스페이서에 의해 제공된다.Interdiffusion and gate electrode doping between the oppositely doped LPCVD devoted regions at the edge of the gate electrode are suppressed by the sidewall oxide barrier. In contrast, electrical contact between the doped divert and the gate electrode is provided by a metal spacer.
외부 게이트 도체들(N+ 측벽)을 위한 게이트 산화물의 재성장으로 인해, 중앙 게이트 도체의 에지 아래에 새부리(bird's beak) 모양이 형성되는 범위를 조사하기 위해 시뮬레이션이 행해졌다. 시뮬레이션은 (N+ 측벽 게이트 도체를 위한) 제2 게이트 산화물 재성장 이전의 중앙 게이트 도체 에지의 외형을 필요로 했으며, 프로세스의 이 시점에서 30Å 게이트 산화물이 중앙 게이트 아래에 존재한다. 그 다음, 구조물은 전형적인 게이트 산화 주기(950C, 150s, RTO, 100% 드라이 O2)에 종속되어, 그 후에 외부 N+ 게이트 도체 세그먼트를 포함할 영역 내의 기판 표면 상에 30Å의 산화물을 성장시키고, 그 결과 무시할 만한 새부리 모양이 발생했다. 명백하게, 새부리 모양은 아주 최소한으로 되고, 장치의 동작에 아무런 문제도 일으키지 않게 하고자 했다.Due to the regrowth of the gate oxide for the outer gate conductors (N + sidewalls), a simulation was performed to investigate the extent to which bird's beak shapes are formed under the edge of the center gate conductor. The simulation required the appearance of the center gate conductor edge before the second gate oxide regrowth (for the N + sidewall gate conductor), at which point 30 kV gate oxide is present below the center gate. The structure is then subjected to typical gate oxidation cycles (950C, 150s, RTO, 100% dry O2), which then grows 30 산화물 of oxide on the substrate surface in the region that will contain the outer N + gate conductor segment, resulting in There was a negligible beak appearance. Obviously, the beak shape was kept to a very minimum and to avoid causing any problems with the operation of the device.
큰 새부리 모양이 형성된 경우라도, P+ 내부 게이트 영역에 대한 N+ 외부 게이트 영역의 1.1V 일함수 변화는 외부 게이트 영역 내에서 반전이 처음 발생하게 할 수 있었다. 그러므로, 채널 전류는 가장 높은 Vt를 갖는 중앙 게이트 영역에 의해 지배될 수 있어서, 새부리 모양이 채널 전류 상에서 나타낼 수 있는 어떤 효과들을 최소화할 수 있다.Even when a large beak was formed, a 1.1V work function change of the N + outer gate region to the P + inner gate region could cause the inversion to occur within the outer gate region for the first time. Therefore, the channel current can be dominated by the central gate region with the highest Vt, thereby minimizing any effects that the beak shape can exhibit on the channel current.
본 발명은 패터닝된 중앙 게이트 도체 및 주위 기판 영역의 수평면 상에 오프셋 막을 형성하기 위해 양호하게 비등방성 유전체 증착을 사용함으로써, 패터닝된 중앙 게이트 도체 및 주위 기판 영역의 수평면 상에 오프셋 막을 형성하는 단계를 포함하는 저 게이트 유도 누설 전류(GIDL) MOSFET 장치를 제조하는 방법을 제공한다. 패터닝된 중앙 게이트 도체는 게이트 유전체에 의해 덮여진 기판상에 폴리실리콘을 증착한 다음에, 리소그래피 및 반응성 이온 에칭 프로세스에 의해 MOSFET 중앙 게이트 도체를 패터닝함으로써 양호하게 형성된다.The present invention provides a method of forming an offset film on a horizontal plane of a patterned center gate conductor and a surrounding substrate region by using preferably anisotropic dielectric deposition to form an offset film on a horizontal plane of a patterned central gate conductor and a surrounding substrate region. A method of manufacturing a low gate induced leakage current (GIDL) MOSFET device is provided. The patterned central gate conductor is well formed by depositing polysilicon on a substrate covered by the gate dielectric and then patterning the MOSFET central gate conductor by lithography and reactive ion etching processes.
그 다음, 프로세스는 계속하여, 중앙 게이트 도체의 측벽 상에 도전성 확산 장벽을 증착한 다음에, 중앙 게이트 도체 측벽 상의 도전성 확산 장벽 위에 금속 스페이서를 형성하고, 그 후 오프셋 막은 언더컷 영역 위에 행잉 금속 스페이서를 형성하기 위해 스트립된다.The process then continues by depositing a conductive diffusion barrier on the sidewalls of the central gate conductor, then forming a metal spacer over the conductive diffusion barrier on the central gate conductor sidewalls, and then the offset film forms a hanging metal spacer over the undercut region. Are stripped to form.
그 다음, 프로세스는 계속하여, 중앙 게이트 도체와 후속적으로 형성된 좌우측 사이드 윙 게이트 도체 사이에 정류 접합이 형성되지 않게 하기 위해 행잉 금속 스페이서 아래의 중앙 게이트 도체를 산화시킨 다음에, 행잉 금속 스페이서 아래의 언더컷 영역을 채우기 위해 폴리실리콘 층을 증착하고, 그 후 폴리실리콘 층은 좌우측 사이드 윙 게이트 도체를 형성하기 위해 행잉 금속 스페이서 아래의 언더컷 영역 내에 폴리실리콘을 남겨 둔채로 등방성 에칭에 의해 제거된다.The process then continues by oxidizing the center gate conductor under the hanging metal spacer so that no rectifying junction is formed between the center gate conductor and the subsequently formed left and right side wing gate conductors, and then under the hanging metal spacer. A layer of polysilicon is deposited to fill the undercut regions, and then the polysilicon layer is removed by isotropic etching leaving polysilicon in the undercut regions under the hanging metal spacers to form the left and right side wing gate conductors.
그 다음, 프로세스는 계속하여, 소스 및 드레인 확장부/헤일로 및 스페이서를 증착한 다음에, 도체 상에 살리사이드를 형성함으로써 완료된다. 양호한 실시예에서, 중앙 게이트 도체 및 좌우측 사이드 윙 게이트 도체는 양호하게 도핑된 폴 리실리콘으로 형성된다.The process is then completed by depositing the source and drain extensions / halo and spacers and then forming salicide on the conductor. In a preferred embodiment, the center gate conductor and the left and right side wing gate conductors are formed of well doped polysilicon.
설명된 프로세스는 소스 확산 영역, 드레인 확산 영역 및 중앙 게이트를 포함하는 저 게이트 유도 누설(GIDL) 전류를 갖는 MOSFET 장치를 제공한다. 중앙 게이트는 중앙 게이트 도체, 좌측 사이드 윙 게이트 도체 및 우측 사이드 윙 게이트 도체를 포함하고, 좌측 사이드 윙 게이트 도체 및 우측 사이드 윙 게이트 도체의 각각은 박형 절연 및 확산 장벽층에 의해 중앙 게이트 도체로부터 분리된다.The described process provides a MOSFET device having a low gate induced leakage (GIDL) current comprising a source diffusion region, a drain diffusion region and a central gate. The center gate comprises a center gate conductor, a left side wing gate conductor and a right side wing gate conductor, each of the left side wing gate conductor and the right side wing gate conductor separated from the center gate conductor by a thin insulation and diffusion barrier layer. .
중앙 게이트 도체의 좌측 및 우측 에지는 소스 확산 영역 및 드레인 확산 영역 중의 하나와 중첩할 수 있다. 좌우측 사이드 윙 게이트 도체의 좌측 및 우측 에지도 또한 소스 확산 영역 및 드레인 확산 영역 중의 하나와 중첩할 수 있다.The left and right edges of the center gate conductor may overlap one of the source diffusion region and the drain diffusion region. The left and right edges of the left and right side wing gate conductors may also overlap one of the source diffusion region and the drain diffusion region.
중앙 게이트 도체 및 좌우측 사이드 윙 게이트 도체는 위에 놓여있는 금속 측벽 도전층에 의해 함께 스트랩된다. 위에 놓여있는 금속 측벽 도전층은 중앙 게이트 도체와 좌우측 사이드 윙 게이트 도체 사이에서 정류 접합이 형성되지 않게 하기 위해 중앙 게이트 도체의 좌우 측벽을 따라 형성된 좌우 금속 측벽 스페이서를 포함한다. 좌우 금속 측벽 스페이서는 도전성 확산 장벽층에 의해 중앙 게이트 도체로부터 분리된다.The center gate conductor and the left and right side wing gate conductors are strapped together by a metal sidewall conductive layer overlying them. The underlying metal sidewall conductive layer includes left and right metal sidewall spacers formed along the left and right sidewalls of the center gate conductor to prevent the formation of a rectifying junction between the center gate conductor and the left and right side wing gate conductors. The left and right metal sidewall spacers are separated from the central gate conductor by a conductive diffusion barrier layer.
좌우측 사이드 윙 도체 아래의 게이트 절연체의 두께는 중앙 도체 아래의 게이트 절연체의 두께보다 더 두꺼워질 수 있도록 독립적으로 지정가능하게 될 수 있다.The thickness of the gate insulator under the left and right side wing conductors can be independently assignable so that it can be thicker than the thickness of the gate insulator under the center conductor.
저 GIDL MOSFET 및 그 제조 방법에 관한 본 발명의 몇몇 실시예 및 변형이 여기에서 상세하게 설명되었지만, 본 발명의 개시 및 교시는 본 분야에 숙련된 기 술자들에게 많은 대안적인 설계를 제안할 수 있다는 것을 명백히 알아야 된다.While some embodiments and variations of the present invention regarding low GIDL MOSFETs and methods of fabricating the same have been described in detail herein, the disclosure and teachings of the present invention may suggest many alternative designs to those skilled in the art. It should be clear that
본 발명은 일반적으로 전자 장치, 더욱 구체적으로 저-GIDL MOSFET 구조에 대한 산업상 이용가능성을 갖는다.The present invention generally has industrial applicability for electronic devices, more specifically for low-GIDL MOSFET structures.
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