KR100732297B1 - Method for Forming Landing Plug Contact Hole of Semiconductor Device - Google Patents
Method for Forming Landing Plug Contact Hole of Semiconductor Device Download PDFInfo
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- KR100732297B1 KR100732297B1 KR1020050056182A KR20050056182A KR100732297B1 KR 100732297 B1 KR100732297 B1 KR 100732297B1 KR 1020050056182 A KR1020050056182 A KR 1020050056182A KR 20050056182 A KR20050056182 A KR 20050056182A KR 100732297 B1 KR100732297 B1 KR 100732297B1
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
본 발명은 반도체 소자의 랜딩플러그 콘택홀 형성방법에 관한 것으로, 소정의 하부 구조를 구비하는 반도체 기판의 활성 영역 상에 측벽 스페이서를 구비하는 게이트 패턴을 형성하는 단계와, 상기 구조의 전체 표면 상부에 층간절연막을 형성하는 단계와, 상기 게이트 패턴을 배리어로 하고, 콘택 마스크를 이용한 식각 공정으로 상기 층간절연막을 식각하여 제1 랜딩플러그 콘택홀을 형성하는 단계와, 상기 구조의 전체 표면 상부에 제1 랜딩플러그 물질을 증착하여 제1 랜딩플러그를 형성하되, 제1 랜딩플러그 콘택홀의 내부가 완전히 채워지지 않도록 형성하는 단계와, 상기 제1 랜딩플러그 물질을 전면식각하여 스페이서를 형성하는 단계와, 상기 스페이서를 배리어로 하여 상기 반도체 기판의 활성 영역을 식각하여 제2 랜딩플러그 콘택홀을 형성하는 단계와, 상기 제2 랜딩플러그 콘택홀을 매립하는 제2 랜딩플러그 물질을 증착하여 제2 랜딩플러그를 형성하는 단계를 포함하는 반도체 소자의 랜딩플러그 콘택홀 형성방법을 개시한다.The present invention relates to a method of forming a landing plug contact hole of a semiconductor device, the method comprising: forming a gate pattern having sidewall spacers on an active region of a semiconductor substrate having a predetermined substructure, and forming a gate pattern on an entire surface of the structure; Forming a first insulating plug contact hole by forming an interlayer insulating film, etching the interlayer insulating film using an etching process using a contact mask as a barrier, and forming a first landing plug contact hole on the entire surface of the structure; Forming a first landing plug by depositing a landing plug material so as to prevent the interior of the first landing plug contact hole from being completely filled; forming a spacer by totally etching the first landing plug material, and forming the spacer; A second landing plug contact hole is formed by etching the active region of the semiconductor substrate as a barrier. It discloses a step and the second landing plug contact second landing the plug material deposited by the second forming landing plug contact hole of a semiconductor device including forming a plug landing method for filling the holes.
Description
도 1 내지 도 5는 본 발명에 따른 반도체 소자의 랜딩플러그 콘택홀 형성방법을 도시하는 단면도.1 to 5 are cross-sectional views illustrating a method for forming a landing plug contact hole in a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 반도체 기판 12 : 폴리실리콘막10
14 : 금속층 16 : 하드마스크막14
18 : 스페이서 20 : 층간절연막18
22 : 제1 랜딩플러그 콘택홀 24 : 제1 랜딩플러그22: the first landing plug contact hole 24: the first landing plug
26 : 제1 랜딩플러그 스페이서 28 : 제2 랜딩플러그 콘택홀26: first landing plug spacer 28: second landing plug contact hole
30 : 제2 랜딩플러그30: second landing plug
본 발명은 반도체 소자의 랜딩플러그 콘택홀 형성방법에 관한 것으로, 더욱 상세하게는 이중 식각 공정으로 랜딩플러그 콘택홀을 형성함으로써, 저항을 감소시키고 랜딩플러그 콘택 이온 주입에 의한 과도한 이온 주입이 트랜지스터에 주는 악 영향을 감소시킬 수 있는 방법에 관한 것이다.The present invention relates to a method of forming a landing plug contact hole of a semiconductor device, and more particularly, by forming a landing plug contact hole by a double etching process, thereby reducing resistance and exerting excessive ion implantation into the transistor by landing plug contact ion implantation. It is about how to reduce the adverse effect.
현재 반도체 소자를 제조하는 기술이 미세화됨에 따라, 랜딩플러그 콘택홀의 저항 증가로 소자의 속도 특성이 열화되었고, 저항을 감소시킬 목적으로 실시하는 랜딩플러그 콘택 이온 주입 공정은 트랜지스터의 특성 저하를 야기시켰다.As the current technology for manufacturing semiconductor devices has been miniaturized, the speed characteristics of the devices have been degraded due to the increase in the resistance of the landing plug contact holes, and the landing plug contact ion implantation process, which is performed for the purpose of reducing the resistance, has caused the transistor characteristics to degrade.
종래에 반도체 소자의 랜딩플러그 콘택홀을 형성하는 공정은, 랜딩플러그 콘택 식각 공정을 수행함에 있어 게이트 패턴을 배리어 (barrier)로 하여 랜딩플러그 콘택홀을 형성하였다.Conventionally, in the process of forming the landing plug contact hole of the semiconductor device, the landing plug contact hole is formed using the gate pattern as a barrier in performing the landing plug contact etching process.
그러나 상기 종래의 방법으로 랜딩플러그 콘택홀을 형성하면 게이트 패턴의 높이가 5000∼7000Å으로 높기 때문에, 랜딩플러그 콘택홀의 하단부에서의 과도 식각 (over etch)의 정도에 따라 저항이 급변한다. However, when the landing plug contact hole is formed by the conventional method, since the height of the gate pattern is high as 5000 to 7000 Å, the resistance changes rapidly depending on the degree of overetch at the lower end of the landing plug contact hole.
또한 저항을 감소시킬 목적으로 과도 식각을 수행할 경우 식각이 수직 방향 뿐만 아니라, 수평 방향으로도 이루어지기 때문에 트랜지스터의 특성에 영향을 준다. 특히, 랜딩플러그 콘택 이온 주입 공정을 수행할 경우 이온의 확산 현상이 일어나 트랜지스터의 특성을 더욱 저하시킨다.In addition, when the excessive etching is performed to reduce the resistance, the etching is performed not only in the vertical direction but also in the horizontal direction, thereby affecting the characteristics of the transistor. In particular, when the landing plug contact ion implantation process is performed, the diffusion of ions occurs to further deteriorate the transistor characteristics.
상기 문제점 때문에, 랜딩플러그 콘택 식각을 조절하기가 쉽지 않으며 과도한 식각은 더욱 어려워 랜딩플러그 물질과 활성 영역간의 접촉 저항을 증가시켜 트랜지스터의 특성을 확보하는 방향으로 공정을 수행하게 되었다. 그러나 이러한 저항 증가는 소자의 속도 특성을 저하시켜 불량율을 증가시키고 고속 동작하는 소자의 개발을 어렵게 만들었다.Due to the above problems, it is difficult to control the landing plug contact etch and the excessive etching is more difficult, thereby increasing the contact resistance between the landing plug material and the active region to secure the transistor characteristics. However, this increase in resistance lowers the device's speed characteristics, increasing the defect rate and making it difficult to develop high-speed devices.
본 발명은 상기 종래기술의 문제점을 해결하기 위한 것으로, 랜딩플러그 콘택홀을 형성함에 있어 이중 식각 공정을 수행함으로써, 저항을 감소시키고 랜딩플러그 콘택 이온 주입에 의한 과도한 이온 주입이 트랜지스터에 주는 악영향을 감소시킬 수 있는 반도체 소자의 랜딩플러그 콘택홀 형성방법을 제공하는 것을 목적으로 한다.The present invention is to solve the problems of the prior art, by performing a double etching process in forming the landing plug contact hole, thereby reducing the resistance and the adverse effect of excessive ion implantation by the landing plug contact ion implantation to the transistor An object of the present invention is to provide a method for forming a landing plug contact hole in a semiconductor device.
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 랜딩플러그 콘택홀 형성방법은,
반도체 기판의 활성 영역 상에 측벽 스페이서를 구비하는 게이트 패턴을 형성하는 단계;
상기 구조의 전체 표면 상부에 층간절연막을 형성하는 단계;
콘택 마스크를 이용한 식각 공정으로 상기 층간절연막을 식각하여 제1 랜딩플러그 콘택홀을 형성하는 단계;
상기 제1 랜딩플러그 콘택홀에 제1 랜딩플러그 물질로 스페이서를 형성하는 단계;
상기 스페이서를 배리어로 하여 상기 제1 랜딩플러그 콘택홀 저부의 활성 영역을 식각하여 제2 랜딩플러그 콘택홀을 형성하는 단계; 및
상기 제2 랜딩플러그 콘택홀을 매립하는 제2 랜딩플러그를 형성하는 포함하는 것과,
상기 제2 콘택플러그 콘택홀 형성후 이온 주입 공정을 더 수행하는 것과,Landing plug contact hole forming method of a semiconductor device according to the present invention to achieve the above object,
Forming a gate pattern having sidewall spacers on an active region of the semiconductor substrate;
Forming an interlayer insulating film over the entire surface of the structure;
Etching the interlayer insulating layer by an etching process using a contact mask to form a first landing plug contact hole;
Forming a spacer with a first landing plug material in the first landing plug contact hole;
Etching the active region of the bottom of the first landing plug contact hole using the spacer as a barrier to form a second landing plug contact hole; And
Forming a second landing plug to fill the second landing plug contact hole;
Performing an ion implantation process after forming the second contact plug contact hole;
상기 제2 랜딩플러그는 폴리실리콘 또는 전도성 물질로 형성하는 것을 제공한다.
이하, 첨부된 도면을 참고로 하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.The second landing plug provides forming with polysilicon or a conductive material.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
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도 1 내지 도 5는 본 발명에 따른 반도체 소자의 랜딩플러그 콘택홀 형성방법을 도시하는 단면도로서, 그 제조과정을 살피면 다음과 같다.1 to 5 are cross-sectional views illustrating a method of forming a landing plug contact hole of a semiconductor device according to the present invention.
도 1을 참조하면, 반도체 기판(10)에 얇은 트렌치 소자분리 (Shallow Trench Isolation; STI) 공정을 수행하여 소자분리막을 형성함으로써, 반도체 기판을 소자분리 영역 및 활성 영역으로 구분하고, 통상의 공정을 수행하여 소정의 하부 구조를 구비하도록 한다.Referring to FIG. 1, by forming a device isolation layer by performing a thin trench isolation (STI) process on a
다음, 상기 소정의 하부 구조를 구비하는 반도체 기판(10)의 활성 영역 상에 게이트 산화막(미도시), 폴리실리콘막(12), 금속층(14) 및 하드 마스크막(16)으로 이루어지는 게이트 형성용 막(미도시)을 형성한 후, 게이트 마스크(미도시)를 이용한 식각공정으로 상기 게이트 형성용 막을 식각하여 게이트 패턴(미도시)을 형성한다.Next, a gate oxide film (not shown), a
다음, 상기 구조의 전체 표면 상부에 질화막을 증착한 후, 상기 질화막을 전면식각하여 상기 게이트 패턴의 측벽에 질화막 스페이서(18)를 형성한다.Next, after the nitride film is deposited on the entire surface of the structure, the nitride film is etched entirely to form the
다음, 상기 구조의 전체 표면 상부에 고밀도 플라즈마 산화막 등의 산화막을 증착하여 층간절연막(20)을 형성한다.Next, an interlayer
도 2를 참조하면, 층간절연막(20) 상부에 포토레지스트를 도포하여 포토레지스트막(미도시)을 형성한 다음, 노광 마스크를 이용하여 상기 포토레지스트막을 선 택적으로 노광한 후 현상하여 포토레지스트 패턴(미도시)을 형성한다.Referring to FIG. 2, a photoresist is formed by applying a photoresist on the
다음, 상기 게이트 패턴을 배리어로 하고 상기 포토레지스트 패턴을 콘택 마스크로 이용한 식각 공정으로 층간절연막(20)을 식각하여 제1 랜딩플러그 콘택홀(22)을 형성한다.Next, the first insulating
다음, 상기 콘택 마스크로 이용된 포토레지스트 패턴을 제거한다.Next, the photoresist pattern used as the contact mask is removed.
도 3을 참조하면, 상기 구조의 전체 표면 상부에 폴리실리콘 등의 제1 랜딩플러그 물질을 증착하여 랜딩플러그(24)를 형성하는데, 이때 제1 랜딩플러그 콘택홀(22)의 내부가 완전히 채워지지 않도록 그 두께를 조절하여 증착한다.Referring to FIG. 3, a first landing plug material such as polysilicon is deposited on the entire surface of the structure to form a
본 발명에서는 상기와 같이 제1 랜딩플러그 콘택홀(22) 및 제1 랜딩플러그(24)의 형성을 통해 제1 랜딩플러그(24)와 트랜지스터(미도시)의 간격을 충분히 확보할 수 있다.In the present invention, the gap between the
도 4를 참조하면, 제1 랜딩플러그(24)를 전면식각하여 제1 랜딩플러그 스페이서(26)를 형성한다.Referring to FIG. 4, the
다음, 제1 랜딩플러그 스페이서(26)를 배리어로 하여 반도체 기판(10)의 활성 영역을 50∼300Å의 깊이로 식각하여 제2 랜딩플러그 콘택홀(28)을 형성한다.Next, the second landing
다음, 제1 랜딩플러그 스페이서(26)를 배리어로 하는 이온 주입 공정을 수행하여 반도체 기판(10)의 활성 영역에 불순물이 주입되도록 할 수도 있다. 이는 저항 감소를 목적으로 실시하는 것이다.Next, an ion implantation process may be performed using the first
도 5를 참조하면, 제2 랜딩플러그 콘택홀(28)을 매립하도록 폴리실리콘 또는 전도성 물질 등의 제2 랜딩플러그 물질을 증착하여 제2 랜딩플러그(30)를 형성한 다음, 화학적 기계적 연마 (CMP) 등의 평탄화 공정을 수행하여 제2 랜딩플러그(30)를 분리한다.Referring to FIG. 5, a
본 발명에서는 상기와 같이, 제2 랜딩플러그 콘택홀(28) 및 제2 랜딩플러그(30)의 형성을 통해 효과적으로 저항을 감소시킬 수 있다.In the present invention, as described above, the resistance can be effectively reduced through the formation of the second landing
상기한 바와 같이, 본 발명에서는 반도체 소자의 랜딩플러그 콘택홀을 형성함에 있어 이중 식각 공정을 수행하는 것이 특징으로, 제1 랜딩플러그 콘택홀(22) 및 제1 랜딩플러그(24)의 형성을 통해 제1 랜딩플러그(24)와 트랜지스터의 간격을 충분히 확보하고, 제2 랜딩플러그 콘택홀(28) 및 제2 랜딩플러그(30)의 형성을 통해 효과적으로 저항을 감소시킬 수 있으며, 제2 랜딩플러그(30)를 형성하기에 앞서 이온 주입 공정을 더 수행함으로써, 저항이 더욱 감소되도록 할 수 있다.As described above, the present invention is characterized in that the double etching process is performed in forming the landing plug contact hole of the semiconductor device, through the formation of the first landing
아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
이상에서 설명한 바와 같이, 본 발명에서는 이중 식각 공정으로 랜딩플러그 콘택홀을 형성함으로써, 저항을 감소시킬 수 있어 고수율로 반도체 소자를 얻을 수 있을 뿐만 아니라, 랜딩플러그 콘택 이온 주입에 의한 과도한 이온 주입이 트랜지스터에 주는 영향을 최소화시킬 수 있다.As described above, in the present invention, by forming the landing plug contact hole in the double etching process, the resistance can be reduced, so that the semiconductor device can be obtained with high yield, and excessive ion implantation by the landing plug contact ion implantation The effect on the transistor can be minimized.
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| KR20050052608A (en) * | 2003-11-28 | 2005-06-03 | 주식회사 하이닉스반도체 | Method for forming storagenode contact in semiconductor device |
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| KR20040085911A (en) * | 2003-04-02 | 2004-10-08 | 주식회사 하이닉스반도체 | A method for forming a test pattern of a semiconductor device |
| KR20050052608A (en) * | 2003-11-28 | 2005-06-03 | 주식회사 하이닉스반도체 | Method for forming storagenode contact in semiconductor device |
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