KR100720498B1 - Method for forming metal line of semiconductor - Google Patents
Method for forming metal line of semiconductor Download PDFInfo
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- KR100720498B1 KR100720498B1 KR1020050134791A KR20050134791A KR100720498B1 KR 100720498 B1 KR100720498 B1 KR 100720498B1 KR 1020050134791 A KR1020050134791 A KR 1020050134791A KR 20050134791 A KR20050134791 A KR 20050134791A KR 100720498 B1 KR100720498 B1 KR 100720498B1
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- contact hole
- metal wiring
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 30
- 239000002184 metal Substances 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title description 6
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 239000001307 helium Substances 0.000 claims abstract description 4
- 229910052734 helium Inorganic materials 0.000 claims abstract description 4
- -1 helium ions Chemical class 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000035622 drinking Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 금속 배선 형성 방법에 관한 것이다.The present invention relates to a metal wiring forming method.
본 발명에 따른 금속 배선 형성 방법은 먼저 실리콘 기판에 형성된 층간 절연막을 선택적으로 식각하여 콘택홀을 형성한다. 이렇게 형성된 콘택홀의 입구를 넓혀서 콘택홀의 종횡비를 줄인다. 이때 콘택홀의 입구를 넓히는 공정은 헬륨 이온을 사용한 플라즈마 건식 식각 방법을 사용할 수 있다. 이어서 콘택홀에 금속을 매립함으로써 금속 배선을 형성한다.In the method for forming metal lines according to the present invention, first, the interlayer insulating layer formed on the silicon substrate is selectively etched to form contact holes. The aspect ratio of the contact hole is reduced by widening the entrance of the contact hole thus formed. In this case, the process of widening the inlet of the contact hole may use a plasma dry etching method using helium ions. Subsequently, the metal wiring is formed by burying the metal in the contact hole.
다마신 공정, 금속 배선, 화학기상증착법 Damascene process, metallization, chemical vapor deposition
Description
도 1a 내지 도 1c는 종래의 금속 배선 형성 방법을 나타내는 단면도.1A to 1C are cross-sectional views showing a conventional metal wiring forming method.
도 2a 내지 도 2e는 본 발명에 따른 금속 배선 형성 방법을 나타내는 단면도.2A to 2E are cross-sectional views illustrating a metal wiring forming method according to the present invention.
<도면에 사용된 참조 번호의 설명><Description of Reference Number Used in Drawing>
22 : 반도체 기판 2, 24 : 층간 절연막22
13,33 : 콘택홀 35 : 장벽층13,33: contact hole 35: barrier layer
11,31 : 포토레지스트 패턴11,31: Photoresist Pattern
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 화학기상증착법으로 텅스텐을 매립하는 금속 배선의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in which tungsten is embedded by chemical vapor deposition.
실리콘 기판에 반도체 소자를 패터닝하는 방법으로는 사진 공정과 식각 공정을 통해 원하는 패턴을 형성하는 포토리소그라피 방법과, 물질층을 선택적으로 식각하여 형성된 패턴, 예컨대 콘택홀 내부에 금속 배선용 물질을 매립하는 다마신 공정 방법이 있다.The method of patterning a semiconductor device on a silicon substrate includes a photolithography method for forming a desired pattern through a photo process and an etching process, and a material formed by selectively etching a material layer, for example, a metal wiring material is embedded in a contact hole. There is a method of drinking.
콘택홀은 도 1a와 같이 절연막(2)에 포토레지스트 패턴(11)을 정렬하고, 포토레지스트 패턴(11)을 마스크로 절연막(2)을 선택적으로 식각함으로써 도 1b와 같은 콘택홀(33)을 형성할 수 있다. As shown in FIG. 1A, the contact hole is aligned with the
이렇게 형성된 콘택홀(13)에는 금속 배선용 물질을 형성한다. 예를 들어 금속 배선용 물질은 텅스텐(W)을 사용할 수도 있고, 텅스텐을 사용할 경우 콘택홀(13) 내부에 텅스텐을 매립하는 방법은 화학기상증착법을 이용한다. The contact hole 13 formed as above is formed with a metal wiring material. For example, the metal wiring material may use tungsten (W), and when tungsten is used, the method of embedding tungsten in the contact hole 13 uses a chemical vapor deposition method.
그런데 이처럼 금속을 매립하는 과정에서 도 1c고 같이 텅스텐(15)이 콘택홀(13)을 완전히 채우지 못하여 틈(15)이 발생하는 경우도 있다. 이러한 현상은 텅스텐 등의 금속을 화학기상증착방법으로 형성할 때에 발생하는 결함으로 특히, 반도체 칩이 고집적화됨에 따라 콘택홀(13)의 임계치수는 점차 작아지고 종횡비(aspect ration)는 커지기 때문에 금속을 증착할 때 난점으로 인해 생성된다. 이처럼 콘택홀 내에 발생하는 틈은 전류 패스를 감소시켜서 저항을 증가시키며, 전류의 흐름을 방해하여 소자의 특성을 저하시킨다. However, in this process of embedding the metal, as shown in FIG. 1C, the
본 발명은 전술한 종래 기술의 문제점을 해결하기 위한 것으로서, 화학기상 증착법을 이용하여 콘택홀에 금속 배선을 형성할 때 틈이 발생하는 현상을 방지할 수 있는 금속 배선 형성 방법을 제공하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a method for forming a metal wiring, which can prevent a phenomenon in which a gap occurs when forming a metal wiring in a contact hole using a chemical vapor deposition method. .
이러한 목적들을 달성하기 위하여, 본 발명에 따른 금속 배선 형성 방법은 먼저 실리콘 기판에 형성된 층간 절연막을 선택적으로 식각하여 콘택홀을 형성한다. 이렇게 형성된 콘택홀의 입구를 넓혀서 콘택홀의 종횡비를 줄인다. 이때 콘택홀의 입구를 넓히는 공정은 헬륨 이온을 사용한 플라즈마 건식 식각 방법을 사용할 수 있다. 이어서 콘택홀에 금속을 매립함으로써 금속 배선을 형성한다.In order to achieve these objects, the metal wiring forming method according to the present invention first forms a contact hole by selectively etching the interlayer insulating film formed on the silicon substrate. The aspect ratio of the contact hole is reduced by widening the entrance of the contact hole thus formed. In this case, the process of widening the inlet of the contact hole may use a plasma dry etching method using helium ions. Subsequently, the metal wiring is formed by burying the metal in the contact hole.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 방법으로 금속 배선을 형성하는 것을 나타내는 단면도이다.2A-2E are cross-sectional views illustrating the formation of metal wires by the method according to the invention.
본 발명에 따른 콘택홀의 형성 방법은 먼저, 도 2a와 같이 반도체 기판(22) 상에 층간 절연막(24)을 형성한다. 층간 절연막(24) 위에는 콘택홀의 형성을 위한 포토레지스트 패턴(31)을 정렬한다.In the method of forming a contact hole according to the present invention, first, an
그리고, 포토레지스트 패턴(31)을 마스크로 하여 층간 절연막(24)을 선택적으로 식각함으로써 도 2b과 같이 콘택홀(33)을 형성한다.The
이어서 도 2c에서처럼 콘택홀(33)의 내부에는 장벽층(barrier; 35)를 형성한다. 장벽층(35)은 콘택홀(33) 내부에 매립될 텅스텐(W)과의 접착력이 좋은 물질을 사용함으로써 금속 배선의 형성을 원활히 한다. 이하의 설명에서 도면의 간략화를 위해 장벽층(35)은 생략하여 표현하기로 한다.Next, as shown in FIG. 2C, a
장벽층을 형성한 다음에는 도 2d처럼 콘택홀(33)의 입구를 확장한다. After the barrier layer is formed, the inlet of the
콘택홀(33)의 입구를 확장하는 것은 플라즈마 스퍼터링을 이용한 건식 식각 방법을 사용한다. 이때 식각 가스로는 헬륨 이온(He+)을 사용한다.Expanding the inlet of the
이처럼 본 발명에 따른 콘택홀의 형성 방법에 의하면 콘택홀이 입구가 좀 더 넓어져서 이후의 금속 배선을 채우는 데에 더욱 효율적이다. 즉, 기존처럼 텅스텐을 화학기상증착법으로 콘택홀(33)에 매립하는 과정에 있어서 콘택홀(33)의 입구가 넓기 때문에 텅스텐이 콘택홀(33)의 넓은 측벽을 따라서 자연스럽게 매립되면서 그 내부에 빈 공간이 발생하지 않는다. Thus, according to the method for forming a contact hole according to the present invention, the contact hole has a wider inlet, which is more efficient for filling subsequent metal wiring. That is, since the inlet of the
이렇게 금속 배선을 형성한 다음에는 평탄화 공정으로 층간 절연막을 평평하게 한다. 이때 콘택홀의 넓혀진 입구 부분도 제거하여 도 2e와 같이 콘택홀의 상부와 하부의 직경이 동일하게 하는 것이 바람직하다.After the metal wirings are formed in this manner, the interlayer insulating film is flattened by a planarization process. At this time, it is preferable to remove the widened inlet portion of the contact hole so that the diameter of the upper and lower portions of the contact hole is the same as shown in FIG. 2E.
지금까지 실시예를 통하여 설명한 바와 같이, 본 발명에 의한 금속 배선 형성 방법에 의하면 콘택홀에 형성된 금속 배선 내부에 빈 공간이 발생하는 것을 방지하여 저항값의 안정화를 이룰 수 있고, 소자의 신뢰성을 향상시킬 수 있다.As described through the embodiments up to now, according to the method for forming a metal wiring according to the present invention, it is possible to stabilize the resistance value by preventing an empty space from occurring inside the metal wiring formed in the contact hole, thereby improving the reliability of the device. You can.
본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며, 이를 위해 비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽 게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 자명한 것이다.In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used for this purpose, they are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050026270A (en) * | 2003-09-09 | 2005-03-15 | 삼성전자주식회사 | Methods of fabricating a semiconductor device having a slope at lower side of interconnection hole with an etch stopping layer |
| KR20050116483A (en) * | 2004-06-07 | 2005-12-13 | 주식회사 하이닉스반도체 | Forming method of contact hole in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050026270A (en) * | 2003-09-09 | 2005-03-15 | 삼성전자주식회사 | Methods of fabricating a semiconductor device having a slope at lower side of interconnection hole with an etch stopping layer |
| KR20050116483A (en) * | 2004-06-07 | 2005-12-13 | 주식회사 하이닉스반도체 | Forming method of contact hole in semiconductor device |
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