KR100713315B1 - Method for forming non-salicide in fabricating semiconductor devices - Google Patents

Method for forming non-salicide in fabricating semiconductor devices Download PDF

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KR100713315B1
KR100713315B1 KR1020050131234A KR20050131234A KR100713315B1 KR 100713315 B1 KR100713315 B1 KR 100713315B1 KR 1020050131234 A KR1020050131234 A KR 1020050131234A KR 20050131234 A KR20050131234 A KR 20050131234A KR 100713315 B1 KR100713315 B1 KR 100713315B1
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oxide
salicide
etching
film
forming
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김경록
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Abstract

본 발명은 반도체 소자 제조 시 논-살리사이드 형성방법에 관한 것이다. 즉, 본 발명에서는 반도체 소자 제조 시 논-살리사이드 형성 공정에서 논-살리사이드 영역 형성을 위한 SAB 옥사이드를 식각 선택비가 서로 다른 산화막과 질화막/질산화막의 이중 구조로 형성하여 논-살리사이드 형성 후, SAB 옥사이드막 식각 시 상부 산화막과 질화막/질산화막, 그리고 질화막/질산화막 하부의 STI 필드 산화막간 식각 선택비에 따른 과식각이 방지되도록 함으로써, STI 필드 산화막 측벽부의 산화막 손실을 줄여 STI 필드 산화막 측벽부에서의 리키지 특성을 개선시키게 된다.The present invention relates to a method of forming a non-salicide in manufacturing a semiconductor device. That is, in the present invention, in forming a non-salicide region during fabrication of a semiconductor device, after forming non-salicide, a SAB oxide for forming a non-salicide region is formed in a double structure of an oxide film and a nitride / nitride film having different etching selectivity. When the SAB oxide layer is etched, the over-etch due to the etching selectivity between the upper oxide layer, the nitride layer / nitride layer, and the STI field oxide layer below the nitride layer / nitride layer is prevented, thereby reducing the oxide loss of the sidewall portion of the STI field oxide layer. It will improve the liquidity characteristics in wealth.

논-살리사이드, STI, 질화막, 질산화막, 옥사이드 Non-salicide, STI, Nitride, Nitride, Oxide

Description

반도체 소자 제조 공정 시 논-살리사이드 형성 방법{METHOD FOR FORMING NON-SALICIDE IN FABRICATING SEMICONDUCTOR DEVICES}METHOD FOR FORMING NON-SALICIDE IN FABRICATING SEMICONDUCTOR DEVICES

도 1a 내지 도 1b는 종래 논-살리사이드 영역 형성을 위한 SAB 옥사이드 식각 시 STI 필드 산화막 측벽부의 산화막 손실 모식도,1A to 1B are schematic diagrams of oxide loss of an STI field oxide sidewall portion during SAB oxide etching for forming a conventional non-salicide region;

도 2a 내지 도 2b는 본 발명의 실시 예에 따른 논-살리사이드 영역 형성을 위한 SAB 옥사이드 식각 시 STI 필드 산화막 측벽부의 산화막 손실 모식도.2A to 2B are schematic diagrams of oxide loss of an STI field oxide sidewall during SAB oxide etching for forming a non-salicide region according to an exemplary embodiment of the present invention.

<도면의 주요 부호에 대한 간략한 설명><Brief description of the major symbols in the drawings>

200 : STI 필드 산화막 202 : 질화막200: STI field oxide film 202: nitride film

204 : 산화막 206 : SAB 옥사이드204: oxide film 206: SAB oxide

210 : STI 필드 산화막 측벽부 210: STI field oxide sidewall

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 반도체 소자 제조 시 논-살리사이드(non-salicide) 영역 형성을 위한 SAB 옥사이드(oxide)를 식각 선택 비가 서로 다른 두 개의 절연막 구조로 형성하여, SAB 옥사이드 식각 시 두 절연막간 식각 선택비에 따른 과식각을 방지시킴으로써, SAB 옥사이드 하부에 위치하는 소자 분리막(shallow trench isolation :STI) 필드(field) 측벽부의 산화막 손실을 줄여 STI 필드 측벽부에서의 리키지 특성을 개선시키는 논-살리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, SAB oxide for forming a non-salicide region during semiconductor device fabrication is formed by forming two insulating layers having different etching selectivities, thereby forming SAB oxide. By preventing over-etching due to the etch selectivity between the two insulating layers during etching, the oxide characteristics of the shallow sidewall of the shallow trench isolation (STI) field located under the SAB oxide are reduced to reduce the leakage characteristics of the sidewall of the STI field. It relates to a non-salicide forming method to improve the.

통상적으로 반도체 소자 제조 공정에서는 소자의 동작 속도가 매우 중요한 요소로 작용하기 때문에 저항 감소를 위해 실리사이드(silicide)를 적용하고 있다. 이러한 실리사이드 형성 공정은 금속을 증착하고 열공정에 의해서 금속 실리사이드를 형성하게 되는데, 이때 실리콘으로 구성되어 있는 액티브 영역(active area)과 게이트(gate) 형성 물질인 폴리 실리콘(polly silicon) 위에만 실리사이드가 형성되고 나머지 절연 물질에는 형성이 되지 않게 하는 샐리사이드(Self Aligned Silicide) 공정을 채택하고 있다.In general, in the semiconductor device manufacturing process, silicide is applied to reduce resistance because the operation speed of the device is very important. This silicide forming process deposits metal and forms metal silicide by thermal process, in which silicide is formed only on the active area composed of silicon and on poly silicon, which is a gate forming material. It forms a self-aligned silicide process that is formed and is not formed in the remaining insulating material.

그러나, 이렇게 실리사이드가 형성된 영역은 저항이 매우 낮기 때문에 실제로 높은 저항이 요구되는 영역에서는 적용을 할 수 없으므로 반도체 기판 상 실리사이드가 형성되지 않아야 할 지역을 절연막으로 덮고 그 이외의 지역에서는 실리사이드를 형성시키는 논-살리사이드(Non-Salicide) 공정이 필요하게 된다.However, since the silicide-formed region is very low in resistance, it cannot be applied in a region where a high resistance is actually required. Thus, a field for covering the region where silicide should not be formed on the semiconductor substrate with an insulating film and forming silicide in other regions Non-Salicide process is needed.

상기 논-살리사이드(non-salicide) 공정은 살리사이드(salicide)를 형성하기 이전 반도체 기판 전면에 절연막을 증착하고 포토 마스크(photo-mask)를 이용하여 논-살리사이드 영역의 절연막은 보호하고 살리사이드 형성 영역의 절연막은 제거하게 된다.The non-salicide process deposits an insulating film on the entire surface of the semiconductor substrate before forming the salicide, and protects the insulating film in the non-salicide region by using a photo-mask. The insulating film in the side formation region is removed.

즉, 논-살리사이드 영역을 형성시키기 위한 일반적인 방법은 반도체 소자 분리막(STI)을 포함하는 반도체 기판 전면에 SAB 옥사이드를 증착하고 패터닝 한 후, 옥사이드 식각을 통한 절연막 제거를 통하여 실리사이드를 형성시킬 부분과 실리사이드를 형성시키지 않아야 할 부분으로 구분하여 형성시키며, 이때 상기 SAB 옥사이드 증착은 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방식을 이용한 TEOS막으로 보통 1000Å정도의 두께로 증착하게 된다.That is, a general method for forming a non-salicide region includes a portion to form silicide by depositing and patterning SAB oxide on the entire surface of a semiconductor substrate including a semiconductor device isolation layer (STI) and removing the insulating layer through oxide etching. The silicide is formed into portions that should not be formed, and the SAB oxide deposition is a TEOS film using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

그러나 종래 논-살리사이드 공정에서는 도 1a에서 보여지는 바와 같이 PE TEOS(Plasma Enhanced-Tetra Ethylene Ortho Silicate)에 의한 SAB 옥사이드(oxide)(104) 증착 시 STI 필드(field) 산화막(100) 측벽부의 단차에 의해 스텝 커버리지(step coverage) 불량(104)이 발생하여 STI 필드 산화막(100)의 증착 두께가 낮아지고, 이후 SAB 옥사이드(102) 식각 과정에서 과식각(over etch), 세정(clean) 등에 의해 도 1b에서 보여지는 바와 같이 STI 필드 산화막(100) 측벽부의 손실이 심화되어, 상기 산화막 손실이 심화된 STI 필드 산화막 측벽부위(110)로 후속 스퍼터링(sputtering) 공정에서 Co, Ti가 침투되어 실리사이드(silicide)가 깊게 형성되고 이 부분에서 리키지(leakage) 등의 특성이 나타나는 문제점이 있었다.However, in the conventional non-salicide process, as shown in FIG. 1A, when the SAB oxide 104 is deposited by Plasma Enhanced-Tetra Ethylene Ortho Silicate (PE TEOS), a step difference between the sidewalls of the STI field oxide film 100 is shown. As a result, poor step coverage 104 occurs, and the deposition thickness of the STI field oxide film 100 is lowered. Then, overetch, clean, etc., during the SAB oxide 102 etching process are performed. As shown in FIG. 1B, the loss of the sidewall portion of the STI field oxide film 100 is deepened, so that Co and Ti penetrates into the STI field oxide sidewall portion 110 where the oxide loss is increased in a subsequent sputtering process. There was a problem that the silicide was formed deep and the characteristics such as leakage (leakage) in this portion.

따라서, 본 발명의 목적은 반도체 소자 제조 시 논-살리사이드 영역 형성을 위한 SAB 옥사이드를 식각 선택비가 서로 다른 두 개의 절연막 구조로 형성하여, SAB 옥사이드 식각 시 두 절연막간 식각 선택비에 따른 과식각을 방지시킴으로써, SAB 옥사이드 하부에 위치하는 STI 필드 측벽부의 산화막 손실을 줄여 STI 필드 측 벽부에서의 리키지 특성을 개선시키는 논-살리사이드 형성방법을 제공함에 있다.Therefore, an object of the present invention is to form a SAB oxide for forming a non-salicide region in the semiconductor device fabrication with two insulating layers having different etching selectivity, so that the over-etching according to the etching selectivity between the two insulating layers during SAB oxide etching The present invention provides a method for forming a non-salicide which prevents oxide loss of an STI field sidewall portion located under the SAB oxide, thereby improving the leakage characteristics at the STI field side wall portion.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자 제조공정 시 논-살리사이드 형성 방법으로서, (a)반도체 기판상 논-살리사이드 영역 형성을 위한 살리사이드 블록킹막으로 식각 선택비가 다른 두 개의 절연막으로 구성된 SAB 옥사이드를 형성시키는 단계와, (b)상기 SAB 옥사이드가 상기 반도체 기판 상 상기 논-살리사이드 영역을 블록킹하도록 패터닝하는 단계와, (c)상기 논-살리사이드 영역인 STI 영역에 증착된 상기 SAB 옥사이드의 상부 제1 절연막을 해당 절연막 식각 분위기에서 1차 식각시키는 단계와, (d)상기 SAB 옥사이드의 상부 제1절연막 하부의 제2 절연막을 해당 절연막 식각 분위기에서 2차 식각시키는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a non-salicide in a semiconductor device manufacturing process, comprising: (a) a salicide blocking film for forming a non-salicide region on a semiconductor substrate; Forming a constructed SAB oxide, (b) patterning the SAB oxide to block the non-salicide region on the semiconductor substrate, and (c) the deposition on an STI region that is the non-salicide region First etching the upper first insulating film of SAB oxide in a corresponding insulating film etching atmosphere, and (d) second etching the second insulating film below the upper first insulating film of SAB oxide in a corresponding insulating film etching atmosphere. It is characterized by.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 2a 내지 도 2c는 본 발명의 논-살리사이드(non-salicide) 영역 형성을 위한 SAB 옥사이드(oxide) 식각 시 STI 필드 산화막 측벽부의 산화막 손실 모식도를 도시한 것이다. 이하 상기 도 2a 내지 도 2c를 참조하여 SAB 옥사이드 식각 시 STI 필드 산화막 측벽부의 산화막 손실을 줄여 STI 필드 산화막 측벽부에서의 리키지(leakage) 특성을 개선시키는 논-살리사이드 형성 공정을 상세히 설명하기로 한다.2A to 2C illustrate oxide loss schematic diagrams of STI field oxide sidewalls during SAB oxide etching for forming a non-salicide region of the present invention. Hereinafter, referring to FIGS. 2A to 2C, a non-salicide forming process of reducing oxide loss in STI field oxide sidewalls during SAB oxide etching to improve leakage characteristics in STI field oxide sidewalls will be described in detail. do.

먼저 일반적으로 PE-TEOS(Plasma Enhanced-Tetra Ethylene Ortho Silicate) 는 소정의 온도와 압력에서, RF 파워를 인가한 상태에서 TEOS 가스를 흘려 플라즈마를 형성하여 웨이퍼에 증착되는 산화막(SiO2) 구조의 막으로, 논-살리사이드 영역을 형성시키기 위해 반도체 기판상 논-살리사이드 영역인 STI 영역에 증착되는 SAB 옥사이드는 상기 PE-TEOS로 증착된다. 그러나 상기 PE-TEOS로 증착되는 SAB 옥사이드는 두께가 얇은 만큼 상대적으로 과식각 되는 양이 많아 STI 필드 산화막 측벽부에서 산화막 손실이 컷음은 전술한 바와 같다.In general, PE-TEOS (Plasma Enhanced-Tetra Ethylene Ortho Silicate) is an oxide film (SiO 2 ) structure that is deposited on a wafer by forming a plasma by flowing TEOS gas at a predetermined temperature and pressure with RF power applied thereto. As a result, SAB oxide deposited in the STI region, which is a non-salicide region on a semiconductor substrate, to form a non-salicide region is deposited with the PE-TEOS. However, the SAB oxide deposited by PE-TEOS has a relatively large amount of overetching due to its thin thickness, and thus, the loss of oxide loss in the STI field oxide sidewall portion is as described above.

따라서 본 발명에서는 STI 영역 상부에 증착되는 논-살리사이드(non-salicide) 영역 형성을 위한 SAB 옥사이드의 구성을 질화막(SiN)과 산화막(SiO2)으로 구성하여 산화막(SiO2)의 두께 차이가 발생하더라도 산화막(SiO2)과 질화막(SiN)간 식각 선택비(etch selectivity) 차이에 의해 과식각(over etch)이 방지되도록 한다. In this invention, rice is deposited over the STI region has a thickness difference between the salicide (non-salicide) SAB by configuring the structure of the oxide to nitride (SiN) film and an oxide film (SiO 2) an oxide film (SiO 2) for the region forming Even if it occurs, overetch is prevented by the difference in the etch selectivity between the oxide film SiO 2 and the nitride film SiN.

이하 본 발명의 설명에서는 설명의 편의상 SAB 옥사이드의 구성 중 산화막(SiO2)과 다른 식각 선택비를 가지는 절연막 물질로 질화막(SiN)을 예를 들어 설명하기로 하나, 산화막(SiO2)과 다른 식각 선택비를 가지는 질산화막(SiON) 등의 절연막 물질을 사용하는 경우에도 동일하게 적용 가능하다.Below the oxide film of the structure of convenience SAB oxide described in the description of the present invention (SiO 2) and a insulating material having a different etching selectivity one will be described, for example, a nitride film (SiN), an oxide film (SiO 2) and other etch The same applies to the case where an insulating material such as a nitride oxide film (SiON) having a selectivity is used.

즉, 상기 도 2a에서와 보여지는 바와 같이 본 발명에서는 STI 영역(200) 상부에 살리사이드 방어용 SAB 옥사이드(202)를 PE-TEOS로 증착시키되, 먼저 STI 영역(200)을 포함하는 반도체 기판 전체 표면에 질화막(SiN)(202)을 1차적으로 증착 시킨 후, 질화막(SiN)(202) 상부에 다시 식각 선택비가 다른 산화막(SiO2)(204)을 2차적으로 증착시킨다. 이에 따라 식각 선택비가 서로 다른 질화막(SiN)(202)과 산화막(SiO2)(204)으로 구성되는 살리사이드 방어용 SAB 옥사이드(oxide)(206)가 형성된다.That is, as shown in FIG. 2A, in the present invention, a salicide-defense SAB oxide 202 is deposited by PE-TEOS on the STI region 200, but first, the entire surface of the semiconductor substrate including the STI region 200. After the first deposition of the nitride film (SiN) 202, an oxide film (SiO 2 ) 204 having a different etching selectivity is deposited on the nitride film (SiN) 202 again. As a result, a salicide defense SAB oxide 206 including a nitride film (SiN) 202 and an oxide film (SiO 2 ) 204 having different etching selectivity is formed.

이후, 상기 살리사이드 방어용 SAB 옥사이드를 이용한 논-살리사이드 형성 공정 후, 상기 SAB 옥사이드(206) 식각 제거 시에는 먼저 제1 절연막인 산화막(SiO2) 식각 분위기에서 상부의 산화막(SiO2)(204) 만을 먼저 식각시킨다. Subsequently, after the non-salicide forming process using the salicide defense SAB oxide, when the SAB oxide 206 is etched, the first oxide layer (SiO 2 ), which is the first insulating layer, is etched from the upper oxide layer (SiO 2 ) 204. ) Etch only first.

이때 상기 산화막(SiO2) 식각 분위기에서의 산화막(SiO2)(204) 식각 시에는 식각 선택비에 따라 상기 도 2b에서와 같이 질화막(SiN)(202)에서 식각이 정지되어 하부 질화막(SiN)(202)까지 과식각이 발생하지 않는다. At this time, when etching the oxide film (SiO 2 ) 204 in the oxide film (SiO 2 ) etching atmosphere, the etching is stopped in the nitride film (SiN) 202 as shown in FIG. 2B according to the etching selectivity, and thus the lower nitride film (SiN) is etched. No over etching occurs until (202).

또한, 위와 같이 상부 산화막(SiO2)(204)에 대한 식각 후에는 식각 분위기를 제2절연막인 질화막(SiN)(202)의 식각 분위기로 전환하여 하부의 질화막(SiN)(202)에 대한 식각을 수행하게 되며, 상기 질화막(SiN)(202)의 식각에 따라 상기 도 2c에서와 같이 논-살리사이드 영역 형성을 위해 증착되었던 SAB 옥사이드(206)를 모두 식각시키게 된다.In addition, after etching the upper oxide film (SiO 2 ) 204 as described above, the etching atmosphere is changed to the etching atmosphere of the nitride film (SiN) 202, which is the second insulating film, to etch the lower nitride film (SiN) 202. According to the etching of the nitride film (SiN) 202, all of the SAB oxide 206 that has been deposited to form the non-salicide region as shown in FIG. 2C is etched.

이때 상기 질화막(SiN) 식각 분위기에서의 질화막(SiN)(202) 식각 시, 상기 질화막(SiN)(202) 하부의 STI 영역(200)이 상기 제1절연막과 동일한 산화막(SiO2)으로 형성되기 때문에 상기 질화막(SiN)(202)과의 식각 선택비에 따라 STI 필드 산화 막(SiO2)(200)에서 식각이 정지되며, 상기 도 2c에서와 같이 STI 필드 산화막 측벽부(210)에서 산화막 손실이 거의 발생하지 않게 된다.In this case, when the nitride layer (SiN) 202 is etched in the nitride layer (SiN) etching atmosphere, the STI region 200 under the nitride layer (SiN) 202 is formed of the same oxide layer (SiO 2 ) as the first insulating layer. Therefore, the etching is stopped in the STI field oxide film (SiO 2 ) 200 according to the etching selectivity with respect to the nitride film (SiN) 202, and the oxide film loss in the sidewall portion 210 of the STI field oxide film as shown in FIG. This rarely happens.

상기한 바와 같이 본 발명에서는 반도체 소자 제조 시 논-살리사이드 형성 공정에서 논-살리사이드 영역 형성을 위한 SAB 옥사이드를 식각 선택비가 서로 다른 산화막과 질화막/질산화막의 이중 구조로 형성하여 논-살리사이드 형성 후, SAB 옥사이드막 식각 시 상부 산화막과 질화막/질산화막, 그리고 질화막/질산화막 하부의 STI 필드 산화막간 식각 선택비에 따른 과식각이 방지되도록 함으로써, STI 필드 산화막 측벽부의 산화막 손실을 줄여 STI 필드 산화막 측벽부에서의 리키지 특성을 개선시키게 된다.As described above, in the present invention, the SAB oxide for forming the non-salicide region in the non-salicide formation process of the semiconductor device is formed by forming a double structure of an oxide film and a nitride / nitride film having different etching selectivity. After formation, over-etching due to the etch selectivity between the top oxide film, nitride film / nitride film, and the STI field oxide film under the nitride film / nitride film is prevented during SAB oxide film etching, thereby reducing the oxide loss of the STI field oxide sidewalls. It improves the leakage characteristic in the oxide film side wall part.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명에서는 반도체 소자 제조 시 논-살리사이드 형성 공정에서 논-살리사이드 영역 형성을 위한 SAB 옥사이드를 식각 선택비가 서로 다른 산화막과 질화막/질산화막의 이중 구조로 형성하여 논-살리사이드 형성 후, SAB 옥사이드막 식각 시 상부 산화막과 질화막/질산화막, 그리고 질화막/질산화막 하부의 STI 필드 산화막간 식각 선택비에 따른 과식각이 방지되도록 함으로 써, STI 필드 산화막 측벽부의 산화막 손실을 줄여 STI 필드 산화막 측벽부에서의 리키지 특성을 개선시키는 이점이 있다.As described above, in the present invention, the SAB oxide for forming the non-salicide region in the non-salicide formation process during semiconductor device manufacturing is formed by forming a double structure of an oxide film and a nitride / nitride film having different etching selectivity. After salicide formation, the oxide loss of the STI field oxide sidewalls is prevented by overetching according to the etching selectivity between the upper oxide layer, nitride layer / nitride layer, and the STI field oxide layer below the nitride layer / nitride layer during SAB oxide layer etching. In other words, there is an advantage of improving the leakage characteristics of the STI field oxide sidewalls.

Claims (6)

반도체 소자 제조공정 시 논-살리사이드 형성 방법으로서,As a method of forming a non-salicide in a semiconductor device manufacturing process, (a)반도체 기판상 논-살리사이드 영역 형성을 위한 살리사이드 블록킹막으로 식각 선택비가 다른 두 개의 절연막으로 구성된 SAB 옥사이드를 형성시키는 단계와,(a) forming a SAB oxide comprising two insulating films having different etching selectivities using a salicide blocking film for forming a non-salicide region on a semiconductor substrate, (b)상기 SAB 옥사이드가 상기 반도체 기판 상 상기 논-살리사이드 영역을 블록킹하도록 패터닝하는 단계와,(b) patterning the SAB oxide to block the non-salicide region on the semiconductor substrate; (c)상기 논-살리사이드 영역인 STI 영역에 증착된 상기 SAB 옥사이드의 상부 제1 절연막을 해당 절연막 식각 분위기에서 1차 식각시키는 단계와,(c) first etching the upper first insulating film of the SAB oxide deposited in the STI region, which is the non-salicide region, in an insulating film etching atmosphere; (d)상기 SAB 옥사이드의 상부 제1절연막 하부의 제2 절연막을 해당 절연막 식각 분위기에서 2차 식각시키는 단계(d) second etching the second insulating layer under the upper first insulating layer of the SAB oxide in a corresponding insulating layer etching atmosphere; 를 포함하는 반도체 소자 제조 공정 시 논-살리사이드 형성 방법.Non-salicide forming method in a semiconductor device manufacturing process comprising a. 제1항에 있어서,The method of claim 1, 상기 (a)단계에서, 상기 SAB 옥사이드는, PE-TEOS 로 증착시키는 것을 특징으로 하는 반도체 소자 제조 공정 시 논-살리사이드 형성 방법.In the step (a), the SAB oxide, non-salicide forming method in the semiconductor device manufacturing process, characterized in that the deposition by PE-TEOS. 제1항에 있어서,The method of claim 1, 상기 (c)단계에서, 상기 제1절연막의 1차 식각은, 상기 제2절연막과의 식각 선택비에 따라 상기 제2절연막에서 식각이 정지되는 것을 특징으로 하는 반도체 소자 제조 공정 시 논-살리사이드 형성 방법.In the step (c), the first etching of the first insulating layer, the etching is stopped in the second insulating layer according to the etching selectivity with the second insulating layer, non-salicide during the semiconductor device manufacturing process Forming method. 제1항에 있어서,The method of claim 1, 상기 (d)단계에서, 상기 제2절연막의 2차 식각은, 상기 제2절연막 하부의 STI 필드 산화막과의 식각 선택비에 따라 상기 STI 필드 산화막에서 식각이 정지되는 것을 특징으로 하는 반도체 소자 제조 공정 시 논-살리사이드 형성 방법.In the step (d), the second etching of the second insulating film, the semiconductor device manufacturing process characterized in that the etching is stopped in the STI field oxide film according to the etching selectivity with the STI field oxide film under the second insulating film. Cynon-salicide formation method. 제1항에 있어서,The method of claim 1, 상기 제1/제2절연막은, 각각 산화막(SiO2)과 질화막(SiN)으로 형성되는 것을 특징으로 하는 반도체 소자 제조 공정 시 논-살리사이드 형성 방법.And the first and second insulating layers are formed of an oxide film (SiO 2 ) and a nitride film (SiN), respectively. 제1항에 있어서,The method of claim 1, 상기 제1/제2절연막은, 산화막(SiO2)과 질산화막(SiON)으로 형성되는 것을 특징으로 하는 반도체 소자 제조 공정 시 논-살리사이드 형성 방법.The first / second insulating layer is formed of an oxide film (SiO 2 ) and a nitride oxide (SiON), characterized in that the non-salicide forming method in the semiconductor device manufacturing process.
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