KR100673110B1 - A method for sensing a bit line of a semiconductor device - Google Patents
A method for sensing a bit line of a semiconductor device Download PDFInfo
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- KR100673110B1 KR100673110B1 KR1019990066329A KR19990066329A KR100673110B1 KR 100673110 B1 KR100673110 B1 KR 100673110B1 KR 1019990066329 A KR1019990066329 A KR 1019990066329A KR 19990066329 A KR19990066329 A KR 19990066329A KR 100673110 B1 KR100673110 B1 KR 100673110B1
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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Abstract
본 발명은 반도체소자의 비트라인 센싱(sensing)방법에 관한 것으로, The present invention relates to a bit line sensing method of a semiconductor device.
센스 앰프에서 센싱시 비트라인과 게이트산화막 캐패시터를 이용하여 폴디드 비트라인 구조를 형성하여 비트라인을 센싱함으로써 폴디드 비트라인 센스앰프 구조의 노이즈를 감소시키고 리프레쉬 특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.When sensing in a sense amplifier, a folded bit line structure is formed using a bit line and a gate oxide capacitor to sense a bit line, thereby reducing noise and improving refresh characteristics of the folded bit line sense amplifier structure, thereby improving the characteristics and reliability of the semiconductor device. It is a technology that enables to improve the integration and accordingly high integration of semiconductor devices.
Description
도 1 은 종래기술에 따른 반도체소자의 비트라인 센싱방법을 도시한 개략도.1 is a schematic diagram illustrating a bit line sensing method of a semiconductor device according to the prior art.
도 2 는 본 발명의 제1실시예에 따른 반도체소자의 비트라인 센싱방법을 도시한 개략도.2 is a schematic diagram illustrating a bit line sensing method of a semiconductor device according to a first exemplary embodiment of the present invention.
도 3 은 본 발명의 제3실시예에 따른 반도체소자의 비트라인 센싱방법을 도시한 개략도.3 is a schematic diagram illustrating a bit line sensing method of a semiconductor device according to a third exemplary embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
ⓐ : 게이트산화막 캐패시터Ⓐ: gate oxide capacitor
본 발명은 반도체소자의 비트라인 센싱방법에 관한 것으로, 특히 기존의 비트라인(BIT)과 비트바아 라인(/BIT)를 사용하는 대신에 BIT 과 게이트산화막 캐패시터를 사용하여 센싱 ( sensing ) 하도록 하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for sensing a bit line of a semiconductor device, and more particularly, a technology for sensing by using a BIT and a gate oxide capacitor instead of using a conventional bit line and a bit bar line. It is about.
일반적으로, 디램의 입출력 회로나 주변회로는 비교적 큰 전압 진폭 ( 0.9∼5V ) 논리동작이 주를 이루므로 셀 어레이에 비해 노이즈의 영향이 상대적으로 적다.In general, a relatively large voltage amplitude (0.9 to 5V) logic operation of a DRAM input / output circuit or a peripheral circuit is relatively less affected by noise than a cell array.
셀은 자체에 증폭 작용이 없으므로 리드 ( read ) 시 전하분배 ( charge sharing ) 에 의해 100 ∼ 250 mV 의 낮은 신호 전압이 나타나며 이후 센스 앰프에 의한 증폭 과정에서 비트라인에 발생하는 차동 잡음에 의해 메모리 셀의 전압 마진이 결정된다.Since the cell does not have an amplification effect on its own, a low signal voltage of 100 to 250 mV appears due to charge sharing during reads, and the memory cell is caused by differential noise generated in the bit line during amplification by a sense amplifier. The voltage margin of is determined.
디램의 용량이 증가함에 따라 한꺼번에 충방전되어야 하는 비트라인의 수가 2배씩 증가하므로 이만큼 잡음도 증가하며 미세화와 함께 셀 어레이를 구성하는 각종 배선의 커플링 캐패시턴스가 증가하여 이에 의한 잡음도 증가한다.As the capacity of the DRAM increases, the number of bit lines that need to be charged and discharged at a time increases by twice, thus increasing the noise. As a result, the noise increases due to the miniaturization and the coupling capacitance of various wirings forming the cell array.
또한 서브 마이크론 트랜지스터의 특성 편차가 상대적으로 심하므로 센스 앰프의 옵섹 ( offset ) 도 증가하여 이에 의한 잡음도 커진다.In addition, since the characteristic deviation of the sub-micron transistor is relatively severe, the offset of the sense amplifier increases, thereby increasing the noise.
상기한 바와같이 메모리 셀 내부의 잡음을 제거하기 위하여, 최근에는 폴디드 비트라인 ( folded bit line ) 을 형성하여 사용하였다.As described above, in order to remove noise inside the memory cell, a folded bit line has recently been used.
그러나, 상기 폴디드 비트라인 센스앰프의 경우는 비트라인과 비트바아 라인으로 센싱하여 데이타를 읽는데, 읽고 있는 비트라인과 비트바아 라인의 아래위도 같이 센싱하여 노이즈를 많이 받게 되고 그로 인한 오동작과 리프레쉬 ( refresh ) 특성을 열화시키는 원인이 된다.However, in the case of the folded bit line sense amplifier, data is sensed by bit lines and bit bar lines to read data, and the bit lines and bit bar lines that are being read are also sensed up and down to receive a lot of noise, resulting in malfunction and refresh ( refresh) causes the property to deteriorate.
도 1 은 종래기술에 따른 반도체소자의 비트라인 센싱방법을 도시한 개략도로서, 비트라인과 비트바아 라인 각각 센스앰프에 센싱하는 것이다.1 is a schematic diagram illustrating a bit line sensing method of a semiconductor device according to the prior art, in which a bit line and a bit bar line are respectively sensed by a sense amplifier.
상기한 바와같이 종래기술에 따른 반도체소자의 비트라인 센싱방법은, 센싱 동작시 잡음으로 인하여 오동작이 유발될 수 있으며, 리프레쉬 특성이 열화될 수 있어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the bit line sensing method of a semiconductor device according to the related art, malfunction may occur due to noise during sensing operation, and refresh characteristics may deteriorate, thereby degrading the characteristics and reliability of the semiconductor device and thereby the semiconductor device. There is a problem that makes it difficult to integrate.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 비트라인과 비트바아 라인 대신에 비트라인과 게이트산화막 트랜지스터를 이용하여 센싱함으로써 소자의 특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 비트라인 센싱방법을 제공하는데 그 목적이 있다.The present invention improves the characteristics of the device by sensing the bit line and the gate oxide transistor instead of the bit line and the bit bar line in order to solve the above problems of the prior art to improve the characteristics and reliability of the semiconductor device It is an object of the present invention to provide a bit line sensing method of a semiconductor device that enables high integration of the semiconductor device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 비트라인 센싱방법은,
폴디드 비트라인 구조를 갖는 반도체소자의 비트라인 센싱방법에 있어서,
비트라인과 비트바아 라인를 프리차지 시키는 제 1 단계와,
비트라인에 실린 셀의 데이타가 센스앰프에 의해 센싱되는 제 2 단계
를 포함하되, 상기 비트바아 라인는 게이트산화막 캐패시터인 것을 특징으로 하고,In order to achieve the above object, a bit line sensing method of a semiconductor device according to the present invention,
In the bit line sensing method of a semiconductor device having a folded bit line structure,
A first step of precharging the bit line and the bit bar line,
Second step in which the data of the cell on the bit line is sensed by the sense amplifier
Including, but the bit bar line is characterized in that the gate oxide capacitor,
삭제delete
상기 게이트산화막 캐패시터는 상기 비트라인의 캐패시터 캐패시턴스와 동일하게 하여 형성하고,The gate oxide capacitor is formed in the same manner as the capacitor capacitance of the bit line,
상기 게이트산화막 캐패시터 대신에 고농도의 엔형 불순물 접합영역 캐패시터를 이용하여 형성하고,Instead of the gate oxide capacitor, a high concentration of an en-type impurity junction region capacitor is formed,
상기 센스앰프와 연결된 제 1 비트라인은 이웃하는 센스앰프와 연결된 제 2 비트라인과 교차되어 형성됨을 특징으로 한다.The first bit line connected to the sense amplifier is formed to cross the second bit line connected to the neighboring sense amplifier.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 제1실시예에 따른 반도체소자의 비트라인 센싱방법을 도시한 개략도로서, 비트라인과 게이트산화막 캐패시터 ⓐ 를 이용하여 센싱하는 폴디드 비트라인 방식을 도시한다.FIG. 2 is a schematic diagram illustrating a bit line sensing method of a semiconductor device according to a first embodiment of the present invention, and illustrates a folded bit line method for sensing by using a bit line and a gate oxide capacitor ⓐ.
이때, 상기 게이트산화막 캐패시터의 일측, 즉 상기 센스앰프의 바깥쪽은 그라운드시키고 타측, 즉 상기 센스앰프의 바깥쪽은 센스 앰프에 연결된다.At this time, one side of the gate oxide capacitor, that is, the outside of the sense amplifier is grounded, and the other side, that is, the outside of the sense amplifier is connected to the sense amplifier.
그리고, 상기 게이트산화막 캐패시터는 상기 비트라인 캐패시터와 동일하게 형성한다.The gate oxide capacitor is formed in the same manner as the bit line capacitor.
상기 비트라인의 센싱 방법은 다음과 같다.The sensing method of the bit line is as follows.
센싱은 비트라인과 비트바아 라인를 이용한 센싱에서와 같이 게이트산화막 캐패시터와 비트라인을 하프 Vcc 로 프리차지 시킨후 센스앰프가 비트라인에 걸린 셀의 데이타가 하이 ( high ) 이면 비트라인의 전위를 Vcc 로 높이고 게이트산화막의 전위는 Vss 로 내려 센싱을 하게 된다. Sensing precharges the gate oxide capacitor and bit line to half Vcc as in sensing using bit line and bit bar line. If the data of the cell where the sense amplifier is on the bit line is high, the potential of the bit line is changed to Vcc. The potential of the gate oxide is lowered to Vss and sensed.
반대로, 비트라인에 걸린 데이타가 로우 ( low ) 이면 비트라인의 전위를 Vss 로 내리고 게이트산화막 캐패시터의 전위를 Vcc 로 높여 센싱하게 한다.On the contrary, when the data on the bit line is low, the potential of the bit line is lowered to Vss and the potential of the gate oxide capacitor is raised to Vcc to sense.
상기한 바와같이 센싱의 동작은, 비트라인과 비트바아 라인를 사용할때와 동일하며 단지 비트바아 라인 대신에 게이트산화막 캐패시터를 사용한 것일 뿐이다.As described above, the sensing operation is the same as when using the bit line and the bit bar line, and merely uses a gate oxide capacitor instead of the bit bar line.
본 발명의 제2실시예는 상기 게이트산화막 캐패시터 대신에 고농도의 엔형 불순물 접합영역 캐패시터를 사용하는 것이다.
본 발명의 제3실시예는 상기한 제1실시예와 같이 형성된 비트라인과 게이트산화막 캐패시터로 구비되는 폴디드 비트라인 구조에서 도 3에 도시된 바와 같이, 센스앰프와 연결된 비트라인 BIT1과 상기 센스앰프와 이웃하는 센스앰프와 연결된 비트라인 BIT2을 교차시켜 형성함으로써 커플링 노이즈로 인한 잡음의 유발을 방지하는 것이다. In a second embodiment of the present invention, a high concentration of an en-type impurity junction region capacitor is used in place of the gate oxide capacitor.
According to the third embodiment of the present invention, in the folded bit line structure including the bit line and the gate oxide capacitor formed as in the first embodiment, the bit line BIT1 connected to the sense amplifier and the sense as shown in FIG. By forming the bit line BIT2 connected to the amplifier and the neighboring sense amplifier, it prevents the noise caused by the coupling noise.
예를 들어, 비트라인 BIT1에 '0' 데이터가 실릴 때, 비트라인 BIT2에 비트라인 BIT1에 실린 데이터와 반대 데이터, 즉 '1' 데이터가 실리는 경우 비트라인 BIT2에 의해 비트라인 BIT1에 커플링 노이즈가 유발된다. 그러나, 비트라인 BIT1과 비트라인 BIT2가 교차되어 형성되어 있기 때문에 종래와 같이 비트라인이 교차되지 않은 경우에 비해 커플링 노이즈의 영향을 감소시킬 수 있다.For example, when '0' data is loaded on the bit line BIT1, if the data loaded on the bit line BIT2 is opposite to the data loaded on the bit line BIT1, that is, '1' data is coupled to the bit line BIT1 by the bit line BIT2 Noise is caused. However, since the bit lines BIT1 and the bit lines BIT2 are formed to cross each other, the influence of the coupling noise can be reduced as compared with the case where the bit lines are not crossed as in the related art.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 비트라인 센싱방법은, 게이트산화막 캐패시터를 사용하여 커플링 노이즈 캐패시터의 감소를 가능하게 하여 소자의 동작속도를 향상시키고 리프레쉬 특성을 향상시킬 수 있고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키며 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the bit line sensing method of the semiconductor device according to the present invention can reduce the coupling noise capacitor by using the gate oxide capacitor, thereby improving the operation speed of the device and improving the refresh characteristics. It improves the characteristics and reliability of the semiconductor device and provides the effect of enabling high integration of the semiconductor device.
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| KR19980058196A (en) * | 1996-12-30 | 1998-09-25 | 문정환 | Structure of Cell Array and Sense Amplifier with Improved Noise Characteristics |
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|---|---|---|---|---|
| US4003034A (en) * | 1975-05-23 | 1977-01-11 | Fairchild Camera And Instrument Corporation | Sense amplifier circuit for a random access memory |
| JPH07202021A (en) * | 1993-12-28 | 1995-08-04 | Toshiba Corp | Semiconductor storage device |
| KR19980058196A (en) * | 1996-12-30 | 1998-09-25 | 문정환 | Structure of Cell Array and Sense Amplifier with Improved Noise Characteristics |
| KR20010005157A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Semiconductor device |
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|---|---|
| KR20010058953A (en) | 2001-07-06 |
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