KR100636912B1 - Method for forming dual gate of semiconductor device - Google Patents

Method for forming dual gate of semiconductor device Download PDF

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KR100636912B1
KR100636912B1 KR1020050065785A KR20050065785A KR100636912B1 KR 100636912 B1 KR100636912 B1 KR 100636912B1 KR 1020050065785 A KR1020050065785 A KR 1020050065785A KR 20050065785 A KR20050065785 A KR 20050065785A KR 100636912 B1 KR100636912 B1 KR 100636912B1
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layer
polysilicon
forming
tungsten silicide
thin film
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Korean (ko)
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황윤택
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A method for forming a dual gate in a semiconductor device is provided to improve the capability of a semiconductor device by forming a stack structure of a silicon-rich tungsten silicide thin film and an amorphous polysilicon thin film between a polysilicon layer and a tungsten silicide layer. An isolation layer(110), an N-type well region(120) and a P-type well region(130) are formed on a semiconductor substrate(100). A gate oxide layer and a polysilicon layer are formed on the resultant structure. A first photoresist layer pattern is formed on the P-type well region, and P-type impurities are implanted into the polysilicon layer in the N-type well region by using the first photoresist layer pattern as a mask. A second photoresist layer pattern is formed on the N-type well region, and N-type impurities are implanted into the polysilicon layer in the P-type well region by using the second photoresist layer pattern as a mask. After a tungsten silicide thin film and an amorphous polysilicon thin film are formed on the resultant structure, a tungsten silicide layer is formed. A hard mask nitride layer and an ARC(anti-reflective coating) are formed on the resultant structure. The gate oxide layer, the polysilicon layer, the tungsten silicide thin film, the amorphous polysilicon thin film and the tungsten silicide layer are patterned to form dual gate electrodes(230,240) on the N-type and P-type well regions, respectively.

Description

반도체소자의 듀얼 게이트 형성방법{Method for forming dual gate of semiconductor device}Method for forming dual gate of semiconductor device

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체소자의 듀얼 게이트 형성방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device in accordance with an embodiment of the present invention.

< 도면의 주요 부분에 대한 설명 ><Description of Main Parts of Drawings>

100 : 반도체 기판 110 : 소자분리막100 semiconductor substrate 110 device isolation film

120 : N형 웰 130 : P형 웰120: N type well 130: P type well

140 : 게이트 산화막층 150 : 폴리실리콘층140: gate oxide layer 150: polysilicon layer

160 : 제 1 감광막 패턴 170 : 제 2 감광막 패턴160: first photosensitive film pattern 170: second photosensitive film pattern

180 : 텅스텐 실리사이드 박막층 190 : 비정질 폴리실리콘 박막층180: tungsten silicide thin film layer 190: amorphous polysilicon thin film layer

200 : 텅스텐 실리사이드층 210 : 하드마스크 질화막층200: tungsten silicide layer 210: hard mask nitride film layer

220 : 반사방지막220: antireflection film

본 발명은 반도체소자의 듀얼 게이트 형성방법에 관한 것으로, 특히 게이트 형성과정에서 폴리실리콘층과 텅스텐 실리사이드층 사이에 실리콘-리치(silicon- rich) 텅스텐 실리사이드(WSix) 박막층과 비정질(amorphous) 폴리실리콘 박막층의 적층구조를 형성하여 반도체소자의 성능향상을 가져오는 반도체소자의 듀얼 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dual gate of a semiconductor device, and in particular, a silicon-rich tungsten silicide (WSix) thin film layer and an amorphous polysilicon thin film layer between a polysilicon layer and a tungsten silicide layer during a gate formation process. The present invention relates to a method of forming a dual gate of a semiconductor device in which the stacked structure of the semiconductor device improves the performance of the semiconductor device.

주지된 바와 같이, CMOS 소자는 NMOS와 PMOS 영역에서 모두 N+ 도핑된 폴리실리콘 게이트 전극을 형성하여 왔는데, 이 방법의 경우 PMOS 영역에서 매립 채널(buried channel)이 형성되어 쇼트 채널 효과(short channel effect)가 증대되는 문제점이 발생하였다.As is well known, CMOS devices have formed N + doped polysilicon gate electrodes in both NMOS and PMOS regions, in which case a buried channel is formed in the PMOS region, resulting in a short channel effect. There is a problem that is increased.

이에 따라, 최근에는 NMOS 영역의 게이트 폴리실리콘에는 N+ 도핑을 적용하고, PMOS 영역의 게이트 폴리실리콘에는 P+ 도핑을 적용하는 듀얼 게이트(dual gate) 형성방법이 이용되고 있으며, 이러한 듀얼 게이트 형성방법의 경우 NMOS 및 PMOS 영역 모두에서 표면 채널(surface channel)을 형성시켜서 상기 매립 채널로 인한 문제점을 해결한다.Accordingly, recently, a dual gate forming method using N + doping is applied to the gate polysilicon of the NMOS region and P + doping is applied to the gate polysilicon of the PMOS region. In the case of such a dual gate forming method, Surface channels are formed in both NMOS and PMOS regions to solve the problems caused by the buried channels.

듀얼 게이트 적용을 위한 공정에 있어, NMOS와 PMOS 영역의 각 게이트 전극용 폴리실리콘층은 동시에 증착되고 패터닝되기 때문에, 먼저 도핑되지 않은 폴리실리콘을 증착하고 NMOS와 PMOS의 각 게이트 영역에 서로 다른 타입의 불순물을 도핑하기 위하여 선택적 이온주입 공정이 적용된다.In the process for dual gate application, since the polysilicon layers for each gate electrode in the NMOS and PMOS regions are deposited and patterned at the same time, first, undoped polysilicon is deposited and a different type of gate is formed in each gate region of the NMOS and PMOS regions. Selective ion implantation processes are applied to dope the impurities.

통상적으로, NMOS 영역의 게이트 폴리실리콘에는 인(Phosporous, P)을 이온주입하는 방법을 적용하고, PMOS 영역의 게이트 폴리실리콘에는 붕소(Boron, B)를 이온주입하는 방법을 적용하고 있다.In general, a method of ion implanting phosphorous (P) is applied to the gate polysilicon of the NMOS region, and a method of ion implantation of boron (Bron) B is applied to the gate polysilicon of the PMOS region.

종래의 듀얼 게이트 형성방법은 다음과 같다.The conventional dual gate forming method is as follows.

먼저, 반도체 기판 상에 소자분리막을 형성하고, PMOS 영역에는 N형 웰을, NMOS 영역에는 P형 웰을 각각 형성한다.First, an isolation layer is formed on a semiconductor substrate, and an N type well is formed in a PMOS region, and a P type well is formed in an NMOS region, respectively.

이어 상부에 게이트 산화막층 및 폴리실리콘층을 형성한다.Subsequently, a gate oxide layer and a polysilicon layer are formed on the top.

감광막패턴을 마스크로 하여 NMOS 영역의 폴리실리콘층에는 N형 불순물을, PMOS 영역의 폴리실리콘층에는 P형 불순물을 주입한다.Using a photosensitive film pattern as a mask, N-type impurities are injected into the polysilicon layer in the NMOS region, and P-type impurities are injected into the polysilicon layer in the PMOS region.

이어 전체 표면 상부에 텅스텐 실리사이드층을 형성한다.A tungsten silicide layer is then formed over the entire surface.

종래의 듀얼 게이트 형성방법에서는 후속 열공정으로 인해 폴리실리콘층 내에 주입된 불순물 이온이 텅스텐 실리사이드층으로 확산되어 PMOS의 문턱 전압 변이 및 반도체 소자의 성능 저하를 가져오는 문제점이 있다.In the conventional dual gate forming method, impurity ions implanted in the polysilicon layer are diffused into the tungsten silicide layer due to a subsequent thermal process, resulting in a threshold voltage variation of the PMOS and performance degradation of the semiconductor device.

상기 문제점을 해결하기 위하여, 본 발명은 게이트 형성과정에서 폴리실리콘층과 텅스텐 실리사이드층 사이에 실리콘-리치 텅스텐 실리사이드 박막층과 비정질 폴리실리콘 박막층의 적층구조를 형성하여 반도체소자의 성능향상을 가져오는 반도체소자의 듀얼 게이트 형성방법을 제공하는 것을 목적으로 한다.In order to solve the above problems, the present invention forms a stacked structure of the silicon-rich tungsten silicide thin film layer and the amorphous polysilicon thin film layer between the polysilicon layer and the tungsten silicide layer during the gate formation process, thereby improving the performance of the semiconductor device. An object of the present invention is to provide a dual gate forming method.

본 발명에 따른 반도체소자의 듀얼 게이트 형성방법은 반도체 기판 상부에 소자분리막과 N형 웰 영역 및 P형 웰 영역을 형성하는 단계; 전체 표면 상부에 게이트 산화막층과 폴리실리콘층을 형성하는 단계; P형 웰 영역 상부에 제 1 감광막패턴을 형성하고, 제 1 감광막패턴을 마스크로 하여 N형 웰 영역의 폴리실리콘층에 P형 불순물을 주입하는 단계; N형 웰 영역 상부에 제 2 감광막패턴을 형성하고, 제 2 감광막패턴을 마스크로 하여 P형 웰 영역의 폴리실리콘층에 N형 불순물을 주입하는 단계; 전체 표면 상부에 텅스텐 실리사이드(WSix) 박막층과 비정질 폴리실리콘 박막층을 형성한 후, 텅스텐 실리사이드(WSix)층을 형성하는 단계; 및 적층된 게이트 산화막층, 폴리실리콘층, 텅스텐 실리사이드(WSix) 박막층, 비정질 폴리실리콘 박막층 및 텅스텐 실리사이드(WSix)층을 패터닝하여 N형 웰 영역 및 P형 웰 영역 상부에 각각 듀얼 게이트 전극을 형성하는 단계를 포함한다.A method of forming a dual gate of a semiconductor device according to the present invention may include forming an isolation layer, an N-type well region, and a P-type well region on a semiconductor substrate; Forming a gate oxide layer and a polysilicon layer over the entire surface; Forming a first photoresist pattern on the P-type well region, and implanting P-type impurities into the polysilicon layer of the N-type well region using the first photoresist pattern as a mask; Forming a second photoresist pattern on the N-type well region, and implanting N-type impurities into the polysilicon layer of the P-type well region using the second photoresist pattern as a mask; Forming a tungsten silicide (WSix) thin film layer and an amorphous polysilicon thin film layer on the entire surface, and then forming a tungsten silicide (WSix) layer; And patterning the stacked gate oxide layer, the polysilicon layer, the tungsten silicide (WSix) thin film layer, the amorphous polysilicon thin film layer, and the tungsten silicide (WSix) layer to form dual gate electrodes on the N-type well region and the P-type well region, respectively. Steps.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체소자의 듀얼 게이트 형성방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device in accordance with an embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(100) 상부에 소자분리막(110)과 PMOS 영역에는 N형 웰(120)을, NMOS 영역에는 P형 웰(130)을 각각 형성한다.Referring to FIG. 1A, an N-type well 120 is formed in an isolation layer 110 and a PMOS region, and a P-type well 130 is formed in an NMOS region, respectively, on the semiconductor substrate 100.

이어 전체 표면 상부에 게이트 산화막층(140)과 폴리실리콘층(150)을 형성한다.Subsequently, the gate oxide layer 140 and the polysilicon layer 150 are formed on the entire surface.

폴리실리콘층(150)은 도핑된 폴리실리콘 또는 도핑되지 않은 폴리실리콘으로 형성할 수 있다.The polysilicon layer 150 may be formed of doped polysilicon or undoped polysilicon.

폴리실리콘층(150)이 도핑된 폴리실리콘으로 형성되는 경우, 주입되는 불순물은 N형이고, 상기 불순물의 도핑농도는 1E20 내지 4E20/cm3 인 것이 바람직하다.When the polysilicon layer 150 is formed of doped polysilicon, the implanted impurities are N-type, and the doping concentration of the impurities is preferably 1E20 to 4E20 / cm 3 .

도 1b를 참조하면, P형 웰 영역(130) 상부에 제 1 감광막패턴(160)을 형성하 고, 제 1 감광막패턴(160)을 마스크로 하여 N형 웰 영역(120)의 폴리실리콘층(150)에 P형 불순물을 주입한다. 그리고 제 1 감광막패턴(160)을 제거한다.Referring to FIG. 1B, the polysilicon layer of the N-type well region 120 is formed by forming a first photoresist pattern 160 on the P-type well region 130 and using the first photoresist pattern 160 as a mask. P-type impurity is injected into 150). Then, the first photoresist pattern 160 is removed.

상기 P형 불순물은 11B이온 또는 BF2이온인 것이 바람직하다. 그리고, 상기 11B이온은 3 내지 5KeV의 이온 에너지로 1E15 내지 5E15/cm2의 도즈량을 갖도록 주입하는 것이 바람직하고, 상기 BF2이온은 10 내지 22KeV의 이온 에너지로 1E15 내지 5E15/cm2의 도즈량을 갖도록 주입하는 것이 바람직하다.The P-type impurity is preferably from 11 B ion or BF 2 ions. In addition, the 11 B ion is preferably implanted to have a dose of 1E15 to 5E15 / cm 2 at an ion energy of 3 to 5 KeV, and the BF 2 ion is 1E15 to 5E15 / cm 2 at an ion energy of 10 to 22 KeV. It is preferable to inject to have a dose.

도 1c를 참조하면, N형 웰 영역(120) 상부에 제 2 감광막패턴(170)을 형성하고, 제 2 감광막패턴(170)을 마스크로 하여 P형 웰 영역(130)의 폴리실리콘층(150)에 N형 불순물을 주입한다. 그리고 제 2 감광막패턴(170)을 제거한다.Referring to FIG. 1C, a polysilicon layer 150 of the P-type well region 130 is formed by forming a second photoresist pattern 170 on the N-type well region 120 and using the second photoresist pattern 170 as a mask. Inject N-type impurities into the Then, the second photoresist layer pattern 170 is removed.

상기 N형 불순물은 31P이온인 것이 바람직하다. 그리고, 상기 31P이온은 10 내지 15KeV의 이온 에너지로 1E15 내지 5E15/cm2의 도즈량을 갖도록 주입하는 것이 바람직하다.It is preferable that the said N-type impurity is 31 P ion. In addition, the 31 P ion is preferably implanted with a dose of 1E15 to 5E15 / cm 2 at an ion energy of 10 to 15 KeV.

도 1d를 참조하면, 전체 표면 상부에 텅스텐 실리사이드(WSix) 박막층(180)과 비정질 폴리실리콘 박막층(190)을 형성한 후, 텅스텐 실리사이드층(WSix)(200)을 형성한다.Referring to FIG. 1D, after forming the tungsten silicide (WSix) thin film layer 180 and the amorphous polysilicon thin film layer 190 on the entire surface, a tungsten silicide layer (WSix) 200 is formed.

텅스텐 실리사이드(WSix) 박막층(180)은 실리콘 함유량(x)이 0.26 보다 큰 실리콘-리치(silicon-rich) 텅스텐 실리사이드(WSix)로 형성되는 것이 바람직하다. 그리고, 텅스텐 실리사이드(WSix) 박막층(180)의 두께는 20 ~ 100 Å인 것이 바람직하다.The tungsten silicide (WSix) thin film layer 180 is preferably formed of silicon-rich tungsten silicide (WSix) having a silicon content (x) of greater than 0.26. In addition, the thickness of the tungsten silicide (WSix) thin film layer 180 is preferably 20 to 100 GPa.

비정질 폴리실리콘 박막층(190)의 두께는 20 ~ 100 Å인 것이 바람직하다.The thickness of the amorphous polysilicon thin film layer 190 is preferably 20 to 100 mm 3.

도 1e를 참조하면, 전체 표면 상부에 하드마스크 질화막층(210)과 반사방지막(anti-reflection coating, ARC)층(220)을 형성한다.Referring to FIG. 1E, a hard mask nitride layer 210 and an anti-reflection coating (ARC) layer 220 are formed on the entire surface.

도 1f를 참조하면, N형 웰 영역(120) 상부에 P형 게이트 전극의 형성을 위한 감광막패턴을 형성한 후 적층된 게이트 산화막층(140), 폴리실리콘층(150), 텅스텐 실리사이드(WSix) 박막층(180), 비정질 폴리실리콘 박막층(190), 텅스텐 실리사이드(WSix)층(200), 및 하드마스크 질화막층(210)을 패터닝하여 P형 게이트 전극(230)을 형성한다.Referring to FIG. 1F, a gate oxide layer 140, a polysilicon layer 150, and tungsten silicide WSix are formed after forming a photoresist pattern for forming a P-type gate electrode on an N-type well region 120. The thin film layer 180, the amorphous polysilicon thin film layer 190, the tungsten silicide (WSix) layer 200, and the hard mask nitride layer 210 are patterned to form the P-type gate electrode 230.

이어 P형 웰 영역(130) 상부에 N형 게이트 전극의 형성을 위한 감광막패턴을 형성한 후 적층된 게이트 산화막층(140), 폴리실리콘층(150), 텅스텐 실리사이드(WSix) 박막층(180), 비정질 폴리실리콘 박막층(190), 텅스텐 실리사이드(WSix)층(200), 및 하드마스크 질화막층(210)을 패터닝하여 N형 게이트 전극(240)을 형성한다.Subsequently, after forming a photoresist pattern for forming an N-type gate electrode on the P-type well region 130, the gate oxide layer 140, the polysilicon layer 150, the tungsten silicide (WSix) thin film layer 180, The N-type gate electrode 240 is formed by patterning the amorphous polysilicon thin film layer 190, the tungsten silicide (WSix) layer 200, and the hard mask nitride layer 210.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허 청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

본 발명에 따른 반도체소자의 듀얼 게이트 형성방법은 게이트 형성과정에서 폴리실리콘층과 텅스텐 실리사이드층 사이에 실리콘-리치 텅스텐 실리사이드 박막층과 비정질 폴리실리콘 박막층의 적층구조를 형성하여 후속 열공정으로 인해 폴리실리콘층 내에 주입된 불순물 이온이 텅스텐 실리사이드층으로 확산되어 PMOS의 문턱 전압 변이와 반도체소자의 성능 저하를 가져오는 것을 방지할 수 있다.In the method of forming a dual gate of a semiconductor device according to the present invention, a polysilicon layer is formed by forming a stacked structure of a silicon-rich tungsten silicide thin film layer and an amorphous polysilicon thin film layer between a polysilicon layer and a tungsten silicide layer during a gate formation process. Impurity ions implanted therein can be prevented from diffusing into the tungsten silicide layer, leading to a transition of the threshold voltage of the PMOS and the degradation of the performance of the semiconductor device.

Claims (8)

반도체 기판 상부에 소자분리막과 N형 웰 영역 및 P형 웰 영역을 형성하는 단계;Forming an isolation layer, an N-type well region, and a P-type well region on the semiconductor substrate; 전체 표면 상부에 게이트 산화막층과 폴리실리콘층을 형성하는 단계;Forming a gate oxide layer and a polysilicon layer over the entire surface; 상기 P형 웰 영역 상부에 제 1 감광막패턴을 형성하고, 상기 제 1 감광막패턴을 마스크로 하여 상기 N형 웰 영역의 폴리실리콘층에 P형 불순물을 주입하는 단계;Forming a first photoresist pattern on the P-type well region, and implanting P-type impurities into the polysilicon layer of the N-type well region using the first photoresist pattern as a mask; 상기 N형 웰 영역 상부에 제 2 감광막패턴을 형성하고, 상기 제 2 감광막패턴을 마스크로 하여 상기 P형 웰 영역의 폴리실리콘층에 N형 불순물을 주입하는 단계;Forming a second photoresist pattern on the N-type well region, and implanting N-type impurities into the polysilicon layer of the P-type well region using the second photoresist pattern as a mask; 전체 표면 상부에 텅스텐 실리사이드(WSix) 박막층과 비정질 폴리실리콘 박막층을 형성한 후, 텅스텐 실리사이드(WSix)층을 형성하는 단계; 및Forming a tungsten silicide (WSix) thin film layer and an amorphous polysilicon thin film layer on the entire surface, and then forming a tungsten silicide (WSix) layer; And 상기 적층된 게이트 산화막층, 폴리실리콘층, 텅스텐 실리사이드(WSix) 박막층, 비정질 폴리실리콘 박막층 및 텅스텐 실리사이드(WSix)층을 패터닝하여 상기 N형 웰 영역 및 P형 웰 영역 상부에 각각 듀얼 게이트 전극을 형성하는 단계The stacked gate oxide layer, the polysilicon layer, the tungsten silicide (WSix) thin film layer, the amorphous polysilicon thin film layer, and the tungsten silicide (WSix) layer are patterned to form dual gate electrodes on the N-type well region and the P-type well region, respectively. Steps to 를 포함하는 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.Dual gate forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐 실리사이드(WSix)층을 형성하는 단계를 수행한 후 전체 표면 상 부에 하드마스크 질화막층과 반사방지막층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.And forming a hard mask nitride layer and an anti-reflective layer on the entire surface after performing the step of forming the tungsten silicide (WSix) layer. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘층은 도핑된 폴리실리콘 또는 도핑되지 않은 폴리실리콘으로 형성되는 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.And wherein said polysilicon layer is formed of doped polysilicon or undoped polysilicon. 제 3 항에 있어서,The method of claim 3, wherein 상기 폴리실리콘층이 도핑된 폴리실리콘으로 형성되는 경우, 주입되는 불순물은 N형이고, 상기 불순물의 도핑농도는 1E20 내지 4E20/cm3 인 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.When the polysilicon layer is formed of doped polysilicon, the implanted impurity is N-type, the doping concentration of the impurity is 1E20 to 4E20 / cm 3 characterized in that the dual gate formation method of the semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 P형 불순물은 11B이온 또는 BF2이온이고, 상기 11B이온은 3 내지 5KeV의 이온 에너지로 1E15 내지 5E15/cm2의 도즈량을 갖도록 주입하고, 상기 BF2이온은 10 내지 22KeV의 이온 에너지로 1E15 내지 5E15/cm2의 도즈량을 갖도록 주입하는 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.The P-type impurities are 11 B ions or BF 2 ions, the 11 B ions are implanted to have a dose of 1E15 to 5E15 / cm 2 at an ion energy of 3 to 5 KeV, and the BF 2 ions are 10 to 22 KeV ions. A method of forming a dual gate of a semiconductor device, characterized by injecting energy with a dose of 1E15 to 5E15 / cm 2 . 제 1 항에 있어서,The method of claim 1, 상기 N형 불순물은 31P이온이고, 상기 31P이온은 10 내지 15KeV의 이온 에너지로 1E15 내지 5E15/cm2의 도즈량을 갖도록 주입하는 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.Wherein the N-type impurity is 31 P ions, and the 31 P ions are implanted to have a dose of 1E15 to 5E15 / cm 2 at an ion energy of 10 to 15 KeV. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐 실리사이드(WSix) 박막층은 실리콘 함유량(x)이 0.26 보다 큰 실리콘-리치 텅스텐 실리사이드(WSix)로 형성되고, 상기 텅스텐 실리사이드(WSix) 박막층의 두께는 20 ~ 100 Å인 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.The tungsten silicide (WSix) thin film layer is formed of silicon-rich tungsten silicide (WSix) having a silicon content (x) of greater than 0.26, and the thickness of the tungsten silicide (WSix) thin film layer is 20 to 100 GPa. Dual gate formation method. 제 1 항에 있어서,The method of claim 1, 상기 비정질 폴리실리콘 박막층의 두께는 20 ~ 100 Å인 것을 특징으로 하는 반도체소자의 듀얼 게이트 형성방법.The thickness of the amorphous polysilicon thin film layer is a dual gate forming method of a semiconductor device, characterized in that 20 to 100 kPa.
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