KR100628220B1 - Method for Fabricating Contact of Semiconductor Device - Google Patents

Method for Fabricating Contact of Semiconductor Device Download PDF

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KR100628220B1
KR100628220B1 KR1020040112913A KR20040112913A KR100628220B1 KR 100628220 B1 KR100628220 B1 KR 100628220B1 KR 1020040112913 A KR1020040112913 A KR 1020040112913A KR 20040112913 A KR20040112913 A KR 20040112913A KR 100628220 B1 KR100628220 B1 KR 100628220B1
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insulating film
contact
contact hole
forming
semiconductor device
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KR1020040112913A
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Korean (ko)
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KR20060074241A (en
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김성래
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

본 발명은 반도체 소자의 콘택 제조방법에 관한 것으로, 트랜지스터가 형성된 기판의 표면을 평탄화함과 아울러 기판의 선택된 영역을 배선과 전기적으로 연결시키기 위한 비피에스지나 피에스지와 같은 유동성 재질의 절연막에 보이드가 발생하여 콘택홀을 형성하기 위해 식각할 때, 게이트 산화막과 같은 인접하는 경계막을 손상시키더라도 콘택홀의 측벽에 잔류하는 질화막이 콘택홀에 채워지는 도전물질이 손상된 경계막에 영향을 주는 것을 차단할 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device. When generated and etched to form a contact hole, the nitride film remaining on the sidewall of the contact hole can prevent the conductive material filling the contact hole from affecting the damaged boundary film even if adjacent boundary films such as gate oxides are damaged. do.

보이드, 비피에스지, 피에스지, 콘택홀, 단락불량Void, BPS, PS, contact hole, short circuit

Description

반도체 소자의 콘택 제조방법{Method for Fabricating Contact of Semiconductor Device}Method for fabricating contact of semiconductor device {Method for Fabricating Contact of Semiconductor Device}

도 1은 비피에스지나 피에스지와 같은 유동성 재질의 절연막에 형성된 보이드(Void)를 보인 예시도.1 is an exemplary view showing a void (Void) formed in the insulating film of a fluid material such as BPS or PS.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택구조 제조방법을 순차적으로 보인 예시도.2A to 2C are exemplary views sequentially showing a method of manufacturing a contact structure of a semiconductor device according to the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

21:기판 22:게이트 산화막21: substrate 22: gate oxide film

23:제1절연막 24:콘택홀23: first insulating film 24: contact hole

25:제2절연막 26:배리어 금속25: second insulating film 26: barrier metal

27:텅스텐 28:배선27: tungsten 28: wiring

본 발명은 반도체 소자의 콘택 제조방법에 관한 것으로, 보다 상세하게는 다층 금속배선들과 기판의 선택된 영역들을 전기적으로 연결시키는 콘택(Contact)불량에 의한 반도체 소자의 오동작을 방지하기에 적당하도록 한 반도체 소자의 콘택 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device, and more particularly, to a semiconductor suitable for preventing malfunction of a semiconductor device due to a contact defect that electrically connects multilayered metal wires and selected regions of a substrate. It relates to a method for manufacturing a contact of a device.

일반적으로, 반도체 소자는 복수의 트랜지스터들이 형성된 기판 상에 절연막을 형성한 다음 트랜지스터의 게이트나 소스/드레인 등이 선택적으로 노출되도록 식각하고, 도전물질을 채워 넣어 콘택을 형성한 다음 콘택과 연결되는 배선을 패터닝하여 전기적으로 구동되도록 설계된다.In general, a semiconductor device forms an insulating film on a substrate on which a plurality of transistors are formed, and then etches a gate or a source / drain of the transistor to be selectively exposed, forms a contact by filling a conductive material, and then connects the wiring to the contact. It is designed to be electrically driven by patterning it.

상기 절연막은 기판 표면의 평탄화를 위해 비피에스지(BPSG)나 피에스지(PSG)와 같은 유동성을 갖는 재질로 형성되는데, 최근 반도체 소자의 고집적화로 인해 트랜지스터들의 사이즈와 트랜지스터들이 이격되는 간격이 미세해짐에 따라 게이트 사이에 채워지는 비피에스지나 피에스지와 같은 절연막에 보이드(Void)가 발생되어 후속 콘택 형성시 반도체 소자의 불량을 발생시키는 요인이 되고 있다.The insulating layer is formed of a material having fluidity such as BPSG or PSG to planarize the surface of the substrate. Recently, due to the high integration of semiconductor devices, the size of the transistors and the intervals between the transistors become smaller. As a result, voids are generated in an insulating film such as a non-PSI or a PSI filled between the gates, thereby causing a defect of the semiconductor device during subsequent contact formation.

도 1은 비피에스지나 피에스지와 같은 유동성 재질의 절연막에 형성된 보이드(Void)를 보인 예시도로서, 이를 참조하여 종래 반도체 소자의 콘택 및 그 제조방법을 설명하면 다음과 같다.FIG. 1 is an exemplary view showing a void formed in an insulating film of a fluid material such as BPS or PSG. Referring to this, a contact of a conventional semiconductor device and a method of manufacturing the same will be described below.

먼저, 기판(11) 상에 복수의 게이트(12)와 소스/드레인(미도시)으로 구성되는 복수의 트랜지스터들을 동시에 형성한다.First, a plurality of transistors including a plurality of gates 12 and a source / drain (not shown) are simultaneously formed on the substrate 11.

그리고, 상기 복수의 트랜지스터들이 형성된 기판(11)의 상부전면에 제1절연막(13)을 형성한 다음 배선과 연결될 영역이 노출되도록 선택적으로 식각한다.The first insulating layer 13 is formed on the upper surface of the substrate 11 on which the plurality of transistors are formed, and then selectively etched to expose a region to be connected to the wiring.

그리고, 상기 제1절연막(13)이 선택적으로 식각된 기판(11)의 상부전면에 비피에스지나 피에스지와 같은 유동성 재질의 제2절연막(14)을 형성하여 표면을 평탄화시킨다. 이때, 반도체 소자의 고집적화로 인해 트랜지스터들의 사이즈와 트랜지 스터들이 이격되는 간격이 미세해짐에 따라 게이트(12) 사이에 채워지는 제2절연막(14)에 보이드(15)가 발생된다.In addition, the surface of the upper surface of the substrate 11 on which the first insulating layer 13 is selectively etched is formed to form a second insulating layer 14 made of a fluid material such as non-PS or PS. At this time, due to the high integration of the semiconductor device, the voids 15 are generated in the second insulating layer 14 that is filled between the gates 12 as the size of the transistors and the gaps between the transistors become smaller.

이후, 도 1에 도시되지는 않았지만, 상기 제2절연막(14)의 보이드(15)가 발생된 영역을 식각하여 배선과 연결될 영역이 노출되는 콘택홀(Contact Hole)을 형성하고, 배리어 금속(Barrier Metal)과 텅스텐을 증착하여 콘택홀을 채움으로써, 콘택을 형성한 다음 도전물질을 패터닝하여 콘택과 전기적으로 연결되는 배선을 형성한다.Subsequently, although not shown in FIG. 1, a region in which the void 15 of the second insulating layer 14 is generated is etched to form a contact hole that exposes a region to be connected to the wiring, and a barrier metal (Barrier). Metal) and tungsten are deposited to fill the contact hole, thereby forming a contact and then patterning a conductive material to form a wire electrically connected to the contact.

그러나, 상기한 바와 같은 종래 반도체 소자의 콘택 및 그 제조방법은 제2절연막(14)에 발생된 보이드(15)로 인해 콘택홀을 형성하기 위한 제2절연막(14)의 식각시 게이트 산화막과 같은 인접하는 경계막을 손상시키게 되고, 따라서 콘택을 형성하기 위해 배리어 금속과 텅스텐을 증착하는 경우에 트랜지스터의 단락불량(Short Fail) 등을 유발하여 반도체 소자가 오동작하게 되는 문제점이 있었다.However, the contact and manufacturing method of the conventional semiconductor device as described above, such as the gate oxide film during etching of the second insulating film 14 for forming the contact hole due to the void 15 generated in the second insulating film 14. There is a problem that the adjacent boundary layer is damaged, and thus, when the barrier metal and tungsten are deposited to form a contact, a short failure of the transistor or the like causes a malfunction of the semiconductor device.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위해 창안한 것으로, 본 발명의 목적은 다층 금속배선들과 기판의 선택된 영역들을 전기적으로 연결시키는 콘택 불량에 의한 반도체 소자의 오동작을 방지할 수 있는 반도체 소자의 콘택 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to prevent malfunction of a semiconductor device due to a poor contact that electrically connects multilayered metal wires and selected regions of a substrate. The present invention provides a contact manufacturing method for a semiconductor device.

삭제delete

그리고, 상기 본 발명의 목적을 달성하기 위한 반도체 소자의 콘택 제조방법은 기판 상에 복수의 트랜지스터들을 형성하는 공정과; 상기 기판 상에 제1절연막을 형성한 다음 상기 복수의 트랜지스터들이 형성된 기판의 일부가 노출되도록 제1절연막의 일부를 식각하여 콘택홀을 형성하는 공정과; 상기 제1절연막의 상부전면에 제2절연막을 형성한 다음 제2절연막이 콘택홀의 측벽에만 잔류하도록 선택적으로 식각하는 공정과; 상기 제1절연막의 상부전면에 적어도 하나의 도전막을 형성한 다음 제1절연막이 노출될때까지 평탄화하여 상기 콘택홀이 채워진 콘택을 형성하는 공정과; 상기 제1절연막의 상부전면에 도전물질을 형성한 다음 패터닝하여 상기 콘택과 전기적으로 연결되는 배선을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.In addition, the contact manufacturing method of the semiconductor device for achieving the object of the present invention comprises the steps of forming a plurality of transistors on a substrate; Forming a contact hole by forming a first insulating layer on the substrate and then etching a portion of the first insulating layer to expose a portion of the substrate on which the plurality of transistors are formed; Forming a second insulating film on an upper surface of the first insulating film and then selectively etching the second insulating film so that the second insulating film remains only on the sidewalls of the contact holes; Forming at least one conductive film on an upper surface of the first insulating film, and then planarizing the first insulating film to form a contact filled with the contact hole; And forming a conductive material on the upper surface of the first insulating layer and then patterning the conductive material to form a wire electrically connected to the contact.

상기한 바와같은 본 발명에 의한 반도체 소자의 콘택 제조방법을 첨부한 도면을 참조하여 보다 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a semiconductor device according to the present invention as described above in more detail as follows.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택 제조방법을 순차적으로 보인 예시도이다.2A to 2C are exemplary views sequentially illustrating a method for manufacturing a contact of a semiconductor device according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 기판(21) 상에 복수의 게이트(미도시)와 소스/드레인(미도시)으로 구성되는 복수의 트랜지스터들을 동시에 형성한 다음 상부전면에 비피에스지나 피에스지와 같은 유동성 재질의 제1절연막(23)을 형성하여 표면을 평탄화시킨 다음 후술할 배선(28)과 연결될 영역이 노출되도록 콘택홀(24)을 형성한다. 이때, 트랜지스터의 게이트는 기판(21) 상에 게이트산화막(22), 게이트 전극 및 보호층이 패터닝되는 다층구조로 형성되지만, 도 2a 내지 도 2c에서는 본 발명의 핵심내용에 대한 설명을 집중시키기 위해 게이트산화막(22) 만을 도시하였다.First, as illustrated in FIG. 2A, a plurality of transistors including a plurality of gates (not shown) and a source / drain (not shown) are simultaneously formed on the substrate 21, and then the BPS or PS paper is formed on the upper surface of the substrate 21. The first insulating layer 23 is formed of a fluid material to form a flat surface, and then the contact hole 24 is formed to expose a region to be connected to the wiring 28 to be described later. At this time, the gate of the transistor is formed in a multi-layered structure in which the gate oxide film 22, the gate electrode and the protective layer is patterned on the substrate 21, but in Figures 2a to 2c to focus the description of the core of the present invention Only the gate oxide film 22 is shown.

그리고, 도 2b에 도시된 바와같이 ,상기 결과물의 상부전면에 제2절연막(25)을 형성한 다음 제2절연막(25)이 콘택홀(24)의 측벽에만 잔류하도록 식각한다. 이때, 제2절연막(25)으로는 질화막을 20~50Å 정도의 두께로 형성하고, 제2절연막(25)의 식각은 F 계열의 가스를 사용한 건식으로 실시함으로써, 제1절연막(23)의 상부 및 콘택홀(24)의 바닥에 형성된 제2절연막(25)을 선택적으로 제거한다.As shown in FIG. 2B, the second insulating layer 25 is formed on the upper surface of the resultant, and then the second insulating layer 25 is etched so as to remain only on the sidewall of the contact hole 24. In this case, the nitride film is formed to have a thickness of about 20 to 50 GPa as the second insulating film 25, and the etching of the second insulating film 25 is performed by dry using an F-based gas, thereby forming an upper portion of the first insulating film 23. And selectively remove the second insulating layer 25 formed on the bottom of the contact hole 24.

그리고, 도 2c에 도시된 바와같이, 상기 결과물의 상부전면에 배리어 금속(26)과 텅스텐(27)을 증착하고, 제1절연막(23)이 노출될때까지 평탄화하여 상기 콘택홀(24)의 내부에 배리어 금속(26)과 텅스텐(27)을 채워 넣어 콘택을 형성한다. As shown in FIG. 2C, a barrier metal 26 and tungsten 27 are deposited on the upper surface of the resultant, and planarized until the first insulating layer 23 is exposed, and then the inside of the contact hole 24. The barrier metal 26 and tungsten 27 are filled in to form a contact.

계속해서, 상기 제1절연막(23)의 상부전면에 도전물질을 형성한 다음 패터닝하여 상기 콘택과 전기적으로 연결되는 배선(28)을 형성한다. 이때, 배선(28)의 도전물질로는 저항값이 낮은 알루미늄 재질이 적용될 수 있다.Subsequently, a conductive material is formed on the upper surface of the first insulating layer 23 and then patterned to form a wiring 28 electrically connected to the contact. In this case, an aluminum material having a low resistance value may be used as the conductive material of the wiring 28.

상기한 바와 같은 본 발명에 의한 반도체 소자의 콘택 및 그 제조방법은 제1절연막(23)에 보이드가 발생하더라도 제1절연막(23)을 식각하여 콘택홀(24)을 형성 하고, 그 콘택홀(24)에 배리어 금속(26)과 텅스텐(27)을 채워 넣어 콘택을 형성하는 경우에 콘택홀(24)의 측벽에 제2절연막(25)이 잔류하기 때문에 트랜지스터의 단락불량이 발생되는 것을 방지할 수 있게 된다.As described above, according to the present invention, a contact of a semiconductor device and a method of manufacturing the same according to the present invention may form a contact hole 24 by etching the first insulating layer 23 even when a void occurs in the first insulating layer 23. In the case where the barrier metal 26 and the tungsten 27 are filled with the 24 to form the contact, the second insulating layer 25 remains on the sidewall of the contact hole 24, thereby preventing short-circuit failure of the transistor. It becomes possible.

상술한 바와같이 본 발명에 의한 반도체 소자의 콘택 및 그 제조방법은 트랜지스터가 형성된 기판의 표면을 평탄화함과 아울러 기판의 선택된 영역을 배선과 전기적으로 연결시키기 위한 비피에스지나 피에스지와 같은 유동성 재질의 절연막에 보이드가 발생하여 콘택홀을 형성하기 위해 식각할 때, 게이트 산화막과 같은 인접하는 경계막을 손상시키더라도 콘택홀의 측벽에 잔류하는 질화막이 콘택홀에 채워지는 도전물질이 손상된 경계막에 영향을 주는 것을 차단할 수 있게 된다.As described above, the contact of the semiconductor device and the method of manufacturing the same according to the present invention are made of a fluid material such as non-PS or PS for planarizing the surface of the substrate on which the transistor is formed and electrically connecting the selected region of the substrate to the wiring. When voids are generated in the insulating film to be etched to form the contact holes, the nitride film remaining on the sidewall of the contact hole affects the damaged boundary film in which the conductive material filled in the contact hole is damaged even if adjacent boundary films such as gate oxides are damaged. Can be blocked.

따라서, 콘택 불량에 기인하는 트랜지스터의 단락불량 등을 방지하여 반도체소자의 오동작을 방지할 수 있는 효과가 있다.Therefore, there is an effect that a malfunction of the semiconductor device can be prevented by preventing a short circuit defect of the transistor due to a poor contact.

Claims (6)

삭제delete 삭제delete 삭제delete 삭제delete 기판 상에 복수의 트랜지스터들을 형성하는 공정과, Forming a plurality of transistors on the substrate, 상기 기판 상에 유동성 재질의 제1절연막을 형성하는 공정과,Forming a first insulating film of a flowable material on the substrate; 상기 복수의 트랜지스터들이 형성된 기판의 일부가 노출되도록 제1절연막의 일부를 식각하여 콘택홀을 형성하는 공정과; Forming a contact hole by etching a portion of the first insulating layer to expose a portion of the substrate on which the plurality of transistors are formed; 상기 콘택홀을 포함한 상기 제1절연막의 상부 전면에 제2절연막을 형성하는 공정과,Forming a second insulating film on the entire upper surface of the first insulating film including the contact hole; 상기 제2절연막의 콘택홀의 측벽에만 잔류하도록 상기 제1절연막의 상부 및 콘택홀의 바닥에 형성된 제2절연막을 F 계열의 가스를 사용한 건식식각으로 선택적으로 식각하는 공정과, Selectively etching the second insulating film formed on the top of the first insulating film and the bottom of the contact hole by dry etching using an F-based gas so as to remain only in the sidewalls of the contact holes of the second insulating film; 상기 제1절연막의 상부전면에 적어도 하나의 도전막을 형성한 다음 제1절연막이 노출될 때까지 평탄화하여 상기 콘택홀이 채워진 콘택을 형성하는 공정과, Forming at least one conductive film on an upper surface of the first insulating film and then planarizing the first insulating film until the first insulating film is exposed to form a contact filled with the contact hole; 상기 제1절연막의 상부전면에 도전물질을 형성한 다음 패터닝하여 상기 콘택과 전기적으로 연결되는 배선을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 제조방법.And forming a conductive material on the upper surface of the first insulating layer and then patterning the conductive material to form wirings electrically connected to the contacts. 제 5 항에 있어서, The method of claim 5, 상기 제1절연막의 상부전면에 제2절연막을 형성한 다음 제2절연막이 콘택홀의 측벽에만 잔류하도록 선택적으로 식각하는 공정은 After forming a second insulating film on the upper surface of the first insulating film and selectively etching so that the second insulating film remains only on the sidewall of the contact hole 상기 제2절연막으로는 질화막을 20~50Å 정도의 두께로 형성한 다음 F 계열의 가스를 사용한 건식으로 식각하는 것을 특징으로 하는 반도체 소자의 콘택 제조방법.The second insulating layer is formed of a nitride film having a thickness of about 20 ~ 50 GPa, and then etched by dry using a F-based gas.
KR1020040112913A 2004-12-27 2004-12-27 Method for Fabricating Contact of Semiconductor Device KR100628220B1 (en)

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