KR100623328B1 - 반도체 소자의 cmos 트랜지스터 제조 방법 - Google Patents
반도체 소자의 cmos 트랜지스터 제조 방법 Download PDFInfo
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- KR100623328B1 KR100623328B1 KR1020020038980A KR20020038980A KR100623328B1 KR 100623328 B1 KR100623328 B1 KR 100623328B1 KR 1020020038980 A KR1020020038980 A KR 1020020038980A KR 20020038980 A KR20020038980 A KR 20020038980A KR 100623328 B1 KR100623328 B1 KR 100623328B1
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- Prior art keywords
- gate
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- gate oxide
- forming
- cmos transistor
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 40
- 239000007943 implant Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 abstract description 5
- 239000011800 void material Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 3
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- 238000009826 distribution Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical class CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
- H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (2)
- 반도체 기판 상에 소자 분리막을 형성한 후 N웰 및 P웰을 형성하기 위한 임플란트 공정을 진행하는 단계와,상기 임플란트 공정을 진행한 결과물 상에 게이트 산화막과 게이트 전극 및 식각방지막을 차례로 형성하는 단계와,상기 게이트 전극 및 식각 방지막을 패터닝한 후 게이트 산화막과 식각비가 높은 절연막을 증착하는 단계와,상기 절연막을 건식각을 하여 사이드월 스페이서를 형성하고 임플란트 공정을 통해 소오스/드레인을 형성하는 단계와,상기 사이드월 스페이서와 게이트의 식각 방지막을 식각 장벽층으로 이용하여 상기 사이드월 스페이서의 하부 및 게이트 전극 하부의 에지 근방에 있는 상기 게이트 산화막의 일부를 습식각을 통해 제거하는 단계와,상기 게이트 산화막이 제거된 결과물 상에 층간 절연막을 증착하는 단계를포함하는 것을 특징으로 하는 반도체 소자의 CMOS 트랜지스터 제조 방법.
- 제 1항에 있어서, 상기 게이트 에지 부분의 산화막 식각 공정후 라이트 옥시데이션 공정을 진행하는 것을 특징으로 하는 반도체 소자의 CMOS 트랜지스터 제조 방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020038980A KR100623328B1 (ko) | 2002-07-05 | 2002-07-05 | 반도체 소자의 cmos 트랜지스터 제조 방법 |
US10/331,529 US6740572B2 (en) | 2002-07-05 | 2002-12-30 | Method for fabricating CMOS transistor of a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020038980A KR100623328B1 (ko) | 2002-07-05 | 2002-07-05 | 반도체 소자의 cmos 트랜지스터 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040003950A KR20040003950A (ko) | 2004-01-13 |
KR100623328B1 true KR100623328B1 (ko) | 2006-09-11 |
Family
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Application Number | Title | Priority Date | Filing Date |
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KR1020020038980A KR100623328B1 (ko) | 2002-07-05 | 2002-07-05 | 반도체 소자의 cmos 트랜지스터 제조 방법 |
Country Status (2)
Country | Link |
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US (1) | US6740572B2 (ko) |
KR (1) | KR100623328B1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI487070B (zh) * | 2010-07-05 | 2015-06-01 | United Microelectronics Corp | 互補式金氧半導體元件的製造方法 |
WO2014013959A1 (en) * | 2012-07-20 | 2014-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0786589A (ja) * | 1993-09-14 | 1995-03-31 | Sony Corp | 積み上げ拡散層型mos半導体装置の製造方法 |
KR19990034155A (ko) * | 1997-10-28 | 1999-05-15 | 구본준 | 반도체 소자 및 제조 방법 |
KR19990073841A (ko) * | 1998-03-04 | 1999-10-05 | 김영환 | 트랜지스터의 형성 방법 |
KR20010064034A (ko) * | 1999-12-24 | 2001-07-09 | 윤종용 | 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조방법 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127251A (en) * | 1998-09-08 | 2000-10-03 | Advanced Micro Devices, Inc. | Semiconductor device with a reduced width gate dielectric and method of making same |
-
2002
- 2002-07-05 KR KR1020020038980A patent/KR100623328B1/ko active IP Right Grant
- 2002-12-30 US US10/331,529 patent/US6740572B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0786589A (ja) * | 1993-09-14 | 1995-03-31 | Sony Corp | 積み上げ拡散層型mos半導体装置の製造方法 |
KR19990034155A (ko) * | 1997-10-28 | 1999-05-15 | 구본준 | 반도체 소자 및 제조 방법 |
KR19990073841A (ko) * | 1998-03-04 | 1999-10-05 | 김영환 | 트랜지스터의 형성 방법 |
KR20010064034A (ko) * | 1999-12-24 | 2001-07-09 | 윤종용 | 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20040003950A (ko) | 2004-01-13 |
US6740572B2 (en) | 2004-05-25 |
US20040005751A1 (en) | 2004-01-08 |
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