KR100607782B1 - Method for manufacturing metal silicide layer of the semiconductor device - Google Patents
Method for manufacturing metal silicide layer of the semiconductor device Download PDFInfo
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- KR100607782B1 KR100607782B1 KR1020030060872A KR20030060872A KR100607782B1 KR 100607782 B1 KR100607782 B1 KR 100607782B1 KR 1020030060872 A KR1020030060872 A KR 1020030060872A KR 20030060872 A KR20030060872 A KR 20030060872A KR 100607782 B1 KR100607782 B1 KR 100607782B1
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- metal silicide
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- silicide film
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 47
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 40
- 239000002184 metal Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000010936 titanium Substances 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910017840 NH 3 Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 229910052743 krypton Inorganic materials 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 description 10
- 239000010941 cobalt Substances 0.000 description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 10
- 229910021341 titanium silicide Inorganic materials 0.000 description 7
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
Abstract
본 발명은 반도체 소자의 금속 실리사이드막(silicide layer) 제조 방법에 관한 것으로, 반도체 기판의 실리콘층 상부에 티타늄층과 티타늄 나이트라이드층을 순차 증착하고, 티타늄층 및 티타늄 나이트라이드층이 형성된 기판 전면에 N2 비활성 분위기에서 제1온도범위로 1차 열처리 공정을 실시하여 중간상 결정의 금속 실리사이드막을 형성하며, 중간상 결정의 금속 실리사이드막에 제1온도범위 이상인 제2온도범위로 2차 열처리 공정을 실시하여 설정된 결정의 금속 실리사이드막을 형성하고, 결과물에 세정 공정을 실시하여 실리사이드화에 미반응된 금속층을 제거하는 과정으로 이루어진다. 본 발명에 의하면, MOSFET가 형성된 기판에 실리사이드 금속을 증착하고 1차 열처리 공정을 진행한 후에 세정 공정을 생략한 채 2차 열처리 공정을 진행함으로써 실리사이드 제조 공정을 단순화할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal silicide layer of a semiconductor device, and sequentially deposits a titanium layer and a titanium nitride layer on an upper surface of a silicon layer of a semiconductor substrate, and deposits a titanium layer and a titanium nitride layer on the entire surface of the substrate. A first heat treatment process is performed in a first temperature range in an N 2 inert atmosphere to form a metal silicide film of an intermediate phase crystal, and a second heat treatment process is performed on a metal silicide film of an intermediate phase crystal in a second temperature range that is greater than or equal to the first temperature range. A metal silicide film of a set crystal is formed, and the resultant is subjected to a cleaning process to remove a metal layer unreacted for silicidation. According to the present invention, the silicide manufacturing process can be simplified by depositing a silicide metal on the substrate on which the MOSFET is formed and proceeding the first heat treatment step and then performing the second heat treatment step without the cleaning process.
실리사이드, RTPSilicide, RTP
Description
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 금속 실리사이드막 제조 방법을 설명하기 위한 공정 순서도.1 to 4 are process flowcharts for explaining a method for producing a metal silicide film of a semiconductor device according to the present invention.
본 발명은 반도체 소자 제조 기술에 관한 것으로, 특히 열공정을 단순화하여 균일한 결정상을 갖는 반도체 소자의 금속 실리사이드막을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method of manufacturing a metal silicide film of a semiconductor device having a uniform crystal phase by simplifying a thermal process.
반도체소자의 집적화가 높아짐에 따라 NMOS, PMOS 등의 트랜지스터의 소오스/드레인 영역과 게이트전극의 폭이 감소되고 있다. 이로 인해 소오스/드레인 영역과 게이트전극의 표면 저항(sheet resistance)이 높아져서 반도체소자의 동작이 저하되는 문제점이 있었다. 이에 따라, 반도체 제조 공정시 게이트전극 및 불순물이 주입된 영역에 저 저항 물질의 금속 실리사이드막을 형성하여 표면 저항을 낮추었다. As the integration of semiconductor devices increases, the widths of the source / drain regions and gate electrodes of transistors such as NMOS and PMOS are reduced. As a result, the sheet resistance of the source / drain regions and the gate electrode is increased, thereby degrading the operation of the semiconductor device. As a result, a metal silicide layer of a low resistance material is formed in the region where the gate electrode and the impurity is implanted in the semiconductor manufacturing process to lower the surface resistance.
그런데, 티타늄 실리사이드(TiSi)의 경우 후속으로 진행되는 열처리 공정에 의해 실리사이드의 응집 현상이 발생하여 저항의 증가 및 누설 전류가 발생할 수 있는 문제점이 있다. 이에 최근에는 열적 안정성이 우수한 코발트 실리사이드(CoSi2)도 많이 사용되고 있다.However, in the case of titanium silicide (TiSi), the agglomeration phenomenon of the silicide occurs by a subsequent heat treatment process, which may cause an increase in resistance and a leakage current. Recently, cobalt silicide (CoSi 2 ) having excellent thermal stability is also widely used.
종래 기술에 의한 반도체 소자의 금속 실리사이드막 제조 방법은 다음과 같다. 우선, 반도체 기판으로서 실리콘 기판에 소자의 활성 영역과 비활성 영역을 구분하는 소자 분리막을 형성한다. 그리고 반도체 기판의 활성 영역 상부에 반도체 소자로서 MOSFET 제조 공정을 진행하여 게이트 절연막, 게이트 전극 및 스페이서를 순차적으로 형성하고, 반도체 기판의 활성 영역내에 불순물이 주입된 소오스/드레인 영역을 형성한다.The metal silicide film manufacturing method of the semiconductor element by a prior art is as follows. First, an element isolation film is formed on a silicon substrate as a semiconductor substrate to distinguish between active and inactive regions of the device. Then, a MOSFET manufacturing process is performed as a semiconductor device on the active region of the semiconductor substrate to sequentially form a gate insulating film, a gate electrode, and a spacer, and form a source / drain region in which impurities are injected into the active region of the semiconductor substrate.
그 다음 게이트 전극 및 소오스/드레인 영역에 티타늄 실리사이드(TiSi2) 또는 저저항의 코발트 실리사이드(CoSi2) 제조 공정을 진행한다. 반도체 기판 전면에 티타늄(Ti) 또는 코발트(Co)를 함유한 금속층을 증착한다. 그리고 금속층이 증착된 결과물 전체에 낮은 온도에서 1차 열처리 공정을 실시하여 게이트 전극 및 소오스/드레인 영역 상부에 티타늄 실리사이드(TiSi) 또는 코발트 실리사이드(CoSi)를 형성한 후에, 세정 공정을 실시하여 실리사이드 반응이 되지 않은 금속층을 제거한다. 그리고 나서 1차보다 높은 온도에서 2차 열처리 공정을 진행하여 TiSi의 C49 상을 안정된 C54상으로 상변이시키거나 CoSi를 CoSi2로 변형시킨다. 이로 인해 MOSFET의 게이트 전극 및 소오스/드레인 영역 표면에 최종의 티타늄실리사이드(TiSi2) 또는 코발트 실리사이드(CoSi2)가 형성된다.Next, titanium silicide (TiSi 2 ) or low-resistance cobalt silicide (CoSi 2 ) manufacturing process is performed on the gate electrode and the source / drain regions. A metal layer containing titanium (Ti) or cobalt (Co) is deposited on the entire surface of the semiconductor substrate. In addition, a first heat treatment process is performed at a low temperature on the entire result of the deposition of the metal layer to form titanium silicide (TiSi) or cobalt silicide (CoSi) on the gate electrode and the source / drain regions, followed by a silicide reaction. Remove the metal layer that is not there. Then, a second heat treatment process is performed at a temperature higher than the first to phase shift the C49 phase of TiSi to a stable C54 phase or to transform CoSi into CoSi 2 . This results in the formation of final titanium silicide (TiSi 2 ) or cobalt silicide (CoSi 2 ) on the gate electrode and source / drain regions of the MOSFET.
그런데, 이러한 종래 기술의 금속 실리사이드 제조 공정시 1차 및 2차의 열처리 공정시 중간에 세정 공정을 실시하기 때문에 전체 제조 공정이 증가되는 문제점이 있었다.However, since the cleaning process is performed in the middle of the first and second heat treatment processes in the prior art metal silicide manufacturing process, there is a problem in that the entire manufacturing process is increased.
본 발명은 상술한 종래 기술의 문제점을 해결하기 위한 것으로, 실리사이드용 금속을 증착한 후에 비활성 가스 분위기에서 1차 열처리 공정을 진행한 후에 세정 공정을 생략한 채 2차 열처리 공정을 진행함으로써 전체 실리사이드 제조 공정을 단순화할 수 있는 반도체 소자의 금속 실리사이드막 제조 방법을 제공하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems of the prior art, and after the deposition of the metal for silicide, the first heat treatment process in an inert gas atmosphere, and then proceed with the second heat treatment process without the cleaning process to produce the entire silicide It is an object of the present invention to provide a method for producing a metal silicide film of a semiconductor device which can simplify the process.
이러한 목적을 달성하기 위하여 본 발명은, 금속 실리사이드막을 갖는 반도체소자의 제조 방법으로서, 반도체 기판의 실리콘층 상부에 티타늄층과 티타늄 나이트라이드층을 순차 증착하는 단계와, 상기 티타늄층 및 티타늄 나이트라이드층이 형성된 기판 전면에 N2 비활성 분위기에서 제1온도범위로 1차 열처리 공정을 실시하여 중간상 결정의 금속 실리사이드막을 형성하는 단계와, 상기 중간상 결정의 금속 실리사이드막에 상기 제1온도범위 이상인 제2온도범위로 2차 열처리 공정을 실시하여 설정된 결정의 금속 실리사이드막을 형성하는 단계와, 상기 결과물에 세정 공정을 실시하여 실리사이드화에 미반응된 금속층을 제거하는 단계를 포함하는 반도체 소자의 금속 실리사이드막 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device having a metal silicide film, the step of sequentially depositing a titanium layer and a titanium nitride layer on the silicon layer of the semiconductor substrate, and the titanium layer and titanium nitride layer Forming a metal silicide film of an intermediate phase crystal by performing a first heat treatment process in a first temperature range in an N 2 inert atmosphere on the entire surface of the substrate; and a second temperature of more than the first temperature range of the metal silicide film of the intermediate phase crystal. Forming a metal silicide film of a set crystal by performing a secondary heat treatment process to a range; and performing a cleaning process on the resultant to remove a metal layer unreacted for silicide formation. To provide.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 금속 실리사이드막 제조 방법을 설명하기 위한 공정 순서도로서, 이들 도면을 참조하면 본 발명의 금속 실리사이드막 제조 공정은 다음과 같다.1 to 4 are process flowcharts for explaining a method for manufacturing a metal silicide film of a semiconductor device according to the present invention. Referring to these drawings, the metal silicide film manufacturing process of the present invention is as follows.
도 1에 도시된 바와 같이, 반도체 기판(10)으로서 실리콘 기판에 소자의 활성 영역(active region)과 비활성 영역(nonactive region)을 구분하는 소자 분리막(미도시함)을 형성하고, 반도체 기판(10)의 활성 영역 상부에 게이트 절연막(12), 게이트 전극(14)을 순차적으로 적층하고 그 측벽에 스페이서 절연막(16)을 형성한다. 그리고 도면에 미도시되어 있지만, 반도체 기판(10)의 활성 영역내에 게이트 전극(14) 하부를 사이에 두고 서로 이격된 소오스 및 드레인 영역(18)을 형성하여 MOSFET 소자를 제조한다.As shown in FIG. 1, an isolation layer (not shown) for forming an active region and a nonactive region of an element is formed on a silicon substrate as a
그런 다음, 본 발명에 따라 상기 MOSFET 소자에 금속 실리사이드막 제조 공정을 진행한다.Then, a metal silicide film manufacturing process is performed on the MOSFET device according to the present invention.
우선 도 2에 도시된 바와 같이, 기판 전면에 적어도 1층 이상의 금속층(20, 22)을 증착한다. 예를 들어, 하부의 금속층(20)은 실리콘과 실리사이드 반응을 일으키기 위한 코발트층(Co) 또는 티타늄(Ti)으로 이루어지며 상부 금속층(22)은 이후 열처리 공정시 반응된 실리사이드막으로 산소의 공급을 블록킹하는 역할을 하기 위하여 티타늄(Ti) 또는 티타늄 나이트라이드(TiN)로 형성한다.First, as shown in FIG. 2, at least one or
이렇게 금속층(20, 22)이 형성된 기판이 있는 반응 챔버에 N2 비활성 기체를 공급한 분위기에서 제 1 온도로 1차 열처리 공정을 실시한다. 여기서 1차 열처리 공정의 제 1 온도는 코발트(Co)의 경우 200℃∼700℃, 티타늄(Ti)의 경우 300℃∼750℃ 온도 조건을 갖는다. 그리고 1차 열처리 공정은 급속 열처리 공정(rapid thermal process : RTP) 또는 퍼니스에서 열처리 공정이 진행된다.In this manner, a first heat treatment process is performed at a first temperature in an atmosphere in which an N 2 inert gas is supplied to a reaction chamber having a substrate on which the
이에 따라 게이트 전극(14) 및 소오스/드레인 영역(18) 상부에 중간상 결정 크기를 갖는 티타늄 실리사이드(TiSi) 또는 코발트 실리사이드(CoSi)(24)가 형성된다. 이때, 1차 열처리 공정이 진행되는 반응 챔버에 N2 가스와 함께 NH3, He, Ar, Kr, Xe, 또는 Rn 비활성 가스가 공급되도록 한다.As a result, titanium silicide (TiSi) or cobalt silicide (CoSi) 24 having a mesophase crystal size is formed on the
그런 다음 도 3에 도시된 바와 같이, 세정 공정을 진행하지 않고 중간상 결정의 실리사이드막(24)에 제 1온도보다 높은 제 2온도에서 2차 열처리 공정을 진행하여 TiSi의 C49 상을 안정된 C54상으로 상변이시키거나 CoSi를 CoSi2로 변형시킨다. 여기서 2차 열처리 공정의 제 2 온도는 코발트(Co)의 경우 600℃∼1000℃, 티타늄(Ti)의 경우 700℃∼1000℃ 온도 조건을 갖는다. 그리고 2차 열처리 공정은 급속 열처리 공정(rapid thermal process) 또는 퍼니스에서 열처리 공정이 진행된다.Then, as shown in FIG. 3, a secondary heat treatment process was performed on the
이로 인해 MOSFET의 게이트 전극(16) 및 소오스/드레인 영역(18) 표면에 안정된 결정 크기를 갖는 티타늄실리사이드(TiSi2) 또는 코발트 실리사이드(CoSi2)(24a)가 형성된다.This forms titanium silicide (TiSi 2 ) or cobalt silicide (CoSi 2 ) 24a having a stable crystal size on the surface of the
이때 2차 열처리 공정은 1차 열처리 공정이 진행된 동일한 반응 챔버에서 인 시튜(in-situ)로 진행되거나 별도의 반응 챔버에서 진행되도록 하고 1차 열처리 공정과 마찬가지로 N2 비활성 가스 분위기에서 열처리 공정을 진행한다. 또한 2차 열처리 공정이 진행되는 반응 챔버에도 N2 가스와 함께 NH3, He, Ar, Kr, Xe, 또는 Rn 비활성 가스가 공급되도록 한다.In this case, the secondary heat treatment process may be performed in-situ in the same reaction chamber in which the first heat treatment process is performed or in a separate reaction chamber, and the heat treatment process may be performed in an N 2 inert gas atmosphere as in the first heat treatment process. do. In addition, NH 3 , He, Ar, Kr, Xe, or Rn inert gas is supplied to the reaction chamber along with the secondary heat treatment process along with the N 2 gas.
그런 다음 도 4에 도시된 바와 같이, 2차 열처리 공정이 진행된 기판에 세정 공정을 실시하여 실리사이드화에 미반응된 금속층을 제거하여 본 발명에 따른 실리사이드막(24a)이 있는 MOSFET 소자가 완성된다.Then, as illustrated in FIG. 4, the substrate having undergone the secondary heat treatment process is subjected to a cleaning process to remove the unreacted metal layer from silicide, thereby completing the MOSFET device having the
이상 상술한 바와 같이, 본 발명은 MOSFET가 형성된 기판에 실리사이드 금속을 증착하고 1차 열처리 공정을 진행한 후에 세정 공정을 생략한 채 2차 열처리 공정을 진행함으로써 실리사이드 제조 공정을 단순화할 수 있는 효과가 있다.As described above, the present invention has the effect of simplifying the silicide manufacturing process by depositing the silicide metal on the substrate on which the MOSFET is formed and proceeding the secondary heat treatment step without the cleaning process after performing the first heat treatment step. have.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능함은 물론이다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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