KR100583120B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR100583120B1 KR100583120B1 KR1020000034894A KR20000034894A KR100583120B1 KR 100583120 B1 KR100583120 B1 KR 100583120B1 KR 1020000034894 A KR1020000034894 A KR 1020000034894A KR 20000034894 A KR20000034894 A KR 20000034894A KR 100583120 B1 KR100583120 B1 KR 100583120B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 6
- 239000010408 film Substances 0.000 description 34
- 230000010354 integration Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상에 금속층으로 도전배선을 형성하고, 전체표면 상부에 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성한 다음, 상기 콘택홀에 의해 노출되는 도전배선의 측면을 산화시켜 상기 도전배선 측면에 절연막 스페이서를 형성하는 공정을 생략할 수 있으므로 공정을 단순하게 하고, 절연막 스페이서의 넓이 만큼 콘택면적이 증가하여 콘택저항을 개선할 수 있으며, 그에 따른 반도체소자의 고집적화를 유리하게 하는 기술이다. The present invention relates to a method for manufacturing a semiconductor device, wherein a conductive wiring is formed of a metal layer on a semiconductor substrate, and an interlayer insulating film having a contact hole for exposing a portion intended for contact is formed on the entire surface of the semiconductor substrate. Since the step of oxidizing the side surface of the conductive wiring exposed by the hole to form the insulating film spacer on the side of the conductive wiring can be omitted, the process can be simplified and the contact area can be increased by the area of the insulating film spacer to improve the contact resistance. In accordance with the present invention, the semiconductor device is advantageously integrated.
Description
도 1 은 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.
도 2a 및 도 2b 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10, 20 : 반도체기판 12, 22 : 게이트전극10, 20:
14 : 마스크절연막패턴 16 : 절연막 스페이서14 mask
18, 24 : 층간절연막 19, 26 : 콘택홀18, 24: interlayer
28 : WOx막28: WO x membrane
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 고집적 소자의 콘택 제조 공정 시 금속층 패턴의 측벽에 절연막 스페이서를 형성하지 않고, 후속공정에서 상기 금속층 패턴의 측벽을 소정 두께 산화시켜 절연막 스페이서로 사용함으로써 공정마진을 확보하고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and in particular, in the contact fabrication process of a highly integrated device, an insulating layer spacer is not formed on the sidewall of the metal layer pattern, and in the subsequent step, the sidewall of the metal layer pattern is oxidized to a predetermined thickness to be used as the insulating layer spacer. The present invention relates to a technology for securing a process margin and thereby enabling high integration of semiconductor devices.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선, 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두 층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source, or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. Tri-layer resist (hereinafter referred to as TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers or silicon on the photoresist layer. The method of injecting silicide has been developed to lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화 되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스 펙트비(aspect ratio)가 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들 간의 정확하고, 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is highly integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
이러한 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열의 여유(misalignment tolerance), 노광공정 시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화, 마스크간의 정합 등과 같은 요인들을 고려하여 마스크를 형성한다.These contact holes have factors such as misalignment tolerance during mask alignment, lens distortion during exposure process, critical size change during mask fabrication and photolithography process, and matching between masks to maintain spacing. Consider these to form a mask.
도 1 은 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도로서, 반도체기판(10) 상부에 게이트절연막(도시안됨), 게이트전극(12) 및 마스크절연막패턴(14)의 적층구조를 형성하고, 상기 적층구조의 측벽에 절연막 스페이서(16)를 형성한 후, 전체표면 상부에 콘택으로 예정되는 부분을 노출시키는 콘택홀(19)이 구비된 층간절연막(18)을 형성하였다. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art, in which a stacked structure of a gate insulating film (not shown), a
이때, 상기 마스크절연막패턴(14)과 절연막 스페이서(16)는 상기 층간절연막(18)과 식각선택비 차이를 갖는 박막으로 형성하였다. 예를 들면, 상기 층간절연막(18)이 산화막(SiO2)인 경우 마스크절연막패턴(14)과 절연막 스페이서(16)는 실리콘산질화막(SiON) 또는 실리콘질화막(Si3N4)으로 형성하였다. (도 1 참조)In this case, the mask
그러나, 종래기술에 따른 반도체소자의 제조방법은, 사진공정 시 오배열이 발생하더라도 소자가 간에 쇼트(short)되는 일없이 콘택을 형성하기 위하여 하부의 도전층패턴의 상부에 마스크절연막패턴을 형성하고, 측벽에 절연막 스페이서를 형성하여 층간절연막과 식각선택비를 이용한 자기정렬콘택(self-aligned contact)방법으로 콘택홀을 형성하였으나, 반도체소자가 고집적화되어 갈수록 소자간의 간격이 계속 좁아져 콘택홀 내의 접촉면적이 작아지고, 도전층패턴 측벽의 절연막 스페이서에 의해 콘택면적이 더욱 좁아져 콘택 저항이 증가하여 공정 수율 및 소자동작의 신뢰성을 떨어드리는 문제점이 있다.However, in the method of manufacturing a semiconductor device according to the related art, a mask insulating film pattern is formed on the lower conductive layer pattern so as to form a contact without a short between the devices even when misalignment occurs in the photolithography process. The contact hole was formed by the self-aligned contact method using the interlayer insulating film and the etch selectivity by forming the insulating film spacer on the sidewall. The area is reduced, and the contact area is further narrowed by the insulating film spacers on the sidewalls of the conductive layer pattern, thereby increasing the contact resistance, thereby decreasing process yield and reliability of device operation.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 텅스텐막 패턴으로 게이트전극 또는 비트라인을 형성하고, 전체표면 상부에 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성한 다음, 상기 콘택홀에 의해 노출된 텅스텐막 패턴을 산화시켜 소자간을 절연시킴으로써 콘택면적을 증가시켜 콘택 저항을 감소시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a gate electrode or a bit line is formed of a tungsten film pattern, and an interlayer insulating film having contact holes for exposing a portion intended for contact is formed on the entire surface. The present invention provides a method of fabricating a semiconductor device, which reduces the contact resistance by increasing the contact area by oxidizing the tungsten film pattern exposed by the contact hole to insulate the devices, thereby enabling high integration of the semiconductor device. There is this.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은, Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 금속층으로 형성된 도전배선을 형성하는 공정과,Forming a conductive wiring formed of a metal layer on the semiconductor substrate;
전체표면 상부에 상기 금속층과 식각선택비 차이를 갖는 층간절연막을 형성하는 공정과, Forming an interlayer insulating film having a difference in etching selectivity with the metal layer over the entire surface;
상기 반도체기판에서 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성하는 공정과, Forming a contact hole by etching the interlayer insulating layer with an etch mask using a contact mask that exposes a portion of the semiconductor substrate to be contacted;
상기 콘택홀에 노출되는 상기 도전배선을 산화시켜 절연막 스페이서로 사용하여 콘택 면적을 증가시키는 공정을 포함하는 것을 특징으로 한다.And oxidizing the conductive wiring exposed to the contact hole to use as an insulating film spacer, thereby increasing a contact area.
이하, 첨부된 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings will be described in detail.
도 2a 및 도 2b 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다. 2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(20) 상부에 게이트절연막(도시안됨) 및 텅스텐층(도시안됨)을 순차적으로 형성한다. First, a gate insulating film (not shown) and a tungsten layer (not shown) are sequentially formed on the
상기 텅스텐층 대신 몰리브덴층 또는 상기 텅스텐층 및 몰리브덴층의 합금층으로 형성할 수 있다.Instead of the tungsten layer may be formed of a molybdenum layer or an alloy layer of the tungsten layer and molybdenum layer.
상기 텅스텐층 상부에 마스크절연막을 형성할 수도 있다. 이때, 상기 마스크절연막은 실리콘산화질화막 또는 실리콘질화막 또는 알루미늄산화막으로 형성한다. A mask insulating film may be formed on the tungsten layer. In this case, the mask insulating film is formed of a silicon oxynitride film, a silicon nitride film or an aluminum oxide film.
다음, 게이트전극으로 예정되는 부분을 보호하는 게이트전극 마스크를 식각마스크로 상기 금속층과 게이트절연막을 식각하여 게이트전극(22)을 형성한다. Next, the
그 다음, 전체표면 상부에 산화막으로 층간절연막(24)을 형성하고, 콘택으로 예정되는 부분을 노출시키는 콘택마스크를 식각마스크로 상기 층간절연막(24)을 식각하여 콘택홀(26)을 형성한다. 이때, 상기 콘택마스크는 상기 게이트전극(22) 간의 거리보다 넓은 부분을 노출시키므로, 콘택홀(26) 형성 후 도 2a 에 도시된 ⓧ부분과 같이 게이트전극(22)의 일부가 노출된다.Next, an
상기 식각공정은 탄소/불소의 비율이 높은 C2/F6, C3/F8, C
4/F8 및 C5/F8 가스 로 이루어지는 군에서 임의로 선택되는 하나를 이용하여 식각함으로써 상기 게이트전극(22)과 층간절연막(24) 간에 식각선택비 차이를 높게 유지하면서 식각공정을 실시할 수 있다. The etching process may be performed by etching using one selected from the group consisting of C 2 / F 6 , C 3 / F 8 , C 4 / F 8, and C 5 / F 8 gas having a high carbon / fluorine ratio. An etching process may be performed while maintaining a high difference in etching selectivity between the
다음, 상기 노출된 게이트전극(22)을 산화시켜 WOx막(28)으로 형성한다. 이때, 상기 산화공정은 콘택홀(26) 형성 후 인시튜(insitu)로 실시하되, O2 가스를 첨가가스로 사용하여 상기 게이트전극(22)의 측면이 100 ∼ 200Å 두께로 산화되도록 실시한다. Next, the exposed
그 다음, 상기 산화공정으로 콘택홀(26) 저부에 형성된 산화막을 BOE용액 등을 이용하여 제거한다. Next, the oxide film formed on the bottom of the
한편, 상기 층간절연막(24)을 유기저유전체막으로 형성하는 경우 상기 층간절연막(24)을 O2 가스를 식각가스로 사용하여 식각하면서 인시튜(insitu)로 산화공정을 실시할 수 있다. Meanwhile, when the interlayer insulating
상기 실시예에서는 게이트전극 사이에 콘택홀을 형성하는 공정을 기재하였으나, 비트라인 형성 후에도 상기와 같은 방법으로 콘택홀을 형성할 수 있다. In the above embodiment, a process of forming contact holes between gate electrodes is described. However, the contact holes may be formed in the same manner as described above even after the bit line is formed.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상에 금속층으로 도전배선을 형성하고, 전체표면 상부에 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성한 다음, 상기 콘택홀에 의해 노출되는 도전배선의 측면을 산화시켜 상기 도전배선 측면에 절연막 스페이서를 형성하는 공정을 생략할 수 있으므로 공정을 단순하게 하고, 절연막 스페이서의 넓이 만큼 콘택면적이 증가하여 콘택저항을 개선할 수 있으며, 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, a conductive wiring is formed of a metal layer on a semiconductor substrate, and an interlayer insulating film having contact holes for exposing a portion to be contacted is formed over the entire surface. Next, since the step of oxidizing the side surface of the conductive wiring exposed by the contact hole to form the insulating film spacer on the side of the conductive wiring can be omitted, the process is simplified and the contact area is increased by the area of the insulating film spacer so that the contact resistance is increased. It can be improved, and there is an advantage that advantageously high integration of the semiconductor device.
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