KR100577308B1 - 반도체 소자 및 그의 제조 방법 - Google Patents
반도체 소자 및 그의 제조 방법 Download PDFInfo
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- KR100577308B1 KR100577308B1 KR1020040114798A KR20040114798A KR100577308B1 KR 100577308 B1 KR100577308 B1 KR 100577308B1 KR 1020040114798 A KR1020040114798 A KR 1020040114798A KR 20040114798 A KR20040114798 A KR 20040114798A KR 100577308 B1 KR100577308 B1 KR 100577308B1
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- conductive layer
- passivation layer
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 238000002161 passivation Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000001681 protective effect Effects 0.000 claims abstract description 27
- 239000010949 copper Substances 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052802 copper Inorganic materials 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 238000011109 contamination Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 76
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 230000007547 defect Effects 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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Abstract
Description
Claims (10)
- 메인 칩 부분과 소자 절단부를 구비하고 복수개의 배선이 형성된 반도체 기판;상기 반도체 기판상에 형성된 절연막;상기 메인칩 부분의 상기 절연막위에 형성된 제 1 도전층 및 상기 소자 절단부의 절연막위에 형성된 얼라인 마크;상기 제 1 도전층을 제외한 상기 반도체 기판 전면에 형성된 제 1 보호막;상기 소자 절단부 및 상기 제 1 도전층을 제외한 상기 메인 칩 부분의 기판에 형성된 제 2 보호막;상기 제 1 도전층에 전기적으로 연결되도록 상기 제 2 보호막상에 형성된 제 2 도전층; 그리고상기 소자 절단부 및 상기 제 2 도전층을 제외한 상기 메인 칩 부분의 기판에 형성된 제 3 보호막을 포함하여 구성됨을 특징으로 하는 반도체 소자.
- 제 1 항에 있어서,상기 제 1 도전층 및 얼라인 마크는 구리로 형성됨을 특징으로 하는 반도체 소자.
- 제 1 항에 있어서,상기 제 1 보호막과 제 2 보호막은 각각 다른 식각 선택비를 갖음을 특징으로 하는 반도체 소자.
- 제 1 항에 있어서,상기 제 1 보호막은 실리콘 질화막으로 형성되고, 상기 제 2 보호막은 TEOS 산화막으로 형성됨을 특징으로 하는 반도체 소자.
- 제 1 항에 있어서,상기 제 2 도전층은 알루미늄으로 형성됨을 특징으로 하는 반도체 소자.
- 메인 칩 부분과 소자 절단부를 구비하고 복수개의 배선이 형성된 반도체 기판을 준비하는 단계;상기 반도체 기판상에 절연막을 형성하고, 상기 메인칩 부분의 상기 절연막위에 제 1 도전층 및 상기 소자 절단부의 절연막위에 얼라인 마크를 형성하는 단계;상기 제 1 도전층 및 얼라인 마크를 포함한 기판 전면에 제 1 보호막 및 제 2 보호막을 형성하는 단계;상기 메인 칩 부분의 본딩 패드가 될 영역의 상기 제 1, 제 2 보호막을 제거하여 상기 도전층을 노출시키는 단계;상기 제 1 도전층에 전기적으로 연결되도록 본딩 패드 영역에 제 2 도전층을 형성하는 단계;상기 제 2 도전층을 포함한 기판 전면에 제 3 보호막을 형성하는 단계; 그리고,상기 본딩 패드가 될 부분의 제 3 보호막과 상기 소자 절단부의 제 2, 제 3 보호막을 선택적으로 제거하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법.
- 제 6 항에 있어서,상기 제 1 도전층 및 얼라인 마크는 구리로 형성함을 특징으로 하는 반도체 소자의 제조 방법.
- 제 6 항에 있어서,상기 제 1 보호막과 제 2 보호막은 각각 다른 식각 선택비를 갖는 물질로 형성함을 특징으로 하는 반도체 소자의 제조 방법.
- 제 6 항에 있어서,상기 제 1 보호막은 실리콘 질화막으로 형성하고, 상기 제 2 보호막은 TEOS 산화막으로 형성함을 특징으로 하는 반도체 소자의 제조 방법.
- 제 6 항에 있어서,상기 제 2 도전층은 알루미늄으로 형성함을 특징으로 하는 반도체 소자의 제 조 방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040114798A KR100577308B1 (ko) | 2004-12-29 | 2004-12-29 | 반도체 소자 및 그의 제조 방법 |
US11/312,595 US7575980B2 (en) | 2004-12-29 | 2005-12-21 | Semiconductor device and method for manufacturing the same |
US12/458,682 US7839006B2 (en) | 2004-12-29 | 2009-07-20 | Semiconductor device and method for manufacturing the same |
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Application Number | Priority Date | Filing Date | Title |
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KR1020040114798A KR100577308B1 (ko) | 2004-12-29 | 2004-12-29 | 반도체 소자 및 그의 제조 방법 |
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KR100577308B1 true KR100577308B1 (ko) | 2006-05-10 |
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KR1020040114798A KR100577308B1 (ko) | 2004-12-29 | 2004-12-29 | 반도체 소자 및 그의 제조 방법 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100620430B1 (ko) | 2005-04-29 | 2006-09-06 | 삼성전자주식회사 | 반도체 장치의 얼라인 키 구조물 및 이를 형성하는 방법 |
KR100731128B1 (ko) * | 2005-12-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
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US7344956B2 (en) * | 2004-12-08 | 2008-03-18 | Miradia Inc. | Method and device for wafer scale packaging of optical devices using a scribe and break process |
KR100660893B1 (ko) * | 2005-11-22 | 2006-12-26 | 삼성전자주식회사 | 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법 |
JP2010021293A (ja) * | 2008-07-09 | 2010-01-28 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
US9293388B2 (en) * | 2013-10-22 | 2016-03-22 | Globalfoundries Singapore Pte. Ltd. | Reliable passivation layers for semiconductor devices |
US10290596B2 (en) * | 2016-12-14 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a passivation layer and method of making the same |
JP2019054172A (ja) * | 2017-09-15 | 2019-04-04 | 東芝メモリ株式会社 | 半導体装置 |
CN110587713A (zh) * | 2018-06-13 | 2019-12-20 | 南昌欧菲显示科技有限公司 | 保护膜检测方法、保护膜切割方法以及保护膜切割刀模 |
CN115362549A (zh) * | 2020-04-17 | 2022-11-18 | 华为技术有限公司 | 电子设备、半导体晶片、芯片封装结构及其制作方法 |
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Cited By (2)
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KR100620430B1 (ko) | 2005-04-29 | 2006-09-06 | 삼성전자주식회사 | 반도체 장치의 얼라인 키 구조물 및 이를 형성하는 방법 |
KR100731128B1 (ko) * | 2005-12-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
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US20100019353A1 (en) | 2010-01-28 |
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