KR100577011B1 - Method for forming the semiconductor device - Google Patents

Method for forming the semiconductor device Download PDF

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KR100577011B1
KR100577011B1 KR1020020040085A KR20020040085A KR100577011B1 KR 100577011 B1 KR100577011 B1 KR 100577011B1 KR 1020020040085 A KR1020020040085 A KR 1020020040085A KR 20020040085 A KR20020040085 A KR 20020040085A KR 100577011 B1 KR100577011 B1 KR 100577011B1
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trench
forming
insulating film
silicon substrate
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KR20040005508A (en
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이진호
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 메모리(Memory)소자의 BN 구조 형성방법에 있어서, 실리콘기판에 등방성 식각에 의해 트랜치를 형성하여 트랜치 주변에 이온주입하여 BN 정션을 형성한 후, 트랜치 내에 산화막을 매립하여 BN층을 형성하는 것을 특징으로 하는 트랜치형 BN 구조를 형성함으로써 셀 영역을 평탄하게 형성시켜 소자의 동작 속도를 증가시킬 수 있으며, BN 정션의 안정화를 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the method for forming a BN structure of a memory device, a trench is formed by isotropic etching on a silicon substrate and ion implanted around the trench to form a BN junction. By forming a trench type BN structure, which forms a BN layer by embedding an oxide film in the trench, the cell region can be formed flat to increase the operation speed of the device, and improve the stabilization of the BN junction. And a technique for improving reliability.

BN층, BN정션, 트랜치BN floor, BN junction, trench

Description

반도체소자의 제조방법{Method for forming the semiconductor device} Method for manufacturing a semiconductor device {Method for forming the semiconductor device}             

도 1a 내지 도 1e는 종래 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.1A through 1E are cross-sectional views sequentially illustrating a method of manufacturing a conventional semiconductor device.

도 2는 종래 반도체소자의 제조방법에 의해 형성된 BN 구조의 문제점을 나타낸 SEM 사진이다.2 is a SEM photograph showing the problem of the BN structure formed by the conventional method of manufacturing a semiconductor device.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.3A through 3E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

-- 도면의 주요부분에 대한 부호의 설명 --  -Explanation of symbols for the main parts of the drawing-

10 : 실리콘기판 20 : n-웰10: silicon substrate 20: n-well

30 : 필드산화막 40 : 절연막30: field oxide film 40: insulating film

50 : 스페이서 60 : 트랜치50: spacer 60: trench

70 : BN 정션 80 : BN층 70: BN junction 80: BN floor

본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게는 메모리(Memory)소자의 BN 구조 형성방법에 있어서, 실리콘기판에 트랜치 기법을 사용하여 BN정션을 형성한 후, 트랜치를 매립하여 BN층을 형성하여 평탄한 셀 영역을 형성하도록 하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in a method of forming a BN structure of a memory device, after forming a BN junction on a silicon substrate by using a trench technique, embedding a trench to form a BN layer. The present invention relates to a method for manufacturing a semiconductor device to form a flat cell region.

일반적으로, 플래쉬 이이피롬(FLASH EEPROM)셀이나, 마스크 롬(MASK ROM)의 셀에서 사용중인 베리드 N+(Buried N+)(이하, BN 정션이라 칭함)는 버츄얼 그라운드(Virtual Ground)가 가능하고 콘택(contact)의 수를 감소시킴으로서 사이즈를 감소시키는 잇점이 있다.In general, the buried N + (Buried N + ) (hereinafter referred to as BN junction) used in a flash EEPROM cell or a mask ROM cell can be a virtual ground. And the size is reduced by reducing the number of contacts.

도 1a 내지 도 1e는 종래 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.1A through 1E are cross-sectional views sequentially illustrating a method of manufacturing a conventional semiconductor device.

먼저, 도 1a에 도시된 바와 같이, p형 실리콘기판(1)에 필드산화막(3)을 형성하여 소자를 격리하는 격리영역과 소자를 형성하는 활성영역으로 정의한 후, 활성영역 내에 n-웰(2)을 형성한다.First, as shown in FIG. 1A, a field oxide film 3 is formed on a p-type silicon substrate 1 to define an isolation region to isolate an element and an active region to form an element, and then n-well ( 2) form.

그리고, 도 1b에 도시된 바와 같이, 상기 실리콘기판(1)의 활성영역에 질화물을 이용하여 약 1000Å 정도 증착하여 절연막(4)을 형성하고 절연막(4) 상부에 감광막을 도포한 후 노광 및 현상공정을 진행하여 BN층 형성영역이 개방되도록 감광막 패턴(미도시함)을 형성한다.As shown in FIG. 1B, an insulating film 4 is formed by depositing about 1000 GPa of nitride in the active region of the silicon substrate 1 by applying a photoresist film on the insulating film 4, followed by exposure and development. The process proceeds to form a photoresist pattern (not shown) to open the BN layer formation region.

이때, 상기 절연막(4)은 후속 옥시데이션 공정에 의한 BN층 형성 시, 장벽층 역할 및 BN 정션 형성을 위한 이온 주입 시, 이온주입 마스크 역할을 한다.In this case, the insulating film 4 serves as a barrier layer when forming a BN layer by a subsequent oxidation process and as an ion implantation mask when implanting ions for forming a BN junction.

이어서, 상기 감광막 패턴(미도시함)을 마스크로 하여 절연막(4)을 식각하여 실리콘기판(1)을 소정부분 노출시킨 후, 감광막 패턴(미도시함)을 제거한다.Subsequently, the insulating film 4 is etched using the photoresist pattern (not shown) as a mask to expose the silicon substrate 1 by a predetermined portion, and then the photoresist pattern (not shown) is removed.

그 후, 도 1c에 도시된 바와 같이 결과물 전체에 약 800Å 정도의 두께로 산화막(미도시함)을 증착한 후, 이를 전면식각하여 절연막(4) 측벽에 산화막으로 이루어진 스페이서(5)를 형성한다.Thereafter, an oxide film (not shown) is deposited to a total thickness of about 800 GPa on the entire resultant, as shown in FIG. 1C, and then etched to form a spacer 5 made of an oxide film on the sidewall of the insulating film 4. .

그리고, 도 1d에 도시된 바와 같이 상기 절연막(4)과 스페이서(5)를 마스크로 이용하여 노출된 실리콘기판에 As 이온을 경사없이 수직으로 주입한 후, 옥시데이션 및 열처리 공정을 수행하면 실리콘기판 상에 BN층(6)인 산화막이 성장함과 동시에 이온확산에 의해 BN층(6) 하부에 BN 정션(7)이 형성되며, 이때, 상기 BN 정션(7)은 소자의 소오스 및 드레인영역으로 사용된다.In addition, as shown in FIG. 1D, the As substrate is vertically injected without inclination into the exposed silicon substrate using the insulating film 4 and the spacer 5 as a mask, and then the silicon substrate is subjected to the oxidation and heat treatment processes. At the same time, an oxide film, which is a BN layer 6, grows, and at the same time, a BN junction 7 is formed below the BN layer 6 by ion diffusion, and the BN junction 7 is used as a source and drain region of the device. do.

이어서, 도 1e에 도시된 바와 같이, 상기 절연막과 스페이서를 제거함으로써, 옥시데이션에 의해 형성된 BN 구조를 형성한다.Subsequently, as illustrated in FIG. 1E, the insulating film and the spacer are removed to form a BN structure formed by oxidization.

그러나, 상기와 같은 종래 반도체소자의 제조방법에 의해 BN 구조를 형성하면, 도 2의 "A"와 같이 옥시데이션에 의해 산화막 형성 시, 버즈빅이 형성되어 셀의 CD 및 정션에 악영향을 주어 반도체소자의 특성과 신뢰성을 저하시키는 문제점이 있었다. However, if the BN structure is formed by the conventional method of manufacturing a semiconductor device as described above, when the oxide film is formed by oxidization as shown in " A " of FIG. 2, a burj bic is formed and adversely affects the CD and the junction of the semiconductor. There was a problem of degrading the characteristics and reliability of the device.

또한, 상기 열공정 시 주입된 이온이 확산되어 형성되는 BN 정션은 "B"와 같이 상부 모서리 부분이 얇게 형성되어 셀 특성, 즉 온/오프 셀 문턱전압과 전류 및 속도 등을 저하시켜 반도체소자의 제조수율을 감소시키는 문제점이 있었다.In addition, the BN junction formed by diffusion of ions implanted in the thermal process has a thin upper edge portion, such as "B", and thus deteriorates cell characteristics, that is, on / off cell threshold voltage, current, and speed, and so on. There was a problem in reducing the production yield.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 메모리(Memory)소자의 BN 구조 형성방법에 있어서, 실리콘기판에 등방성 식각에 의해 트랜치를 형성하여 트랜치 주변에 이온주입하여 BN 정션을 형성한 후, 트랜치 내에 산화막을 매립하여 BN층을 형성하는 것을 특징으로 하는 트랜치형 BN 구조를 형성함으로써 셀 영역을 평탄하게 형성시켜 소자의 동작 속도를 증가시킬 수 있으며, BN 정션의 안정화를 향상시키도록 하는 반도체소자의 제조방법을 제공하는 것이다.
The present invention has been made to solve the above problems, and an object of the present invention is to form a trench by isotropic etching on a silicon substrate in the method of forming a BN structure of a memory device by ion implantation around the trench After forming the BN junction, a trench type BN structure is formed by embedding an oxide film in the trench to form a BN layer, thereby forming a flat cell region, thereby increasing the operation speed of the device, and stabilizing the BN junction. It is to provide a method for manufacturing a semiconductor device to improve the.

상기 목적을 달성하기 위하여, 본 발명은 소자분리막과 웰이 형성된 실리콘기판 상에 절연막을 형성한 후 절연막 상부에 BN층 형성 영역이 개방되도록 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 절연막을 식각하여 실리콘기판을 소정부분 노출시킨 후 감광막 패턴을 제거하는 단계와, 상기 결과물 상에 스페이서 형성물질을 증착한 후 등방성 오버식각하여 반도체기판 내에 트랜치와 절연막 측벽에 스페이서를 형성하는 단계와, 상기 절연막과 스페이서를 마스크로 BN 정션 형성을 위한 BN 이온을 주입하고 절연막과 스페이서를 제거하는 단계와, 상기 결과물 상에 산화막을 증착한 후 실리콘기판 상부까지 등방성 식각하여 BN층을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 제조방법을 제공한다.In order to achieve the above object, the present invention is to form an insulating film on the silicon substrate on which the device isolation film and the well is formed, forming a photoresist pattern so that the BN layer forming region is opened on the insulating film, and the insulating film using the photoresist pattern as a mask Etching a portion of the silicon substrate to expose a predetermined portion of the silicon substrate, removing the photoresist pattern, depositing a spacer forming material on the resultant, and then isotropically etching to form a spacer in the trench and the insulating film sidewall in the semiconductor substrate; Implanting BN ions for forming the BN junction with the insulating film and the spacer as a mask, removing the insulating film and the spacer, depositing an oxide film on the resultant, and isotropically etching the silicon substrate to form a BN layer. It provides a method for manufacturing a semiconductor device, characterized in that made.

본 발명은 상기 스페이서 형성물질을 산화물을 이용하여 700~900Å 두께로 증착한 후, 습식 등방성 식각으로 실리콘기판을 표면으로부터 300 ~ 400Å 오버식각하여 실리콘기판 내에 하부가 라운딩진 트랜치를 형성하는 것을 특징으로 한다.The present invention is characterized by depositing the spacer forming material to a thickness of 700 ~ 900Å by using an oxide, and then etching the silicon substrate 300 ~ 400Å over the surface by wet isotropic etching to form a rounded trench in the silicon substrate do.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.3A through 3E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

먼저, 도 3a에 도시된 바와 같이 p형 실리콘기판(10)에 필드산화막(30)을 형성하여 소자를 분리하는 소자분리영역과 소자를 형성하는 활성영역으로 정의한 후, n-웰(20)을 형성한다.First, as shown in FIG. 3A, the field oxide layer 30 is formed on the p-type silicon substrate 10 to define an isolation region for separating devices and an active region for forming devices, and then the n-well 20 is defined. Form.

그리고, 도 3b에 도시된 바와 같이 상기 실리콘기판(10)의 활성영역에 질화물을 이용하여 900~1100Å 바람직하게는 약 1000Å 정도 증착하여 절연막(40)을 형성하고 절연막(40) 상부에 감광막을 도포한 후 노광 및 현상공정을 진행하여 BN층 형성영역이 개방되도록 감광막 패턴(미도시함)을 형성한다.As shown in FIG. 3B, an insulating film 40 is formed by depositing 900 to 1100 Å, preferably about 1000 Å, using nitride in the active region of the silicon substrate 10 to form a photoresist film on the insulating film 40. After that, an exposure and development process is performed to form a photoresist pattern (not shown) to open the BN layer formation region.

이어서, 상기 감광막 패턴(미도시함)을 마스크로 하여 절연막(40)을 식각하여 실리콘기판(10)의 BN층 형성영역을 노출시킨 후, 감광막 패턴(미도시함)을 제거한다.Subsequently, the insulating film 40 is etched using the photoresist pattern (not shown) as a mask to expose the BN layer formation region of the silicon substrate 10, and then the photoresist pattern (not shown) is removed.

그리고, 도 3c에 도시된 바와 같이 상기 결과물 전체에 산화물을 이용하여 700~900Å 두께로 스페이서 형성물질을 증착한 후, 습식 등방성 식각으로 실리콘기 판(10)을 표면으로부터 300 ~ 400Å 오버식각하여 절연막(40) 측벽에 스페이서(50) 및 실리콘기판(10) 내에 깊이 300 ~ 400Å의 트랜치(60)를 형성한다.Then, as shown in FIG. 3c, after depositing a spacer forming material to a thickness of 700 ~ 900Å by using an oxide on the entire result, the silicon substrate 10 by 300 to 400Å over-etched from the surface by wet isotropic etching (40) A trench 60 having a depth of 300 to 400 내에 is formed in the spacer 50 and the silicon substrate 10 on the side wall.

이때, 상기 트랜치(60)는 습식 등방성 식각에 의해 트랜치(60)의 하부가 라운딩지게 형성되어, 후속 BN 이온 주입시 확산공정 없이 수직으로 BN 이온을 주입하여 BN 정션을 형성할 수 있다.In this case, the trench 60 may be formed so that the lower portion of the trench 60 is rounded by wet isotropic etching, thereby forming BN junctions by vertically injecting BN ions without a diffusion process during subsequent BN ion implantation.

그 후, 도 3d에 도시된 바와 같이 상기 절연막(미도시함)과 스페이서(미도시함)를 이온주입 마스크로 BN 이온으로 As 이온을 노출된 실리콘기판 내에 수직으로 주입하여 트랜치(60) 하부 주변에 BN 정션(70)을 형성한 후, 이온주입 마스크로 이용한 절연막(미도시함)과 스페이서(미도시함)를 제거한다.Thereafter, as shown in FIG. 3D, the insulating layer (not shown) and the spacer (not shown) are vertically implanted with BN ions into the exposed silicon substrate with the ion implantation mask to thereby surround the lower portion of the trench 60. After the BN junction 70 is formed in the insulating film, an insulating film (not shown) and a spacer (not shown) used as an ion implantation mask are removed.

그리고, 도 3e에 도시된 바와 같이 상기 결과물 상에 블랭켓(blanket)으로 약 450~550Å 정도 산화막(미도시함)을 증착한 후, 실리콘기판(10) 상부까지 등방성 식각하여 산화막(미도시함) 상부가 라운딩지게 BN층(80)을 형성함으로써, 트랜치형 BN 구조를 형성한다.As shown in FIG. 3E, an oxide film (not shown) is deposited on the resultant with a blanket about 450 to 550 Å, and isotropically etched to the upper portion of the silicon substrate 10 to form an oxide film (not shown). By forming the BN layer 80 so that the upper part is rounded, a trench type BN structure is formed.

그 결과, 상기 트랜치형 BN 구조는 기존의 옥시데이션 공정에 의해 형성되던 산화막의 버즈빅 형성을 방지하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있으며, 이온주입 후 확산공정에 의해 형성되던 BN 정션을 이온주입만으로 형성할 수 있어 공정을 단순화시킬 수 있다. As a result, the trench type BN structure can improve the characteristics and reliability of the semiconductor device by preventing the formation of the oxide film formed by the conventional oxidation process, and the BN junction formed by the diffusion process after ion implantation. It can be formed only by ion implantation, which simplifies the process.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 제조방법을 이용하 게 되면, 실리콘기판에 등방성 식각에 의해 트랜치를 형성하여 트랜치 주변에 이온주입하여 BN 정션을 형성한 후, 트랜치 내에 산화막을 매립하여 BN층을 형성하는 것을 특징으로 하는 트랜치형 BN 구조를 형성함으로써 셀 영역을 평탄하게 형성시켜 소자의 동작 속도를 증가시킬 수 있을 뿐만 아니라 BN 정션의 안정화를 향상시켜 반도체소자의 특성 및 신뢰성을 개선하여 향상시키는 이점이 있다.Therefore, as described above, when the semiconductor device manufacturing method according to the present invention is used, a trench is formed on the silicon substrate by isotropic etching, ion implantation is performed around the trench to form a BN junction, and an oxide film is embedded in the trench. By forming the trench type BN structure, which forms a BN layer, the cell area can be formed flat to increase the operation speed of the device, and improve the stability and stability of the BN junction to improve the characteristics and reliability of the semiconductor device. There is an advantage to improve.

Claims (5)

소자분리막과 웰이 형성된 실리콘기판 상에 절연막을 형성한 후, 절연막 상부에 BN층 형성 영역이 개방되도록 감광막 패턴을 형성하는 단계와;Forming an insulating film on the silicon substrate on which the device isolation film and the well are formed, and then forming a photoresist pattern on the insulating film to open the BN layer forming region; 상기 감광막 패턴을 마스크로 절연막을 식각하여 실리콘기판을 소정부분 노출시킨 후 감광막 패턴을 제거하는 단계와;Etching the insulating film using the photoresist pattern as a mask to expose a predetermined portion of the silicon substrate, and then removing the photoresist pattern; 상기 결과물 상에 스페이서 형성물질을 증착한 후, 등방성 오버식각하여 반도체기판 내에 트랜치와 절연막 측벽에 스페이서를 형성하는 단계와;Depositing a spacer forming material on the resultant, and then isotropic over-etching to form a spacer in the trench and the insulating film sidewalls in the semiconductor substrate; 상기 절연막과 스페이서를 마스크로 BN 정션 형성을 위한 BN 이온으로 As이온을 수직으로 주입하고 절연막과 스페이서를 제거하는 단계와; Vertically implanting As ions into the BN ions for forming the BN junction using the insulating film and the spacer as a mask and removing the insulating film and the spacer; 상기 결과물 상에 산화막을 증착한 후, 실리콘기판 상부까지 등방성 식각하여 BN층을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 제조방법.And depositing an oxide film on the resultant, and isotropically etching the silicon substrate to form a BN layer. 제 1항에 있어서, 상기 절연막은 질화물을 블랭켓으로 900 ~ 1100Å 두께로 증착하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the insulating layer is formed by depositing a nitride having a thickness of 900 to 1100 Å with a blanket. 제 1항에 있어서, 상기 스페이서 형성물질은 산화물을 이용하여 700~900Å 두께로 증착하는 것을 특징으로 하는 반도체소자의 제조방법. The method of claim 1, wherein the spacer forming material is deposited to a thickness of 700 to 900 Å using an oxide. 제 1항에 있어서, 상기 트랜치 및 스페이서는 스페이서 형성물질을 습식 등방성 식각으로 실리콘기판을 표면으로부터 300 ~ 400Å 오버식각하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법. The method of claim 1, wherein the trench and the spacer are formed by wet etching the silicon substrate from 300 to 400 μs from the surface by wet isotropic etching. 삭제delete
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527727A (en) * 1994-09-27 1996-06-18 Hyundai Electronics Industries Co. Ltd. Method of manufacturing split gate EEPROM cells
KR100218330B1 (en) * 1996-11-08 1999-09-01 구본준 A nor-type mask rom and fabrication method of the same
JP2001007224A (en) * 1999-06-22 2001-01-12 Sharp Corp Semiconductor device and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527727A (en) * 1994-09-27 1996-06-18 Hyundai Electronics Industries Co. Ltd. Method of manufacturing split gate EEPROM cells
KR100218330B1 (en) * 1996-11-08 1999-09-01 구본준 A nor-type mask rom and fabrication method of the same
JP2001007224A (en) * 1999-06-22 2001-01-12 Sharp Corp Semiconductor device and manufacture thereof

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