KR100575080B1 - Method for fabricating shallow trench isolation - Google Patents

Method for fabricating shallow trench isolation Download PDF

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KR100575080B1
KR100575080B1 KR1020030101646A KR20030101646A KR100575080B1 KR 100575080 B1 KR100575080 B1 KR 100575080B1 KR 1020030101646 A KR1020030101646 A KR 1020030101646A KR 20030101646 A KR20030101646 A KR 20030101646A KR 100575080 B1 KR100575080 B1 KR 100575080B1
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김봉길
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
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    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract

본 발명은 습식 식각에 의해 STI의 가장자리가 습식 공정에 의해 유실되지 않도록 STI를 형성 하는 방법에 관한 것이다.The present invention relates to a method of forming an STI such that the edge of the STI is not lost by the wet process by wet etching.

본 발명의 소자 분리막 형성 방법은 소정의 소자가 형성된 기판상에 제1산화막 및 제1질화막을 순차적으로 형성하고, 상기 제1질화막 상부에 패턴을 형성하는 단계; 상기 패턴을 이용하여 제1질화막, 제1산화막 및 기판을 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 제2산화막으로 매립하는 단계; 상기 기판을 제1평탄화하고 습식 식각으로 산화물을 제거하는 단계; 상기 기판상에 제2질화막을 형성하는 단계; 및 상기 기판을 제2평탄화하는 단계를 포함하여 이루어짐에 기술적 특징이 있다.The method of forming a device isolation layer of the present invention comprises the steps of sequentially forming a first oxide film and a first nitride film on a substrate on which a predetermined device is formed, and forming a pattern on the first nitride film; Forming a trench by etching the first nitride film, the first oxide film and the substrate using the pattern; Filling the trench with a second oxide film; First planarizing the substrate and removing oxide by wet etching; Forming a second nitride film on the substrate; And a step of flattening the substrate.

따라서, 본 발명의 소자 분리막 형성 방법은 소자 분리막의 가장 자리의 산화막이 유실되는 것을 보상하여 소자의 특성을 개선하는 효과가 있다.Therefore, the device isolation film forming method of the present invention has the effect of compensating for the loss of the oxide film at the edge of the device isolation film to improve the characteristics of the device.

STI, 산화막STI, oxide

Description

소자 분리막 형성 방법{Method for fabricating shallow trench isolation} Method for fabricating shallow trench isolation             

도 1a 내지 도 1e는 종래기술에 의한 소자 분리막 형성 방법의 공정 단면도.1A to 1E are cross-sectional views of a method of forming a device isolation film according to the prior art.

도 2a 내지 도 2c는 본 발명에 소자 분리막 형성 방법의 공정 단면도.2A to 2C are cross-sectional views of a method of forming an isolation layer in the present invention.

본 발명은 소자 분리막 형성 방법에 관한 것으로, 보다 자세하게는 산화물 제거에 의해 소자 분리막의 가장자리도 유실되는데, 이를 질화막으로 충진하여 소자 분리막을 형성 하는 것에 관한 것이다.The present invention relates to a method of forming a device isolation layer, and more particularly, to the edge of the device isolation layer is also lost by removing the oxide, and relates to the formation of the device isolation layer by filling it with a nitride film.

종래에는, 일반적으로 반도체 소자를 분리하는 방법으로는 선택적 산화법으로 질화막을 이용하는 LOCOS(local oxidation of silicon, 이하 LOCOS) 소자 분리 방법이 이용되어 왔다. LOCOS 소자 분리 방법은 질화막을 마스크로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 이점이 있다. 그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 소자의 미세화에 한계가 있 을 뿐만 아니라 버즈 비크(bird's beak)가 발생하게 된다.Conventionally, a LOCOS (local oxidation of silicon, LOCOS) device isolation method using a nitride film has been used as a method for separating semiconductor devices. Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple, and there is an advantage that the device stress problem of the oxide film is small, and the resulting oxide film quality is good. However, when the LOCOS device isolation method is used, the area of the device isolation region is large, thereby limiting the miniaturization of the device and generating a bird's beak.

상기와 같은 문제점을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(shallow trench isolation, 이하 STI)가 있다. 트렌치 소자 분리에서는 실리콘 웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 소자의 미세화에 유리하다. 현재 적용되는 STI 공정은 반도체 기판을 건식 식각하여 트렌치를 형성한 후 건식식각으로 인한 손상(damage)을 큐어링(curing)한 후, 계면 특성 및 활성영역과 소자격리영역의 모서리 라운딩 특성을 향상시키기 위해 트렌치 내부를 열산화하여 산화막을 형성하는 공정을 진행한다. 이후 산화막이 형성된 트렌치를 메우도록 반도체 기판 전면에 절연막을 두껍게 증착하고 화학적 기계적 연마(chemical mechanical polishing)를 진행하여 반도체 기판을 평탄화한다.In order to overcome the above problems, there is a trench trench isolation (STI) as a technique to replace the LOCOS device isolation method. In trench device isolation, a trench is formed in a silicon wafer to insulate the insulator, so the area of the device isolation region is small, which is advantageous for miniaturization of the device. Currently applied STI process is to dry the semiconductor substrate to form a trench, and then to cure the damage caused by dry etching, and then to improve the interface characteristics and the corner rounding characteristics of the active region and the device isolation region In order to do this, the inside of the trench is thermally oxidized to form an oxide film. Thereafter, an insulating film is thickly deposited on the entire surface of the semiconductor substrate to fill the trench in which the oxide film is formed, and chemical mechanical polishing is performed to planarize the semiconductor substrate.

도 1a 내지 도 1d는 종래 기술에 의한 STI 형성 방법의 공정 단면도이다.1A to 1D are cross-sectional views of a STI forming method according to the prior art.

먼저, 도 1a에서 보는 바와 같이 기판(10)상에 패드 산화막(11) 및 질화막(12)을 증착한 후, 패턴(13)을 형성한다.First, as shown in FIG. 1A, after the pad oxide film 11 and the nitride film 12 are deposited on the substrate 10, the pattern 13 is formed.

다음, 도 1b에서 보는 바와 같이 상기 형성된 패턴을 이용하여 상기 질화막 및 패드 산화막을 식각하여 트렌치(14)를 형성한다.Next, as shown in FIG. 1B, the nitride layer and the pad oxide layer are etched using the formed pattern to form the trench 14.

다음, 도 1c에서 보는 바와 같이 상기 형성된 트렌치에 TEOS(Tetra-ethoxysilane, 이하 TEOS) 산화막과 같은 절연물(15)을 증착하여 트렌치를 충진하는 단계이다.Next, as shown in FIG. 1C, a trench is filled by depositing an insulator 15 such as a TE-oxide (TEOS) oxide film in the formed trench.

다음, 도 1d에서 보는 바와 같이 상기 질화막 및 패드 산화막을 완전히 제거 하여 STI를 완성하는 단계이다.Next, as shown in FIG. 1D, the nitride film and the pad oxide film are completely removed to complete the STI.

다음, 도 1e에서 보는 바와 같이 종래 기술에 의해 형성된 소자 분리막은 이후 공정을 거친후 필드 정지 영역(16)을 형성한 후, 소오스/드레인(17)을 이온 주입 공정으로 형성하게 되면 영역이 서로 가까워지는 현상(18)이 일어난다.Next, as shown in FIG. 1E, after forming the field stop region 16 after the process, the region is close to each other when the source / drain 17 is formed by the ion implantation process. Losing phenomenon 18 occurs.

그러나, 상기와 같은 종래의 소자 분리막 형성 방법은 습식 식각 공정으로 소자 분리막의 산화막이 유실되어 소오스/드레인의 불순물 이온 주입시 소오스/드레인 영역이 필드 정지 영역과 가까워지는 문제점이 있다.However, the conventional method of forming a device isolation layer as described above has a problem in that the oxide film of the device isolation layer is lost by a wet etching process, so that the source / drain region approaches the field stop region when impurity ions are implanted into the source / drain.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 유실된 소자 분리막을 질화막으로 충진하여 소자 분리막의 가장 자리의 산화막이 유실되는 것을 보상하여 소자의 특성을 개선하는 소자 분리막을 형성하는 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by filling a missing device isolation film with a nitride film to compensate for the loss of the oxide film of the edge of the device isolation film to form a device isolation film to improve the characteristics of the device It is an object of the present invention to provide a method.

본 발명의 상기 목적은 소정의 소자가 형성된 기판상에 제1산화막 및 제1질화막을 순차적으로 형성하고, 상기 제1질화막 상부에 패턴을 형성하는 단계; 상기 패턴을 이용하여 제1질화막, 제1산화막 및 기판을 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 제2산화막으로 매립하는 단계; 상기 기판을 제1평탄화하고 습식 식각으로 산화물을 제거하는 단계; 상기 기판상에 제2질화막을 형성하는 단계; 및 상기 기판을 제2평탄화하는 단계를 포함하여 이루어진 소자 분리막 형성 방법에 의해 달성된다.The object of the present invention comprises the steps of sequentially forming a first oxide film and a first nitride film on a substrate on which a predetermined element is formed, and forming a pattern on the first nitride film; Forming a trench by etching the first nitride film, the first oxide film and the substrate using the pattern; Filling the trench with a second oxide film; First planarizing the substrate and removing oxide by wet etching; Forming a second nitride film on the substrate; And second planarizing the substrate.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 내지 도 2c는 본 발명에 의한 소자 분리막 형성 방법의 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a device isolation film according to the present invention.

먼저, 도 2a는 소정의 소자가 형성된 기판상에 제1산화막 및 제1질화막을 순차적으로 형성하고, 상기 제1질화막 상부에 패턴을 형성한 후 상기 패턴을 이용하여 제1질화막, 제1산화막 및 기판을 식각하여 트렌치를 형성하는 단계이다. 도에서 보는 바와 같이 소정의 소자가 형성된 기판(21)상에 제1산화막(22) 및 제1질화막(23)을 순차적으로 형성한다. 이때 상기 제1산화막은 열산화막으로 형성하여 이후 공정에서 기판을 보호하는 패드 산화막으로 형성한다. 상기 제1질화막은 상기 형성된 패턴에 의해 식각되어 하드 마스크의 역할을 하는 패드 질화막으로 이용되기 위해 형성된다. 이어서, 상기 제1질화막 상부에 포토레지스트를 도포하고 노광 및 현상 공정을 진행하여 패턴(24)을 형성한다. 그리고 상기 패턴을 이용하여 상기 제1질화막, 제1산화막 및 기판을 RIE(Reactive Ion Etch, 이하 RIE)로 식각하여 트렌치(25)를 형성한다.First, FIG. 2A illustrates that a first oxide film and a first nitride film are sequentially formed on a substrate on which a predetermined element is formed, a pattern is formed on the first nitride film, and then the first nitride film, the first oxide film, and the like are formed using the pattern. Etching the substrate to form a trench. As shown in the figure, the first oxide film 22 and the first nitride film 23 are sequentially formed on the substrate 21 on which the predetermined elements are formed. In this case, the first oxide film is formed of a thermal oxide film and formed of a pad oxide film protecting the substrate in a subsequent process. The first nitride layer is formed to be etched by the formed pattern to be used as a pad nitride layer serving as a hard mask. Subsequently, a photoresist is coated on the first nitride film, and the exposure and development processes are performed to form the pattern 24. The trench 25 is formed by etching the first nitride layer, the first oxide layer, and the substrate using RIE (reactive ion etching, RIE) using the pattern.

다음, 도 2b는 상기 트렌치를 제2산화막으로 매립하고, 상기 기판을 제1평탄화하고 습식 식각으로 산화물을 제거한 후 상기 기판상에 제2질화막을 형성하고 상 기 기판을 제2평탄화하는 단계이다. 도에서 보는 바와 같이 상기 패턴을 스트립(strip) 공정 및 애싱 공정으로 제거하고, 제2산화막을 HDP-CVD(High Density Plasma-Chemical Vapor Deposition, 이하 HDP-CVD)를 이용하여 상기 트렌치를 매립한다. 이어서 상기 기판을 제1CMP(Chemical Mechanical Polishing, 이하 CMP)을 진행하여 상기 제2산화막의 일부 및 제1질화막을 제거한다. 이때 상기 제1CMP는 제1산화막을 식각 정지막으로 설정하여 평탄화한다. 이어서 상기 기판을 습식 식각으로 기판에 형성된 불필요한 산화물을 제거한다. 이때 소자 분리막상의 제2산화물 일부가 식각되어지는데 특히, 소자 분리막의 가장 자리 부분이 가장 많이 식각된다. 이어서 상기 기판에 제2질화막(26)을 증착한다. 마지막으로 상기 제2질화막을 제2평탄화하여 소자 분리막을 형성한다. 이때 상기 제2평탄화는 제1산화막을 식각 정지막으로 설정하여 평탄화한다.Next, FIG. 2B is a step of filling the trench with a second oxide film, first flattening the substrate, removing oxide by wet etching, and then forming a second nitride film on the substrate and second planarizing the substrate. As shown in the figure, the pattern is removed by a strip process and an ashing process, and the second oxide film is buried in the trench by using HDP-CVD (High Density Plasma-Chemical Vapor Deposition). Subsequently, the substrate is subjected to first chemical mechanical polishing (CMP) to remove a portion of the second oxide film and the first nitride film. In this case, the first CMP is planarized by setting the first oxide layer as an etch stop layer. The substrate is then wet etched to remove unnecessary oxides formed on the substrate. At this time, a part of the second oxide on the device isolation layer is etched. In particular, the edge portion of the device isolation layer is etched most. Subsequently, a second nitride film 26 is deposited on the substrate. Finally, the second nitride film is second planarized to form an isolation layer. In this case, the second planarization is planarized by setting the first oxide layer as an etch stop layer.

다음, 도 2c는 본 발명에 의해 형성된 소자 분리막상에 여러 단계의 이온 주입 공정을 형성한 후의 단면도이다. 도에서 보는 바와 같이 필드 정지 영역(27)이 하부에 형성되고, 상기 필드 정지 영역과 이격되어 소오스/드레인 영역(28)이 형성됨으로써 종래 기술에서 발생하는 소오스/드레인 영역과 필드 정지 영역이 서로 가까워지는 현상이 발생하지 않는다(29). 이는 본 발명에 의해 소자 분리막의 가장 자리 영역을 질화막으로 산화막이 유실된 만큼 보정해 주었기 때문에 소오소/드레인 이온 주입시 정상적인 깊이로 소오스/드레인 영역이 형성되었기 때문이다.Next, FIG. 2C is a cross-sectional view after forming various ion implantation processes on the device isolation film formed by the present invention. As shown in the figure, the field stop region 27 is formed at the lower portion, and the source / drain region 28 is formed to be spaced apart from the field stop region so that the source / drain region and the field stop region generated in the prior art are close to each other. Loss does not occur (29). This is because the source / drain regions are formed at a normal depth during the source / drain ion implantation since the edge region of the device isolation layer is corrected as much as the oxide film is lost to the nitride layer according to the present invention.

상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명 하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those of ordinary skill in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

따라서, 본 발명의 소자 분리막 형성 방법은 소자 분리막에 유실된 산화막을 질화막으로 보정함으로써 소자의 특성을 개선하는 효과가 있다.Therefore, the device isolation film forming method of the present invention has the effect of improving the characteristics of the device by correcting the oxide film lost in the device isolation film with a nitride film.

Claims (4)

소자 분리막 형성 방법에 있어서,In the device isolation film forming method, 소정의 소자가 형성된 기판상에 제1산화막 및 제1질화막을 순차적으로 형성하고, 상기 제1질화막 상부에 패턴을 형성하는 단계;Sequentially forming a first oxide film and a first nitride film on a substrate on which a predetermined element is formed, and forming a pattern on the first nitride film; 상기 패턴을 이용하여 제1질화막, 제1산화막 및 기판을 식각하여 트렌치를 형성하는 단계;Forming a trench by etching the first nitride film, the first oxide film and the substrate using the pattern; 상기 트렌치를 제2산화막으로 매립하는 단계;Filling the trench with a second oxide film; 상기 기판을 제1평탄화로 제2산화막의 일부 및 제1질화막을 제거하고, 습식 식각으로 제1산화막과 제2산화막의 일부를 제거하는 단계;Removing the portion of the second oxide film and the first nitride film by first planarizing the substrate, and removing the portion of the first oxide film and the second oxide film by wet etching; 상기 기판상에 제2질화막을 형성하는 단계; 및Forming a second nitride film on the substrate; And 상기 기판을 제2평탄화하는 단계Second planarizing the substrate 를 포함하여 이루어짐을 특징으로 하는 소자 분리막 형성 방법.Device isolation film forming method comprising a. 제 1항에 있어서,The method of claim 1, 상기 제1산화막은 열산화 공정으로 형성함을 특징으로 하는 소자 분리막 형성 방법.The first oxide film is formed by a thermal oxidation process. 제 1항에 있어서,The method of claim 1, 상기 제2산화막은 HDP-CVD 공정으로 형성함을 특징으로 하는 소자 분리막 형성 방법.And the second oxide film is formed by a HDP-CVD process. 제 1항에 있어서,The method of claim 1, 상기 트렌치를 형성하는 식각은 RIE 공정으로 형성함을 특징으로 하는 소자 분리막 형성 방법.The trench forming the trench is formed by a RIE process.
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