KR100567892B1 - Method for forming low-k isolation layer between metal layers in manufacturing semiconductor device - Google Patents

Method for forming low-k isolation layer between metal layers in manufacturing semiconductor device Download PDF

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KR100567892B1
KR100567892B1 KR1020030099088A KR20030099088A KR100567892B1 KR 100567892 B1 KR100567892 B1 KR 100567892B1 KR 1020030099088 A KR1020030099088 A KR 1020030099088A KR 20030099088 A KR20030099088 A KR 20030099088A KR 100567892 B1 KR100567892 B1 KR 100567892B1
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film
forming
insulating film
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usg
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KR20050068040A (en
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김덕수
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것이다. 즉, 본 발명은 반도체 소자 제조 공정 중 금속배선층간 절연막 형성방법에 있어서, 종래 PECVD 장치를 이용한 저유전율 절연막 형성방법과 달리 HDPCVD 장치를 이용하여 동일챔버에서 In-Situ로 USG1, SiOC, USG2 스택구조의 IMD 절연막을 형성함으로서 Low-k IMD 절연막에 의한 커패시턴스를 낮춰 디바이스의 동작속도를 극대화시킬 수 있다.The present invention relates to a semiconductor device manufacturing method. That is, the present invention, in the method of forming an insulating film between metal wiring layers during the semiconductor device manufacturing process, unlike the conventional low-k dielectric film forming method using a PECVD device, USG1, SiOC, USG2 stack structure with In-Situ in the same chamber using an HDPCVD device By forming the IMD insulating film, the capacitance of the low-k IMD insulating film can be reduced to maximize the operation speed of the device.

Description

반도체 소자 제조시 금속배선층간 저유전율 절연막 형성방법{METHOD FOR FORMING LOW-K ISOLATION LAYER BETWEEN METAL LAYERS IN MANUFACTURING SEMICONDUCTOR DEVICE}METHODS FOR FORMING LOW-K ISOLATION LAYER BETWEEN METAL LAYERS IN MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래 PECVD 장치를 이용한 저유전율 절연막 형성 공정 수순도,1 is a flow chart of a low dielectric constant insulating film formation process using a conventional PECVD apparatus,

도 2a 내지 도 2b는 본 발명의 실시 예에 따른 HDPCVD 장치를 이용한 저유전율 절연막 형성 공정 수순도.2A to 2B are flowcharts of a process of forming a low dielectric constant insulating film using an HDPCVD apparatus according to an exemplary embodiment of the present invention.

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 HDPCVD(High Density Plasma Chemical Vapor Deposition) 장치를 이용하여 금속배선층간 저유전율(Low-k) 절연막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a low dielectric constant (Low-k) insulating film between metal wiring layers using a high density plasma chemical vapor deposition (HDPCVD) apparatus.

도 1은 종래 IMD(Inter Metal Dielectric) 절연막 형성방법을 도시한 공정 수순도로, 상기 도 1을 참조하면, IMD 절연막 형성시에는 금속배선 사이에 HDPCVD 장치를 이용하여 USG1(Undoped Silicate Glass)막(104), FSG(Fluorinated Silicate Glass)막(106), USG2막(108) 그리고 CMP 공정을 위한 캡핑(Capping) 역할의 옥사이드를 스택구조로 형성한다. 상기에서 USG1막과 USG2막는 Fluorine기의 확산을 막기 위한 역할을 수행하며, USG1막의 경우에는 HDPCVD 공정에 있어서 금속 배선의 코너 클립핑(Corner clipping)(배선 에지 식각)을 방지하기 위해 사용되어진다. FIG. 1 is a process flow diagram illustrating a conventional method of forming an intermetal dielectric (IMD) insulating film. Referring to FIG. 1, when an IMD insulating film is formed, a USG1 (Undoped Silicate Glass) film 104 is formed by using an HDPCVD device between metal wirings. ), FSG (Fluorinated Silicate Glass) film 106, USG2 film 108 and oxides of the capping (Capping) for the CMP process to form a stack structure. The USG1 film and the USG2 film serve to prevent diffusion of the fluorine group, and the USG1 film is used to prevent corner clipping (wiring edge etching) of metal wiring in the HDPCVD process.

상기한 바와 같이 종래 PECVD 장치를 이용한 금속배선간 저유전율 형성에서는 갭필링(Gap filling) 능력이 낮아 금속과 금속사이에 저유전율을 갖는 절연막을 형성하기 곤란한 문제점이 있었다.As described above, in the formation of a low dielectric constant between metal wirings using a conventional PECVD apparatus, there is a problem that it is difficult to form an insulating film having a low dielectric constant between the metal and the metal due to its low gap filling ability.

따라서, 본 발명의 목적은 반도체 소자 제조시 HDPCVD 장치를 이용하여 금속배선막간 저유전율 절연막을 형성시키는 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for forming a low dielectric constant insulating film between metal wiring films using an HDPCVD apparatus in manufacturing a semiconductor device.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자 제조시 금속배선층간 저유전율 절연막 형성방법으로서, (a)금속배선막 사이에 HDPCVD 장치를 이용하여 제1USG 막을 증착시키는 단계와, (b)상기 제1USG막 위로 저유전율 절연막인 SiOC막을 증착시키는 단계와, (c)상기 SiOC막을 이용하여 금속배선간 갭필링을 완료한 후, SiOC막 위로 제2USG막을 증착시키는 단계와, (d)상기 제2USG막 위로 IMD 평탄화를 위한 옥사이드막을 증착시킨 후, CMP를 통해 평탄화시키는 단계,를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a method of forming a low dielectric constant insulating film between metal wiring layers in the manufacture of a semiconductor device, (a) depositing a first USG film between the metal wiring film using an HDPCVD apparatus, and (b) Depositing a SiOC film, which is a low dielectric constant insulating film, on the 1USG film, (c) completing a gap filling between the metal wirings using the SiOC film, and then depositing a second USG film on the SiOC film, and (d) the second USG film And depositing an oxide film for IMD planarization, followed by planarization through CMP.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 2a 내지 도 2b는 본 발명의 실시 예에 따른 HDPCVD 장치를 이용한 금속배선층간 저유전율(Low-k) 절연막 형성방법을 도시한 공정 수순도이다. 본 발명에서 는 종래의 PECVD 장치를 이용한 저유전율 절연막 형성방법과 달리 HDPCVD 장치를 이용하여 동일 챔버(Chamber)에서 In-Situ로 USG1, SiOC, USG2를 형성하는 것을 특징으로 한다. 2A to 2B are process flowcharts illustrating a method of forming a low-k dielectric film between metal wiring layers using an HDPCVD apparatus according to an exemplary embodiment of the present invention. In the present invention, unlike the conventional method for forming a low dielectric constant insulating film using a PECVD apparatus, it is characterized in that USG1, SiOC, USG2 is formed by In-Situ in the same chamber (Chamber) using an HDPCVD apparatus.

이하 상기 도 2a, 도 2b를 참조하여 본 발명의 금속배선층간 저유전율 절연막 형성방법을 상세히 설명하기로 한다. Hereinafter, a method of forming a low dielectric constant insulating film between metal wiring layers of the present invention will be described in detail with reference to FIGS. 2A and 2B.

먼저, 상기 도 2a의 USG1막(204)을 형성하는 방법은 HDPCVD 장치의 챔버에서 원료가스로 SiH4, O2, Ar를 이용하여 500∼1000Å 정도의 옥사이드를 형성해준다. 이때 상기 USG1막(204)의 목적은 금속 코너 클립핑(Corner clipping) 방지 및 불순물의 확산을 막는 역할을 수행한다. 상기 USG1막(204)을 형성하는데 있어서 중요한 점은 바이어스(Bias) RF 전원을 사용하지 않고, 단지 소스(Source) RF 전원만을 이용하여 형성하는 것이다.First, the method of forming the USG1 film 204 of FIG. 2A forms an oxide of about 500 to 1000 Pa using SiH 4 , O 2 , and Ar as source gases in a chamber of an HDPCVD apparatus. At this time, the purpose of the USG1 film 204 is to prevent metal corner clipping and prevent diffusion of impurities. An important point in forming the USG1 film 204 is to use only a source RF power source, not a bias RF power source.

이때 바이어스 전원까지 이용하는 경우에는 금속 코너 클리핑 현상을 유발할 수도 있다. 따라서 USG1막(204)을 형성함에 있어 소스 RF 전원은 3000∼4000W정도이며, SiH4, O2, Ar 양은 각각 SiH4 50∼70sccm, O2 100∼150sccm, Ar 100∼150sccm 분위기에서 형성한다.In this case, even a bias power supply may cause metal corner clipping. Accordingly, in forming the USG1 film 204, the source RF power supply is about 3000 to 4000 W, and the SiH 4 , O 2 , and Ar amounts are formed in SiH 4 50 to 70 sccm, O 2 100 to 150 sccm, and Ar 100 to 150 sccm, respectively.

다음으로 저유전율(k<3.0) 절연막인 SiOC(Organic Silicate Glass)막(206)를 형성하기 위해서 USG1막(204) 증착 후 일정시간의 세정(Purge)를 행한 후, 동일 챔버에서 SiH4, Ar, CO2 또는 CO 가스를 이용하거나 SiH4, Ar, O2, CF4 또는 CH4, C2H6 등의 원료가스를 이용하여 SiOC막(206)를 증착한다. Next, in order to form an SiOC (Organic Silicate Glass) film 206 which is a low dielectric constant (k <3.0) insulating film, a purge is performed for a predetermined time after deposition of the USG1 film 204, followed by SiH 4 , Ar in the same chamber. , SiO 2 film 206 is deposited using a source gas such as SiH 4 , Ar, O 2 , CF 4 or CH 4 , C 2 H 6 .

상기 SiOC막(206) 증착시에는 USG1막(204) 형성시와는 달리 바이어스 RF 전원을 이용함으로써, 증착과 에칭을 동시에 행하여 금속 배선층간의 갭필링을 실시한다. 이때 원료 가스로는 SiH4 50∼70sccm, Ar 100∼150sccm, CO2 혹은 CO 가스는 100∼150sccm 정도를 사용하며, 갭필링 능력을 최대로 하기 위해 공정 압력은 5mTorr 내로 한다. 또한 SiOC막(206) 형성 시 소스 RF 전원은 USG1막(204) 형성 시와 비슷하게 3000∼4000W 정도를 사용하고, 바이어스 RF 전원은 2500∼3500W 정도를 사용한다. 이때 바이어스 RF 전원을 사용하는 경우에는 증착 온도가 올라가기 때문에 웨이퍼 뒷면(Wafer backside)에서 헬륨 쿨링(Helium Cooling)을 해준다.In the deposition of the SiOC film 206, unlike the formation of the USG1 film 204, deposition and etching are simultaneously performed by using a bias RF power supply, thereby performing gap filling between metal wiring layers. In this case, SiH 4 50 to 70 sccm, Ar 100 to 150 sccm, CO 2 or CO gas is used at about 100 to 150 sccm, and the process pressure is 5 mTorr to maximize the gap filling capability. In addition, the source RF power source is used at the time of forming the SiOC film 206, about 3000 to 4000W, and the bias RF power source is used at about 2500 to 3500W, similarly to the USG1 film 204. In the case of using a bias RF power source, the deposition temperature is increased, so helium cooling is performed on the wafer backside.

상기와 같이 SiOC막(206)을 이용하여 금속 배선간 갭필이 완료되면 일정시간의 세정 단계를 거친 후, 다음으로 USG2막(208)을 형성한다. 이때는 금속 배선 사이의 갭필링이 완료된 상태이므로 하부의 USG1막(204)과 SiOC막(206) 형성 시보다 더 높은 증착속도(Deposition Rate)로 USG2막(208)을 형성하며, 증착 조건으로는 소스 RF 전원은 4000∼5000W, 바이어스 RF 전원은 1500∼2500W 정도를 사용한다. 원료가스로는 SiH4, O2, Ar 양은 USG1 막 형성시와 비슷한 양을 사용하고 공정압력은 10mTorr 내로 한다.When the gap fill between the metal wires is completed using the SiOC film 206 as described above, the USG 2 film 208 is formed after the cleaning step for a predetermined time. At this time, since the gap filling between the metal wirings is completed, the USG2 film 208 is formed at a higher deposition rate than when the lower USG1 film 204 and the SiOC film 206 are formed. The RF power source uses 4000 to 5000 W and the bias RF power source uses about 1500 to 2500 W. As the source gas, SiH 4 , O 2 , and Ar should be used in amounts similar to those of USG1 film formation.

이어 후속 공정으로 도 2b에서와 같이 IMD 평탄화를 위해 캡핑 역할을 위해 옥사이드를 증착시킨 후 CMP(Chemical-Mechanical Polishing) 기술을 이용하여 평탄화를 수행하게 된다.Subsequently, as a subsequent process, as shown in FIG. 2B, an oxide is deposited for a capping role for IMD planarization, and then planarization is performed using a chemical-mechanical polishing (CMP) technique.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명은 반도체 소자 제조 공정시 금속배선층간 절연막 형성방법에 있어서, 종래 PECVD 장치를 이용한 저유전율 절연막 형성방법과 달리 HDPCVD 장치를 이용하여 동일챔버에서 In-Situ로 USG1, SiOC, USG2 스택구조의 IMD 절연막을 형성함으로서 저유전율 IMD 절연막에 의한 커패시턴스를 낮춰 디바이스의 동작속도를 극대화시킬 수 있는 이점이 있다. As described above, the present invention provides a method for forming an insulating film between metal wiring layers during a semiconductor device manufacturing process, unlike a method of forming a low dielectric constant insulating film using a conventional PECVD device, using a HDPCVD device in the same chamber as In-Situ USG1, SiOC. By forming the IMD insulating film of the USG2 stack structure, the capacitance of the low dielectric constant IMD insulating film can be reduced to maximize the operation speed of the device.

Claims (8)

반도체 소자 제조시 금속배선층간 저유전율 절연막 형성방법으로서,As a method of forming a low dielectric constant insulating film between metal wiring layers in the manufacture of semiconductor devices, (a)금속배선층 사이에 HDPCVD 장치를 이용하여 제1USG 막을 증착시키는 단계와,(a) depositing a first USG film between the metallization layers using an HDPCVD apparatus; (b)상기 제1USG막 위로 저유전율 절연막인 SiOC막을 증착시키는 단계와,(b) depositing a SiOC film, which is a low dielectric constant insulating film, on the first USG film; (c)상기 SiOC막을 이용하여 금속배선간 갭필링을 완료한 후, SiOC막 위로 제2USG막을 증착시키는 단계와,(c) depositing a second USG film on the SiOC film after completing the gap filling between the metal wirings using the SiOC film; (d)상기 제2USG막 위로 IMD 평탄화를 위한 옥사이드막을 증착시킨 후, CMP를 통해 평탄화시키는 단계,(d) depositing an oxide film for IMD planarization on the second USG film and then planarizing it through CMP; 를 포함하는 금속배선층간 저유전율 절연막 형성방법.A method of forming a low dielectric constant insulating film between metal wiring layers comprising a. 제1항에 있어서,The method of claim 1, 상기 제1USG, SiOC, 제2USG막은, 순착적 적층 구조로 형성되며, 동일 챔버에서 In-situ로 형성되는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법. The first USG, SiOC, and second USG films may be formed in a stacked structure and formed in-situ in the same chamber. 제1항에 있어서,The method of claim 1, 상기 (a)단계의 제1USG막은, SiH4, O2, Ar 가스를 이용하여 500∼1000Å 두 께의 옥사이드로 성장시키는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법.The method of forming a low dielectric constant insulating film between metal wiring layers, wherein the first USG film of step (a) is grown to an oxide having a thickness of 500 to 1000 kW using SiH 4 , O 2 , and Ar gas. 제3항에 있어서,The method of claim 3, 상기 제1USG막은, 50∼70sccm의 SiH4, 100∼150sccm의 O2, 100∼150sccm의 Ar 가스가 3000∼4000W의 소스 RF 전원의 챔버내에서 반응되어 형성되는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법.The first USG film is formed by reacting SiH 4 of 50 to 70 sccm, O 2 of 100 to 150 sccm, and Ar gas of 100 to 150 sccm in a chamber of a source RF power source of 3000 to 4000 W. Method of forming an insulating film. 제1항에 있어서,The method of claim 1, 상기 (b)단계의 SiOC막은, 상기 제1USG막 증착 후, 일정시간 세정 후, 동일 챔버에서 SiH4와, Ar와 CO2로 이루어진 혼합가스 또는 SiH4와, Ar와 CO로 이루어진 혼합가스 중 어느 하나를 이용하여 형성되는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법.Of the film of the step (b), SiOC, wherein 1USG film after evaporation, and after a certain period of time cleaning, SiH 4 in the same chamber, a mixed gas consisting of Ar and CO 2, or SiH 4, a mixed gas consisting of Ar and CO which A method of forming a low dielectric constant insulating film between metal wiring layers, characterized in that formed using one. 제5항에 있어서,The method of claim 5, 상기 SiOC막은, 50∼70sccm의 SiH4와, 100∼150sccm의 Ar와, 100∼150sccm의 CO2로 이루어진 혼합가스 또는 50∼70sccm의 SiH4와, 100∼150sccm의 Ar와, 100∼150sccm의 CO로 이루어진 혼합가스 중 어느 하나가 3000∼4000W의 소스 RF 전원과 2500∼3500W의 바이어스 RF 전원의 챔버내에서 반응되어 형성되는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법.The SiOC film, 50~70sccm of SiH 4 and the gas mixture of SiH 4 or 50~70sccm consisting of Ar and CO 2, the 100~150sccm 100~150sccm, with the 100~150sccm Ar, CO 100~150sccm A method of forming a low dielectric constant insulating film between metal wiring layers, wherein any one of a mixed gas is formed by reacting in a chamber of a source RF power source of 3000 to 4000W and a bias RF power source of 2500 to 3500W. 제1항에 있어서,The method of claim 1, 상기 (c)단계의 제2USG막은, SiH4, O2, Ar 가스를 이용하여 500∼1000Å 두께의 옥사이드로 성장시키는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법.The method of forming a low dielectric constant insulating film between metal wiring layers, wherein the second USG film of step (c) is grown to an oxide having a thickness of 500 to 1000 Pa using SiH 4 , O 2 , and Ar gas. 제7항에 있어서,The method of claim 7, wherein 상기 제2USG막은, 50∼70sccm의 SiH4, 100∼150sccm의 O2, 100∼150sccm의 Ar 가스가 3000∼4000W의 소스 RF 전원의 챔버내에서 반응되어 형성되는 것을 특징으로 하는 금속배선층간 저유전율 절연막 형성방법.The second USG film is formed by reacting 50 to 70 sccm of SiH 4 , 100 to 150 sccm of O 2 , and 100 to 150 sccm of Ar gas in a chamber of a source RF power source of 3000 to 4000 W. Method of forming an insulating film.
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US11189572B2 (en) 2018-07-17 2021-11-30 Samsung Electronics Co., Ltd. Maintaining height of alignment key in semiconductor devices

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