KR100567129B1 - 반도체 패키지 제조용 몰딩 금형 및 이것을 이용한 반도체패키지 몰딩방법 - Google Patents
반도체 패키지 제조용 몰딩 금형 및 이것을 이용한 반도체패키지 몰딩방법 Download PDFInfo
- Publication number
- KR100567129B1 KR100567129B1 KR1020010019951A KR20010019951A KR100567129B1 KR 100567129 B1 KR100567129 B1 KR 100567129B1 KR 1020010019951 A KR1020010019951 A KR 1020010019951A KR 20010019951 A KR20010019951 A KR 20010019951A KR 100567129 B1 KR100567129 B1 KR 100567129B1
- Authority
- KR
- South Korea
- Prior art keywords
- mounting plate
- chip mounting
- molding
- semiconductor package
- mold
- Prior art date
Links
- 238000000465 moulding Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000011347 resin Substances 0.000 claims abstract description 27
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 238000003825 pressing Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000007747 plating Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000011536 re-plating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (4)
- 소정 체적 공간의 캐비티가 저면에 형성된 구조의 상형과, 평평한 표면으로 형성된 구조의 하형으로 구성된 반도체 패키지 제조용 몰딩금형에 있어서,상기 하형의 표면에 리드프레임의 칩탑재판 저면과 접촉되는 면적에 걸쳐서 돌출부를 일체로 형성한 것을 특징으로 하는 반도체 패키지 제조용 몰딩 금형.
- 제 1 항에 있어서, 상기 돌출부의 돌출 높이는 2mil 이하 인 것을 특징으로 하는 반도체 패키지 제조용 몰딩 금형.
- 캐비티가 저면에 형성된 구조의 상형과, 표면에 돌출부가 형성된 구조의 하형으로 구성된 반도체 패키지 제조용 몰딩금형을 제공하는 단계와;상기 하형의 표면에 반도체 칩 부착공정과 와이어 본딩 공정을 마친 리드프레임의 칩탑재판을 올려 놓는 동시에 칩탑재판의 저면이 상기 하형의 돌출부에 밀착되게 하는 단계와;상기 상형을 하형과 클램핑되도록 하방향으로 이동시켜, 상기 리드프레임의 각 외부리드와 타이바가 상기 상형과 하형 사이에 물리면서 클램핑되도록 한 단계와;상기 상형과 하형간의 클램핑과 함께 상기 하형의 돌출부에 의하여 칩탑재판의 저면이 위쪽으로 들어 올려지는 동시에 일체로 연결되어 있는 타이바가 칩탑재판쪽을 향하여 상향으로 경사지며 위치되는 단계와;상기 상형의 캐비티로 몰딩수지를 소정의 압으로 공급하여, 상기 반도체 칩이 실장된 칩탑재판과, 와이어와, 각 인너리드가 몰딩되도록 한 단계로 이루어진 것을 특징으로 하는 반도체 패키지 몰딩 방법.
- 제 3 항에 있어서, 상기 칩탑재판과 평행한 위치로 있던 타이바가 상향으로 경사지게 되면서, 본래의 평행한 위치로 돌아가려는 탄성복원력을 갖게 되고, 이 타이바의 탄성복원력은 상기 칩탑재판을 밑으로 누르는 힘으로 작용되어, 칩탑재판의 저면이 상기 돌출부에 더 밀착되는 것을 특징으로 하는 반도체 패키지 몰딩 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010019951A KR100567129B1 (ko) | 2001-04-13 | 2001-04-13 | 반도체 패키지 제조용 몰딩 금형 및 이것을 이용한 반도체패키지 몰딩방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010019951A KR100567129B1 (ko) | 2001-04-13 | 2001-04-13 | 반도체 패키지 제조용 몰딩 금형 및 이것을 이용한 반도체패키지 몰딩방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020079211A KR20020079211A (ko) | 2002-10-19 |
KR100567129B1 true KR100567129B1 (ko) | 2006-03-31 |
Family
ID=27701083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010019951A KR100567129B1 (ko) | 2001-04-13 | 2001-04-13 | 반도체 패키지 제조용 몰딩 금형 및 이것을 이용한 반도체패키지 몰딩방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100567129B1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100657159B1 (ko) * | 2005-04-25 | 2006-12-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조용 몰드 구조 |
KR101674537B1 (ko) * | 2010-07-23 | 2016-11-09 | 해성디에스 주식회사 | 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5577160A (en) * | 1978-12-07 | 1980-06-10 | Nec Corp | Semiconductor device |
JPS6155946A (ja) * | 1984-08-27 | 1986-03-20 | Hitachi Chem Co Ltd | 半導体類のパツケ−ジ構造 |
JPH1084055A (ja) * | 1996-09-06 | 1998-03-31 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JPH10326800A (ja) * | 1997-05-26 | 1998-12-08 | Seiko Epson Corp | 半導体装置の製造方法及び半導体製造装置用金型 |
-
2001
- 2001-04-13 KR KR1020010019951A patent/KR100567129B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5577160A (en) * | 1978-12-07 | 1980-06-10 | Nec Corp | Semiconductor device |
JPS6155946A (ja) * | 1984-08-27 | 1986-03-20 | Hitachi Chem Co Ltd | 半導体類のパツケ−ジ構造 |
JPH1084055A (ja) * | 1996-09-06 | 1998-03-31 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JPH10326800A (ja) * | 1997-05-26 | 1998-12-08 | Seiko Epson Corp | 半導体装置の製造方法及び半導体製造装置用金型 |
Also Published As
Publication number | Publication date |
---|---|
KR20020079211A (ko) | 2002-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6812063B2 (en) | Semiconductor package and fabricating method thereof | |
KR100350759B1 (ko) | 볼 그리드 어레이형 반도체 장치 및 그 제조 방법 | |
KR101131353B1 (ko) | 반도체 장치 | |
KR100190981B1 (ko) | 편면수지 봉지형 반도체장치의 제조방법 및 이에 사용되는 캐리어 프레임 | |
CN100517682C (zh) | 半导体器件及其制造方法 | |
US7456049B2 (en) | Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same | |
US20030030131A1 (en) | Semiconductor package apparatus and method | |
JP3170199B2 (ja) | 半導体装置及びその製造方法及び基板フレーム | |
WO2007067998A2 (en) | Device and method for assembling a top and bottom exposed packaged semiconductor | |
US6686652B1 (en) | Locking lead tips and die attach pad for a leadless package apparatus and method | |
JPH11191561A (ja) | 半導体装置の製造方法 | |
US7354804B2 (en) | Method for fabricating lead frame and method of fabricating semiconductor device using the same | |
KR100567129B1 (ko) | 반도체 패키지 제조용 몰딩 금형 및 이것을 이용한 반도체패키지 몰딩방법 | |
JP2001035961A (ja) | 半導体装置及びその製造方法 | |
JPH11176856A (ja) | 半導体装置の製造方法 | |
JP2002151531A (ja) | 半導体装置の製造方法 | |
KR20020093250A (ko) | 리드 노출형 리드 프레임 및 그를 이용한 리드 노출형반도체 패키지 | |
JP2018056310A (ja) | 樹脂封止金型およびそれを用いた半導体装置の製造方法 | |
JP3127104B2 (ja) | 樹脂封止型半導体装置の封止用金型およびこれを用いた製造方法 | |
KR100244721B1 (ko) | 반도체패키지 | |
JP2002050646A (ja) | 半導体装置の製造方法 | |
KR100196289B1 (ko) | Mcp (multi chip package) 본딩장치 | |
KR100418512B1 (ko) | 반도체 팩키지 몰딩용 금형 및 그 금형의 사용 방법 | |
KR100239708B1 (ko) | 비엘피 패키지의 제조방법 | |
KR100534171B1 (ko) | 반도체 패키지의 와이어 본딩용 클램프 구조 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130305 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20140304 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20150303 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20160303 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20180313 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20190313 Year of fee payment: 14 |