KR100557216B1 - The Manufacturing Method for Oxide-Nitride-Oxide layers of flash memory device - Google Patents
The Manufacturing Method for Oxide-Nitride-Oxide layers of flash memory device Download PDFInfo
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- KR100557216B1 KR100557216B1 KR1020030100677A KR20030100677A KR100557216B1 KR 100557216 B1 KR100557216 B1 KR 100557216B1 KR 1020030100677 A KR1020030100677 A KR 1020030100677A KR 20030100677 A KR20030100677 A KR 20030100677A KR 100557216 B1 KR100557216 B1 KR 100557216B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 238000011065 in-situ storage Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 17
- 238000011066 ex-situ storage Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
본 발명은 플래쉬 메모리의 소자의 ONO층을 형성하기 위한 반도체 소자의 제조방법에 관한 것으로, 반도체 기판 상에 제 1산화막 및 질화막을 인시튜 공정으로 형성하는 단계와, 상기 질화막 상에 제 2산화막을 형성하는 단계를 포함하여 이루어져, ONO층의 형성에 따른 공정시간을 대폭 단축시키고, 비용 및 인력을 절감할 수 있으며 핫 케리어 주입특성을 향상시킬 수 있는 것이다. The present invention relates to a method of manufacturing a semiconductor device for forming an ONO layer of a device of a flash memory, comprising the steps of forming a first oxide film and a nitride film on an in-situ process on a semiconductor substrate, and forming a second oxide film on the nitride film. Including the step of forming, it is possible to significantly shorten the process time according to the formation of the ONO layer, to reduce the cost and manpower, and to improve the hot carrier injection characteristics.
반도체, 소자, 플래쉬 메모리, ONO, 산화막, 질화막, 인시튜, 화학기상증착Semiconductor, Device, Flash Memory, ONO, Oxide, Nitride, In-situ, Chemical Vapor Deposition
Description
도 1a 내지 1c는 종래의 반도체 소자의 ONO층 제조방법을 설명하기 위한 공정 단면도1A to 1C are cross-sectional views illustrating a method of manufacturing an ONO layer of a conventional semiconductor device.
도 2a 및 2b는 본 발명의 반도체 소자의 ONO층 제조방법을 설명하기 위한 공정 단면도2A and 2B are cross-sectional views illustrating a method of manufacturing an ONO layer of a semiconductor device of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
30 : 반도체 기판 40 : ONO층30
42 : 제 1산화막 44 : 질화막42: first oxide film 44: nitride film
46 : 제 2산화막 46: second oxide film
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체 소자의 ONO층을 제조함에 있어서 산화막과 질화막을 인시튜 공정으로 형성하여 공정시간을 단축시키고 비용을 절감할 수 있도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE
반도체 소자 중 플래쉬 메모리 소자는 전원이 공급되지 않더라도 그 메모리 셀에 저장되어 있는 정보를 유지할 뿐만 아니라, 회로기판에 장착되어 있는 상태로 고속의 전기적 소거가 가능한 비휘발성(non-volatile) 메모리 소자이다. Among the semiconductor devices, a flash memory device is a non-volatile memory device that not only maintains information stored in the memory cell even when power is supplied, but also enables high-speed electrical erasure while being mounted on a circuit board.
공정기술 측면에서 볼 때 비휘발성 메모리 소자는 크게 플로팅 게이트(floating gate) 계열과 두 종류 이상의 유전막이 2중, 3중으로 적층된 MIS(Metal-Insulator-Semiconductor) 계열로 구분된다.In terms of process technology, nonvolatile memory devices are largely divided into floating gate series and metal-insulator-semiconductor (MIS) series in which two or more dielectric layers are stacked in double or triple layers.
상기 플로팅 게이트 계열의 비휘발성 메모리 소자는 전위 우물(potential well)을 이용하여 메모리 특성을 구현하며, 현재 플래쉬 EEPROM(Electrically Erasable & Programmable Read Only Memory)으로 가장 널리 응용되고 있다.The floating gate-based nonvolatile memory device implements memory characteristics by using potential wells, and is widely used as a flash electrically erasable & programmable read only memory (EEPROM).
상기 플래쉬 EEPROM은 플로팅 게이트와 콘트롤 게이트와의 사이에는 ONO(Oxide-Nitride-Oxide) 구조를 가지는 층간 절연막이 통상적으로 채용되고 있는데, 종래에 반도체 기판 상에 ONO(Oxide-Nitride-Oxide)층을 형성하는 과정은 다음과 같았다. In the flash EEPROM, an interlayer insulating film having an oxide-nitride-oxide (ONO) structure is generally employed between the floating gate and the control gate. An oxide-nitride-oxide (ONO) layer is conventionally formed on a semiconductor substrate. The process was as follows.
먼저, 도 1a에 도시된 바와 같이, 실리콘 재질의 반도체 기판(10)을 열산화장치 내에서 O2나 H2O 분위기로 가열하여 기판 상면에 SiO2의 제 1산화막(22)을 형성시킨다. First, as shown in FIG. 1A, a silicon
이후, 제 1산화막(22)이 형성된 반도체 기판을 엑스시튜(Ex-situ) 공정으로 저압 화학기상증착(LPCVD : Low Pressure Chemical Vapor Deposition) 반응로에서 반응시켜, 도 1b에 도시된 바와 같이, 제 1산화막(22)의 상측에 Si3N4의 질화막(24)을 형성시킨다. Thereafter, the semiconductor substrate on which the
그런 후, 다시 엑스시튜(Ex-situ) 공정으로 상기 질화막(24)의 상측에 도 1c에 도시된 바와 같이, 제 2산화막(26)을 형성하여 전체적인 ONO층(20)을 형성하게 된다. Then, as shown in FIG. 1C, the
그런데, 이와 같은 종래의 ONO층(20) 제조방법은 엑스시튜 공정으로 제 1산화막(22) 및 질화막(24), 제 2산화막(26)이 형성되므로, 공정시간이 과다하게 소요되었고 이는 작업공수 발생 비용증가의 문제가 되었다. However, in the conventional method of manufacturing the
이에 본 발명은 상술한 종래의 제반 문제점을 감안하여 발명된 것으로서, 반도체 기판의 상면에 ONO층 제조시 인시튜 공정으로 산화막과 질화막을 형성함으로써 공정시간을 단축하고 비용을 절감할 수 있도록 한 반도체 소자의 제조방법을 제공함에 발명의 목적이 있다.
Accordingly, the present invention has been made in view of the above-mentioned conventional problems, and is a semiconductor device in which an oxide film and a nitride film are formed on an upper surface of a semiconductor substrate in an in-situ process during fabrication of an ONO layer, thereby shortening process time and reducing costs. An object of the invention to provide a method for producing.
상기의 목적을 달성하기 위한 본 발명은 플래쉬 메모리 소자의 ONO층 제조에 있어서, 반도체 기판 상에 제 1산화막 및 질화막을 인시튜 공정으로 형성하는 단계와, 상기 질화막 상에 제 2산화막을 형성하는 단계를 포함하여 이루어지는 것을 기술적 특징으로 한다. According to an aspect of the present invention, there is provided a method of fabricating an ONO layer of a flash memory device, the method including forming a first oxide film and a nitride film on an in-situ process on a semiconductor substrate, and forming a second oxide film on the nitride film. It is made to include a technical feature.
상기 제 2산화막은 제 1산화막 및 질화막과 함께 인시튜 공정으로 형성하는 것을 특징으로 한다. The second oxide film is formed in an in-situ process together with the first oxide film and the nitride film.
상기 제 1산화막 및 질화막은 저압 화학기상증착 공정을 이용하여 형성하는 것을 특징으로 한다. The first oxide film and the nitride film is formed using a low pressure chemical vapor deposition process.
상기 저압 화학기상증착 공정은 100∼1000 밀리토르 압력하에서, O2가스를 102∼105 sccm 공급한 상태로, 500∼900℃내에서 진행하는 것을 특징으로 한다. The low-pressure chemical vapor deposition process is characterized in that it proceeds within 500 ~ 900 ℃, supplied with 10 2 ~ 10 5 sccm of O 2 gas under 100 to 1000 millitorr pressure.
이하, 본 발명의 바람직한 실시예를 첨부된 예시도면에 의거 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 플래쉬 메모리 소자의 ONO층 제조에 있어서, 우선 도 2a에 도시된 바와 같이, 반도체 기판(30) 상에 제 1산화막(42) 및 질화막(44)을 인시튜 공정으로 형성하며, 바람직하게 저압 화학기상증착 공정을 이용한다. In the present invention, in the fabrication of an ONO layer of a flash memory device, first, as shown in FIG. 2A, a
즉, 제 1산화막(42)과 질화막(44)을 동일한 저압 화학기상증착 공정에서 형성함으로써 공정시간을 단축시키고, 전체적인 ONO층(40)을 통한 안정적인 핫 케리어 주입(Hot Carrier Injection) 특성도 향상시킬 수 있다. That is, by forming the
여기에서, 상기 저압 화학기상증착 공정은 바람직하게 100∼1000 밀리토르 압력하에서, O2가스를 102∼105 sccm 공급한 상태로, 500∼900℃내에서 진행하도록 한다. Here, the low-pressure chemical vapor deposition step is preferably carried out within 500 ~ 900 ℃, supplied with 10 2 ~ 10 5 sccm of O 2 gas under a pressure of 100 ~ 1000 millitorr.
그리고, 상기 제 1산화막(42) 및 질화막(44)의 형성후 도 2b에 도시된 바와 같이, 상기 질화막(44) 상에 제 2산화막(46)을 형성하는데, 제 2산화막(46)도 제 1산화막(42) 및 질화막(44)과 함께 인시튜 공정으로 형성할 수 있다. After the formation of the
따라서, 본 발명의 ONO층(40)을 모두 하나의 인시튜 공정으로 진행함으로써 공정수율을 대폭 향상시킬 수 있게 된다. Therefore, the process yield can be greatly improved by advancing the
이상에서 살펴본 바와 같이 본 발명은 반도체 소자의 ONO층 제조시 인시튜 공정으로 진행함으로써 공정시간을 단축시키고, 비용 및 인력절감의 효과가 있다.
As described above, the present invention shortens the process time by reducing the process time and reduces the manpower by proceeding to an in-situ process when manufacturing an ONO layer of a semiconductor device.
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