KR100532939B1 - Method for forming substrate of semiconductor device - Google Patents

Method for forming substrate of semiconductor device Download PDF

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Publication number
KR100532939B1
KR100532939B1 KR10-1999-0041807A KR19990041807A KR100532939B1 KR 100532939 B1 KR100532939 B1 KR 100532939B1 KR 19990041807 A KR19990041807 A KR 19990041807A KR 100532939 B1 KR100532939 B1 KR 100532939B1
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substrate
oxide film
heat treatment
forming
semiconductor device
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KR10-1999-0041807A
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Korean (ko)
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KR20010029152A (en
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정연우
최조봉
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H01L21/02472—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 기판 형성방법에 관한 것으로, 종래에는 결함이 최소화된 기판을 준비하기 위한 공정이 복잡하고, Dz 열처리를 통해 형성된 산화막을 제거하게 되면, 줄무늬 파티클이 다량 발생하여 공정진행 및 소자특성에 영향을 미치는 문제점이 있었다. 따라서, 본 발명은 반도체기판 상에 Dz 열처리 전세정을 실시하는 공정과; 상기 세정이 실시된 기판 상에 동일한 온도에서 산소의 양이 다르게 1차 및 2차 Dz 열처리를 실시하여 로코스 진행을 위한 산화막을 형성하는 공정과; 상기 산화막 상에 로코스 질화막을 증착하는 공정으로 이루어지는 반도체소자의 기판 형성방법을 제공함으로써, 반도체기판의 결함제거 및 로코스를 진행하기 위한 산화막 형성이 동시에 이루어짐에 따라 공정을 단순화하여 비용을 절감할 수 있으며, 종래에 Dz 열처리를 통해 형성된 산화막 제거를 생략함에 따라 산화막의 제거로 인한 줄무늬 파티클 발생을 방지할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a substrate of a semiconductor device. In the related art, a process for preparing a substrate with minimal defects is complicated, and when an oxide film formed through Dz heat treatment is removed, a large amount of streaked particles are generated to process and process a device. There was a problem affecting the properties. Accordingly, the present invention provides a method of pre-cleaning Dz heat treatment on a semiconductor substrate; Forming an oxide film for locos by performing first and second Dz heat treatments having different amounts of oxygen at the same temperature on the cleaned substrate; By providing a method of forming a substrate of a semiconductor device comprising a step of depositing a locos nitride film on the oxide film, as the oxide film is formed to remove the defects of the semiconductor substrate and proceed with the LOCOS at the same time, the process can be simplified to reduce costs In addition, since the removal of the oxide film formed through the Dz heat treatment has been conventionally performed, there is an effect of preventing the generation of streaked particles due to the removal of the oxide film.

Description

반도체소자의 기판 형성방법{METHOD FOR FORMING SUBSTRATE OF SEMICONDUCTOR DEVICE}Substrate Formation Method of Semiconductor Device {METHOD FOR FORMING SUBSTRATE OF SEMICONDUCTOR DEVICE}

본 발명은 반도체소자의 기판 형성방법에 관한 것으로, 특히 고집적화에 따른 기판의 결함을 최소화함과 아울러 소자를 형성하기 위한 기판 준비를 단순화하기에 적당하도록 한 반도체소자의 기판 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a substrate of a semiconductor device, and more particularly, to a method of forming a substrate of a semiconductor device, which is suitable for minimizing defects of a substrate due to high integration and simplifying substrate preparation for forming a device.

최근 들어, 반도체소자의 고집적화 추세로 인해 소스/드레인의 접합깊이가 얕아지게 되었다. 따라서, 소스/드레인 내에 주입된 불순물이온의 확산을 최소화하기 위해서 소자 제조의 전반적인 열처리 온도가 크게 감소하게 되었으며, 또한 기판의 결함이 소자의 특성에 치명적인 영향을 끼치는 요인이 되고 있다. 이와같은 종래 기판결함을 최소화하기 위한 반도체소자의 기판 형성방법을 첨부한 도1a 내지 도1f의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.Recently, due to the high integration of semiconductor devices, the source / drain junction depth has become shallow. Therefore, in order to minimize the diffusion of impurity ions implanted in the source / drain, the overall heat treatment temperature of the device fabrication is greatly reduced, and defects in the substrate become a critical factor in the device characteristics. This will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1F attached to a method of forming a substrate of a semiconductor device to minimize such a conventional substrate defect.

먼저, 도1a에 도시한 바와같이 저항 9∼12[Ω/cm]인 피형 기판(1)에 디뉴디드 존(denuded zone, 이하 Dz로 약칭함) 열처리 전세정을 통해 30Å 정도의 표면을 식각하여 표면의 이물질을 제거한다. 이때, 전세정은 u + 99HF로 60초간 실시한다.First, as shown in FIG. 1A, a surface of about 30 ms is etched through a pre-cleaned heat treatment in a denuded zone (hereinafter abbreviated as Dz) on the substrate 1 having resistances of 9 to 12 [mW / cm]. Remove foreign substances on the surface. At this time, pre-cleaning is performed for 60 seconds at u + 99HF.

그리고, 도1b에 도시한 바와같이 상기 세정이 실시된 기판(1) 상에 Dz 열처리를 진행하여 240Å 정도의 두께로 산화막(2)을 형성한다. 이때, 열처리 조건은 700℃, 1% O2 ----> 1200℃, 1% O2 로 60분간 진행한다.As shown in FIG. 1B, the Dz heat treatment is performed on the cleaned substrate 1 to form an oxide film 2 having a thickness of about 240 kPa. At this time, the heat treatment conditions are carried out at 700 ℃, 1% O 2 ----> 1200 ℃, 1% O 2 60 minutes.

그리고, 도1c에 도시한 바와같이 상기 산화막(2)이 형성된 기판(1)에 Dz 열처리 후세정을 통해 300Å 정도의 표면을 식각하여 산화막(2)을 제거한다. 이때, 후세정은 u + 99HF로 600초간 실시한다.As illustrated in FIG. 1C, the surface of the substrate 1 on which the oxide film 2 is formed is etched by Dz heat treatment post-cleaning to remove 300 nm of the surface, thereby removing the oxide film 2. At this time, the post-cleaning is performed for 600 seconds at u + 99HF.

그리고, 도1d에 도시한 바와같이 상기 산화막(2)이 제거된 기판(1)에 로코스(LOCOS) 진행 전세정을 통해 10Å 정도의 표면을 식각한다. 이때, 전세정은 u + 99HF로 20초간 실시한다.As shown in FIG. 1D, the surface of the substrate 1 from which the oxide film 2 has been removed is etched by about 10 μs through pre-cleaning of LOCOS. At this time, pre-cleaning is performed for 20 seconds at u + 99HF.

그리고, 도1e에 도시한 바와같이 상기 세정이 실시된 기판(1) 상에 로코스 산화를 실시하여 100Å 정도의 두께로 산화막(3)을 형성한다. 이때, 열처리 조건은 700℃, 1% O2 ----> 800℃, wet ---> 750℃, 1% O2 로 진행한다.Then, as shown in Fig. 1E, LOCOS oxidation is performed on the cleaned substrate 1 to form an oxide film 3 having a thickness of about 100 GPa. At this time, the heat treatment conditions proceed to 700 ℃, 1% O 2 ----> 800 ℃, wet ---> 750 ℃, 1% O 2 .

그리고, 도1f에 도시한 바와같이 상기 산화막(3)의 상부에 로코스 질화막(4)을 1450Å 정도의 두께로 증착한다.Then, as shown in Fig. 1F, a locos nitride film 4 is deposited on the oxide film 3 to a thickness of about 1450 1.

그러나, 상기한 바와같은 종래 반도체소자의 기판 형성방법은 결함이 최소화된 기판을 준비하기 위한 공정이 복잡하고, Dz 열처리를 통해 형성된 산화막을 제거하게 되면, 줄무늬 파티클(particle)이 다량 발생하여 공정진행 및 소자특성에 영향을 미치는 문제점이 있었다.However, the method of forming a substrate of a conventional semiconductor device as described above is complicated to prepare a substrate with minimal defects, and when the oxide film formed through Dz heat treatment is removed, a large amount of streaked particles are generated to proceed the process. And there was a problem affecting the device characteristics.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 결함이 최소화된 기판을 준비하기 위한 공정을 단순화함과 아울러 줄무늬 파티클의 발생을 방지할 수 있는 반도체소자의 기판 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a semiconductor device capable of simplifying a process for preparing a substrate with minimized defects and preventing generation of striped particles. It is to provide a method of forming a substrate.

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 기판 형성방법은 반도체기판 상에 Dz 열처리 전세정을 실시하는 공정과; 상기 세정이 실시된 기판 상에 동일한 온도에서 산소의 양이 다르게 1차 및 2차 Dz 열처리를 실시하여 로코스 진행을 위한 산화막을 형성하는 공정과; 상기 산화막 상에 로코스 질화막을 증착하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A method of forming a substrate of a semiconductor device for achieving the object of the present invention as described above comprises the steps of performing Dz heat treatment pre-cleaning on a semiconductor substrate; Forming an oxide film for locos by performing first and second Dz heat treatments having different amounts of oxygen at the same temperature on the cleaned substrate; And depositing a locos nitride film on the oxide film.

상기한 바와같은 본 발명에 의한 반도체소자의 기판 형성방법을 첨부한 도2a 내지 도2c의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 2a to 2c with the method of forming a substrate of the semiconductor device according to the present invention as described above in detail as an embodiment as follows.

먼저, 도2a에 도시한 바와같이 저항 9∼12[Ω/cm]인 피형 기판(11)에 Dz 열처리 전세정을 통해 30Å 정도의 표면을 식각하여 표면의 이물질을 제거한다. 이때, 전세정은 u + 99HF로 60초간 실시한다.First, as shown in FIG. 2A, the surface of about 30 kV is etched through the Dz heat treatment pre-cleaning to the substrate 11 having a resistance of 9 to 12 [mm / cm] to remove foreign substances on the surface. At this time, pre-cleaning is performed for 60 seconds at u + 99HF.

그리고, 도2b에 도시한 바와같이 상기 세정이 실시된 기판(11) 상에 1100℃, 1% O2 로 60분간 1차 Dz 열처리를 진행한 다음 1100℃, 0.02% O2 로 45분간 2차 Dz 열처리를 진행하여 로코스를 진행하기 위한 100Å 정도의 두께로 산화막(12)을 형성한다.Then, as shown in FIG. 2B, a first Dz heat treatment was performed on the cleaned substrate 11 at 1100 ° C. and 1% O 2 for 60 minutes, and then secondary for 45 minutes at 1100 ° C. and 0.02% O 2 . The oxide film 12 is formed to a thickness of about 100 GPa for the process of performing DZ heat treatment.

그리고, 도2c에 도시한 바와같이 상기 산화막(12)의 상부에 로코스 질화막(13)을 1450Å 정도의 두께로 증착한다.As shown in FIG. 2C, the LOCOS nitride film 13 is deposited on the oxide film 12 to a thickness of about 1450 GPa.

상기한 바와같은 본 발명에 의한 반도체소자의 기판 형성방법은 반도체기판의 결함제거 및 로코스를 진행하기 위한 산화막 형성이 동시에 이루어짐에 따라 공정을 단순화하여 비용을 절감할 수 있으며, 종래에 Dz 열처리를 통해 형성된 산화막 제거를 생략함에 따라 산화막의 제거로 인한 줄무늬 파티클 발생을 방지할 수 있는 효과가 있다.In the method of forming a substrate of a semiconductor device according to the present invention as described above, as the oxide film is formed at the same time to remove the defects of the semiconductor substrate and proceed with the LOCOS, the process can be simplified and the cost can be reduced. By omitting the removal of the oxide film formed through, there is an effect that can prevent the generation of stripes particles due to removal of the oxide film.

도1a 내지 도1f는 종래 반도체소자의 기판 형성방법을 보인 수순단면도.1A to 1F are cross-sectional views showing a method of forming a substrate of a conventional semiconductor device.

도2a 내지 도2c는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2c is a cross-sectional view showing the embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

11:반도체기판 12:산화막11: semiconductor substrate 12: oxide film

13:질화막13: nitride film

Claims (3)

반도체기판 상에 Dz 열처리 전세정을 실시하는 공정과; 상기 세정이 실시된 기판 상에 동일한 온도에서 산소의 양이 다르게 1차 및 2차 Dz 열처리를 실시하여 로코스 진행을 위한 산화막을 형성하는 공정과; 상기 산화막 상에 로코스 질화막을 증착하는 공정을 구비하여 이루어지는 것을 특징으로 하는 반도체소자의 기판 형성방법.Performing pre-cleaning of the Dz heat treatment on the semiconductor substrate; Forming an oxide film for locos by performing first and second Dz heat treatments having different amounts of oxygen at the same temperature on the cleaned substrate; And depositing a locos nitride film on said oxide film. 제 1 항에 있어서, 상기 1차 열처리는 1100℃, 1% O2 로 60분간 실시하는 것을 특징으로 하는 반도체소자의 기판 형성방법.The method of claim 1, wherein the first heat treatment is performed at 1100 ° C. and 1% O 2 for 60 minutes. 제 1 항에 있어서, 상기 2차 열처리는 1100℃, 0.02% O2 로 45분간 실시하는 것을 특징으로 하는 반도체소자의 기판 형성방법.The method of claim 1, wherein the secondary heat treatment is performed at 1100 ° C. and 0.02% O 2 for 45 minutes.
KR10-1999-0041807A 1999-09-29 1999-09-29 Method for forming substrate of semiconductor device KR100532939B1 (en)

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