KR100529382B1 - A method for forming metal wire in semicondutor device - Google Patents
A method for forming metal wire in semicondutor device Download PDFInfo
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- KR100529382B1 KR100529382B1 KR10-1999-0062182A KR19990062182A KR100529382B1 KR 100529382 B1 KR100529382 B1 KR 100529382B1 KR 19990062182 A KR19990062182 A KR 19990062182A KR 100529382 B1 KR100529382 B1 KR 100529382B1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 33
- 239000002184 metal Substances 0.000 title claims abstract description 31
- 229910008484 TiSi Inorganic materials 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 claims description 3
- 239000008096 xylene Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 239000010936 titanium Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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Abstract
본 발명은 장벽금속의 층덮힘성과 확산방지력을 개선할 수 있는 반도체 소자의 금속배선 형성방법을 제공하는 데 그 목적이 있다. 상기 목적을 달성하기 위한 본 발명은, 반도체 소자의 금속배선 형성방법에 있어서, 금속 콘택이 형성될 부분의 실리콘기판이 노출되도록 오픈부를 갖는 층간절연막을 형성하는 제1 단계; 상기 제 1단계가 완료된 결과물의 상부에 TiSix(0.1〈 X〈 2.0)막을 형성하는 제 2단계;상기 TiSix(0.1〈 X〈 2.0)막 상부에 TiSiyN1-y(0.01〈 y〈 0.9)막을 형성하는 제 3단계; 열처리를 실시하여 상기 TiSix(0.1〈 X〈 2.0)막을 결정화하는 제5 단계; 상기 제4 단계가 완료된 결과물의 상부에 배선용 금속막을 형성하는 제4 단계를 포함하여 이루어진다.An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can improve the layer covering and diffusion preventing power of the barrier metal. According to an aspect of the present invention, there is provided a method for forming a metal wiring of a semiconductor device, the method comprising: forming an interlayer insulating film having an open portion to expose a silicon substrate of a portion where a metal contact is to be formed; A second step of forming a TiSi x (0.1 <X <2.0) film on the top of the result of the first step is completed; TiSi y N 1-y (0.01 <y <) on the TiSi x (0.1 <X <2.0) film 0.9) a third step of forming a film; A fifth step of crystallizing the TiSi x (0.1 <X <2.0) film by performing heat treatment; And a fourth step of forming a wiring metal film on the finished product of the fourth step.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 소자 제조공정 중 금속배선 형성공정에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a metal wiring forming process in a semiconductor device manufacturing process.
일반적인 금속배선 공정시 금속 원소가 하부의 실리콘 기판 등으로 확산되는 것을 방지하기 위하여 Ti 및 TiN막을 장벽금속막으로 사용하고 있다.In the general metallization process, Ti and TiN films are used as barrier metal films to prevent metal elements from diffusing to the lower silicon substrates.
종래의 일반적인 금속배선 공정을 간략히 살펴보면, 다음과 같이 이루어진다.Looking briefly at the conventional metallization process of the prior art, it is made as follows.
우선, 접합 영역이 형성된 실리콘 기판 상에 층간 절연막을 형성하고, 이를 선택 식각하여 접합 영역을 노출시키는 콘택홀을 형성한다. 계속하여, 상기 실리콘 기판과의 오믹 콘택(ohmic contact) 및 후속 TiN막 증착시의 접착력 향상을 위하여 전체구조 상부에 Ti막을 증착하고, 후속 공정시 금속 원소가 상기 실리콘 기판으로 확산되는 것을 방지하기 위하여 상기 Ti막 상부에 TiN막을 증착한다. 이때, 상기 TiN막의 주상정 구조로 인하여 결정립 사이에 간격을 가지게 되므로 급속열처리 공정을 실시하여 산소 등을 결정립계에 충진시키게 된다. 이어서, 전체구조 상부에 주 금속막인 텅스텐막을 증착하고, 이를 패터닝하여 금속배선 공정을 완료한다.First, an interlayer insulating film is formed on a silicon substrate on which a junction region is formed, and then selectively etched to form a contact hole exposing the junction region. Subsequently, in order to improve ohmic contact with the silicon substrate and adhesion during subsequent TiN film deposition, a Ti film is deposited on the entire structure, and in order to prevent diffusion of metal elements into the silicon substrate in a subsequent process. A TiN film is deposited on the Ti film. At this time, since the TiN film has a gap between grains due to the columnar crystal structure of the TiN film, oxygen and the like are filled in the grain boundary by performing a rapid heat treatment process. Subsequently, a tungsten film as a main metal film is deposited on the entire structure, and patterned to complete the metallization process.
이때, 상기 확산 방지막의 형성을 위해서 종래에서는 상기 Ti 및 상기 TiN막을 물리 기상 증착(Physical Vapor Deposition, PVD) 방식으로 증착하였다.In this case, in order to form the diffusion barrier layer, the Ti and the TiN layer are conventionally deposited by physical vapor deposition (PVD).
그러나, 반도체 장치의 고집적화에 따라 반도체 소자에 형성이 되는 콘택홀이 깊고 좁게 형성되는 것이 불가피해짐으로 인해 층덮힘성이 나쁜 상기 PVD방식을 사용한 증착방법으로는 많은 어려움이 발생하고 있다.However, due to the high integration of semiconductor devices, it is inevitable to form deep and narrow contact holes formed in the semiconductor devices, and thus, many difficulties have arisen in the deposition method using the PVD method having poor layer covering properties.
이를 보완하기 위하여 PVD방식으로 Ti를 일차 증착하고, 유기금속 화학 기상 증착(Metal Organic Chemical Vapor Deposition, MOCVD)방식으로 TiN을 이차 증착하는 방식이 연구되고 있으나, 콘택의 단차비(Aspect Ratio)가 10이상으로 매우 깊고 좁아질 경우에는 층덮힘성의 확보 차원에서 문제점이 발생하고 있다.In order to compensate for this, a method of first depositing Ti by PVD and a second method of depositing TiN by Metal Organic Chemical Vapor Deposition (MOCVD) has been studied, but the aspect ratio of the contact is 10 In the case of becoming deeper and narrower than above, problems have arisen in order to secure layer covering properties.
장벽금속층의 우수한 층덮힘성을 얻기 위한 또 다른 방법으로써, 최근에는 무기소스인 TiCl4를 이용한 CVD방식으로 Ti 및 TiN을 증착하는 방법이 연구되고 있다.As another method for obtaining excellent layer covering properties of the barrier metal layer, recently, a method of depositing Ti and TiN by CVD using an inorganic source TiCl 4 has been studied.
그러나, 이 방법은 TiCl4증착 시 Cl기가 실리콘 기판을 침식시켜 금속배선 형성 후 소자의 누설전류를 크게 증가시키는 문제점이 발생하고 있다.However, this method has a problem in that the Cl group erodes the silicon substrate during TiCl 4 deposition, thereby greatly increasing the leakage current of the device after metal wiring formation.
또한, CVD방식으로 증착된 TiN은 결정 구조상 기둥모양의 결정으로 이루어진 주상성 조직을 갖고 있으므로 알루미늄(Al), 텅스텐(W) 및 구리(Cu) 등을 사용하는금속배선과 실리콘 기판과의 확산을 방지할 수 있는 확산방지력이 저하되는 문제점이 발생하고 있다. In addition, since TiN deposited by CVD has a columnar structure composed of pillar-shaped crystals in the crystal structure, diffusion of metal wiring using aluminum (Al), tungsten (W), copper (Cu), and the like into the silicon substrate is prevented. There is a problem that the diffusion prevention force that can be prevented is lowered.
본 발명은 장벽금속의 층덮힘성과 확산방지력을 개선할 수 있는 반도체 소자의 금속배선 형성방법을 제공하는 데 그 목적이 있다. An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can improve the layer covering and diffusion preventing power of the barrier metal.
상기 목적을 달성하기 위한 본 발명은, 반도체 소자의 금속배선 형성방법에 있어서, 금속 콘택이 형성될 부분의 실리콘기판이 노출되도록 오픈부를 갖는 층간절연막을 형성하는 제1 단계; 상기 제1 단계가 완료된 결과물의 상부에 TiSix(0.1〈 X〈 2.0)막을 형성하는 제2 단계; 상기 TiSix(0.1〈 X〈 2.0)막 상부에 TiSiyN1-y(0.01〈 y〈 0.9)막을 형성하는 제3 단계; 열처리를 실시하여 상기 TiSix(0.1〈 X〈 2.0)막을 결정화하는 제4 단계; 및 상기 제4 단계가 완료된 결과물의 상부에 배선용 금속막을 형성하는 제5 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method for forming a metal wiring of a semiconductor device, the method comprising: forming an interlayer insulating film having an open portion to expose a silicon substrate of a portion where a metal contact is to be formed; A second step of forming a TiSi x (0.1 <X <2.0) film on top of the resultant of the first step; Forming a TiSi y N 1-y (0.01 <y <0.9) film on the TiSi x (0.1 <X <2.0) film; Performing a heat treatment to crystallize the TiSi x (0.1 <X <2.0) film; And a fifth step of forming a metal film for wiring on the resultant of the fourth step.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도1a 및 도1b는 본 발명의 일실시예에 따른 금속배선 형성공정을 도시한 도면이다.1A and 1B illustrate a metal wiring forming process according to an embodiment of the present invention.
본 발명의 일실시예에 따른 금속배선 형성공정은 먼저, 도1a에 도시된 바와 같이 소정의 공정이 완료된 하부층(10) 상부에 층간절연막(11)을 형성하고, 이를 선택식각하여 캐패시터의 하부전극 콘택을 위한 콘택홀을 형성한다.In the metal wire forming process according to the embodiment of the present invention, first, as shown in FIG. 1A, an interlayer insulating film 11 is formed on the lower layer 10 on which a predetermined process is completed, and then selectively etched to form a lower electrode of the capacitor. A contact hole for contact is formed.
다음으로, 전체 구조물의 표면을 따라 확산방지막을 적층구조로 형성을 한다. Next, the diffusion barrier is formed in a laminated structure along the surface of the entire structure.
이를 구체적으로 살펴보면, 우선 전체 구조물의 표면을 따라 플라즈마 여기 화학 기상 증착(Plasma Enhanced Chemical Vapor Deposition, 이하 PECVD) 방식을 사용하여 비정질 상태의 TiSix(0.1〈 X〈 2.0)막(12)을 증착한다. 여기서, 상기 PECVD방식의 상세한 공정조건을 살펴보기로 한다.Specifically, first, a TiSi x (0.1 <X <2.0) film 12 in an amorphous state is deposited using a plasma enhanced chemical vapor deposition (PECVD) method along the surface of the entire structure. . Here, the detailed process conditions of the PECVD method will be described.
가)증착가스 : 티타늄 테트라클로라이드(TiCl4), 사일렌(SiH4), 수소(H2) 및A) Deposition gas: titanium tetrachloride (TiCl 4 ), xylene (SiH 4 ), hydrogen (H 2 ) and
아르곤(Ar) Argon (Ar)
나)증착온도 : 300 ~ 500℃B) Deposition temperature: 300 ~ 500 ℃
다)증착압력 : 0.1 ~ 20TorrC) Deposition pressure: 0.1 ~ 20Torr
라)RF 전력 : 100W ~ 1KWRF power: 100W ~ 1KW
마)공정가스/유량 : TiCl4/0.5 ~ 100sccm,E) Process gas / flow rate: TiCl 4 /0.5 ~ 100sccm,
SiH4/0.5 ~ 300sccmSiH 4 /0.5 ~ 300sccm
H2/100 ~ 5000sccmH 2/100 ~ 5000sccm
Ar/10 ~ 500sccm Ar / 10 to 500 sccm
다음으로, 비정질 상태의 TiSix(0.1〈 X〈 2.0)막(12) 상부에 TiSiyN1-y(0.01〈 y〈 0.9)막(13)을 증착한다. 이때, 상기 TiSiyN1-y(0.01〈 y〈 0.9)막(13)은 상기 TiSix(0.1〈 X〈 2.0)막(12)을 증착한 챔버에서 상기 TiSix(0.1〈 X〈 2.0)막(12)의 증착이 끝난 후, 별도의 챔버 이동없이 바로 PECVD 증착조건과 동일하게 유지한 상태에서 10sccm 내지 3000sccm 정도의 N2가스를 더 첨가하여 흘려줌으로써, 간단히 증착할 수가 있다.Next, a TiSi y N 1-y (0.01 <y <0.9) film 13 is deposited over the TiSi x (0.1 <X <2.0) film 12 in an amorphous state. At this time, the TiSi y N 1-y (0.01 <y <0.9) film 13 is the TiSi x (0.1 <X <2.0) in the chamber in which the TiSi x (0.1 <X <2.0) film 12 is deposited. After the deposition of the film 12 is completed, it is possible to simply deposit by further adding and flowing N 2 gas of about 10 sccm to 3000 sccm under the same conditions as the PECVD deposition conditions without any additional chamber movement.
다음으로, 도1b에 도시된 바와 같이 상기 TiSix(0.1〈 X〈 2.0)막(12) 및 상기 TiSiyN1-y(0.01〈 y〈 0.9)막(13) 증착 후 급속열처리공정(Rapid Thermal Process, RTP)을 수행한다. 여기서, 급속열처리공정을 수행하는 이유는 상기 TiSix(0.1〈 X〈 2.0)막(12)이 비정질상이기 때문에 실리콘 기판과의 접촉저항이 매우 큰 것에 있으며, 이를 보완하기 위하여 비정질상의 상기 TiSix(0.1〈 X〈 2.0)막(12)을 변형시켜 확산방지력이 우수한 결정질의 TiSix막(14)을 형성하기 위함이다.Next, as illustrated in FIG. 1B, a rapid heat treatment process after deposition of the TiSi x (0.1 <X <2.0) film 12 and the TiSi y N 1-y (0.01 <y <0.9) film 13 is performed. Thermal Process, RTP). The reason for rapidly performing a heat treatment step is that the contact resistance between the silicon substrate is very large because the TiSi x (0.1 <X <2.0 ) layer 12 in the amorphous phase, wherein the amorphous phase in order to compensate, TiSi x ( This is to form a crystalline TiSi x film 14 having excellent diffusion prevention force by deforming the 0.1 <X <2.0) film 12.
이때, 급속열처리공정은 Ar 또는 N2분위기에서 600℃ 내지 750℃의 공정온도 범위에서 5초 내지 30초간 수행한다.At this time, the rapid heat treatment process is performed for 5 seconds to 30 seconds in the process temperature range of 600 ℃ to 750 ℃ in Ar or N 2 atmosphere.
마지막으로, 전체 구조물의 상부에 Al, W, Cu과 같은 금속배선물질(15)을 증착하여 금속배선 형성공정을 완료한다.Finally, the metal wiring material 15 such as Al, W, Cu is deposited on the entire structure to complete the metal wiring forming process.
상기와 같이 기존의 Ti막/TiN막 구조를 가지고 PVD법으로 증착한 확산방지막을 본 발명에서는 PECVD법을 적용한 TiSix막 및 결정질의 TiSiyNy-1막 구조로 변경시키므로써, 콘택홀의 단차비가 커지는 반도체 소자의 고집적화에 대응할 수 있는 층덮힘성을 확보할 수 있고, 상기 결정질의 TiSiyNy-1막 형성에 따라 확산방지력을 증대시킬 수가 있다.As described above, the diffusion barrier film deposited by the PVD method with the existing Ti film / TiN film structure is changed to the TiSi x film and the crystalline TiSi y N y-1 film structure applied with the PECVD method. It is possible to secure the layer covering property which can cope with the high integration of the semiconductor device which the ratio becomes large, and the diffusion prevention force can be increased by forming the crystalline TiSi y N y-1 film.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 깊고 좁은 콘택에서도 우수한 층덮힘성을 가지는 효과 및 우수한 확산방지력 효과가 있다. The present invention has the effect of having excellent layer covering properties and excellent anti-diffusion effect even in deep and narrow contacts.
도1a 및 도1b는 본 발명의 일실시예에 따른 금속배선 형성공정을 도시한 도면.1A and 1B illustrate a metal wiring forming process according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawings
10 : 하부층 11 : 층간절연막10: lower layer 11: interlayer insulating film
12 : TiSix(0.1〈 X〈 2.0)막 14 : 결정질의 TiSix막12: TiSi x (0.1 <X <2.0) film 14: crystalline TiSi x film
15 : 금속배선물질15: metal wiring material
Claims (7)
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| KR10-1999-0062182A KR100529382B1 (en) | 1999-12-24 | 1999-12-24 | A method for forming metal wire in semicondutor device |
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