KR100503379B1 - Method for fabricating gate electrode of semiconductor - Google Patents

Method for fabricating gate electrode of semiconductor Download PDF

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KR100503379B1
KR100503379B1 KR10-2002-0067048A KR20020067048A KR100503379B1 KR 100503379 B1 KR100503379 B1 KR 100503379B1 KR 20020067048 A KR20020067048 A KR 20020067048A KR 100503379 B1 KR100503379 B1 KR 100503379B1
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gate electrode
forming
semiconductor substrate
conductive layer
gate
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KR20040038167A (en
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이대근
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

게이트 전극의 저항을 줄일 수 있고 소오스/드레인에 형성될 콘택 마진을 확보할 수 있는 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법은 소자 분리막이 형성된 반도체 기판 상에 LDD 영역 정의를 위한 제 1포토레지스터 패턴을 형성하는 단계와 제 1포토레지스터 패턴 양측의 반도체 기판에 LDD 영역을 형성한 후에 제 1포토레지스터 패턴을 제거하는 단계와, 반도체 기판 상에 게이트 산화막 및 제 1도전층 순차적으로 증착하고, 제 1도전층을 식각하여 스페이서를 형성하는 단계 및 스페이서가 형성된 반도체 기판 상부에 제 2도전층을 증착하고, 상기 제 2도전층 및 게이트 산화막을 식각하여 스페이서가 게이트 영역에 양측벽 바닥면에 포함되도록 게이트 전극을 형성하는 단계를 포함한다. The gate electrode forming method of the semiconductor device according to the present invention can reduce the resistance of the gate electrode and secure the contact margin to be formed in the source / drain, the first photoresist for defining the LDD region on the semiconductor substrate formed with the device isolation film Removing the first photoresist pattern after forming a pattern, forming an LDD region on the semiconductor substrates on both sides of the first photoresist pattern, depositing a gate oxide film and a first conductive layer sequentially on the semiconductor substrate, and Forming a spacer by etching the conductive layer and depositing a second conductive layer on the semiconductor substrate on which the spacer is formed, and etching the second conductive layer and the gate oxide layer so that the spacer is included in the bottom surface of both sidewalls in the gate region. Forming a gate electrode.

Description

반도체 소자의 게이트 전극 형성 방법{METHOD FOR FABRICATING GATE ELECTRODE OF SEMICONDUCTOR}Gate electrode formation method of a semiconductor device {METHOD FOR FABRICATING GATE ELECTRODE OF SEMICONDUCTOR}

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 게이트 전극 영역에 스페이서를 형성하여 게이트 전극의 저항을 줄일 수 있는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device capable of reducing a resistance of the gate electrode by forming a spacer in the gate electrode region.

일반적으로 반도체 소자의 제조 공정 중에 게이트 스페이서 형성 공정은 LDD(Lightly Doped Drain)영역을 형성하기 위한 것이며, 이러한 LDD 영역은 반도체 소자의 고집적화에 따라 게이트 전극의 크기가 작아지면서 발생되는 핫 캐리어 효과(hot carrier effect)를 감소시키게 된다.In general, a gate spacer forming process is a process of forming a lightly doped drain (LDD) region during a semiconductor device manufacturing process, and the LDD region is a hot carrier effect generated by decreasing the size of a gate electrode due to high integration of a semiconductor device. reduce the carrier effect.

또한 게이트 스페이서는 살리사이드(salicide) 공정에서 액티브 실리콘과 게이트의 상부에서만 선택적으로 살리사이드층이 형성되도록 하여 액티브의 단락을 방지하는데 이용된다.In addition, the gate spacer is used to prevent active short-circuit by selectively forming a salicide layer only on top of the active silicon and the gate in the salicide process.

이하 첨부된 도면을 이용하여 종래 반도체 소자의 게이트 전극 형성 방법을 설명한다. 도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 게이트 스페이서 형성을 위한 공정 단면도들이다.Hereinafter, a method of forming a gate electrode of a conventional semiconductor device will be described with reference to the accompanying drawings. 1A to 1C are cross-sectional views illustrating a process of forming a gate spacer of a semiconductor device according to the related art.

도 1a에 도시한 바와 같이, 반도체 기판(10)의 소정영역에 STI(Shallow Trench Isolation) 구조를 갖는 소자 분리막(11)을 형성하며, 소자 분리막(12)을 포함한 반도체 기판(10)의 전면에 게이트 산화막(12)과 폴리 실리콘층(도시되지 않음)을 순차적으로 형성한다. 이후 폴리 실리콘층 및 게이트 산화막에 사진 및 식각공정을 실시하여 선택적으로 패터닝함으로써 소자격리막(11)사이의 반도체 기판(10)상에 게이트 전극(13)을 형성한 후에 게이트 전극(13)을 마스크로 이용하여 반도체 기판(10)의 전면에 저농도 불순물 이온을 주입하여 게이트 전극(13)의 양측면에 반도체 기판(10) 표면내에 LDD 영역(14)을 형성한다.As shown in FIG. 1A, an isolation layer 11 having a shallow trench isolation (STI) structure is formed in a predetermined region of the semiconductor substrate 10, and is formed on the entire surface of the semiconductor substrate 10 including the isolation layer 12. The gate oxide film 12 and the polysilicon layer (not shown) are sequentially formed. Thereafter, the polysilicon layer and the gate oxide film are subjected to photolithography and etching processes to selectively pattern the gate electrode 13 on the semiconductor substrate 10 between the device isolation layers 11, and then use the gate electrode 13 as a mask. Low concentration impurity ions are implanted into the entire surface of the semiconductor substrate 10 to form the LDD region 14 in the surface of the semiconductor substrate 10 on both sides of the gate electrode 13.

도 1b 내지 도 1c에 도시된 바와 같이 게이트 전극(13)을 포함한 반도체 기판(10)의 전면에 절연막(15)을증착한 후에 절연막(15)의 전면에 에치백(etch back) 공정을 실시하여 게이트 스페이서(16)를 형성한다. 이후, 게이트 스페이서(16) 및 게이트 전극(13)을 마스크로 이용하여 반도체 기판(10)의 전면에 소오스/드레인용 불순물 이온을 주입하여 게이트 전극(13) 양측의 반도체 기판(10)의 표면내에 LDD 영역(14)과 연결되는 소오스/드레인 불순물 확산 영역(17)을 형성한다.1B to 1C, an insulating film 15 is deposited on the entire surface of the semiconductor substrate 10 including the gate electrode 13, and then an etch back process is performed on the entire surface of the insulating film 15. The gate spacer 16 is formed. Subsequently, source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 10 using the gate spacers 16 and the gate electrode 13 as masks, and then, within the surface of the semiconductor substrate 10 on both sides of the gate electrode 13. A source / drain impurity diffusion region 17 connected to the LDD region 14 is formed.

최근에 반도체의 고집적화에 따라 게이트간의 간격이 좁아짐에 따라 두께가 얇은 게이트 스페이서가 요구되지만, 상기와 같은 종래 방법에 의해서 형성된 게이트 스페이서는 게이트간의 간격에 관계없이 일정한 두께를 갖기 때문에 소오스/드레인에 형성될 콘택 마진이 작아지고, 게이트 전극의 저항이 커지는 문제가 있었다.Recently, thinner gate spacers are required as the gap between gates becomes narrower due to the higher integration of semiconductors. There was a problem that the contact margin to be decreased and the resistance of the gate electrode was increased.

본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 게이트 전극의 저항을 줄일 수 있고 소오스/드레인에 형성될 콘택 마진을 확보할 수 있는 반도체 소자의 게이트 전극 형성 방법이 제공된다. SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, and a method of forming a gate electrode of a semiconductor device capable of reducing resistance of a gate electrode and securing a contact margin to be formed on a source / drain is provided.

상기와 같은 목적을 달성하기 위하여 본 발명은, 소자 분리막이 형성된 반도체 기판 상에 LDD 영역 정의를 위한 제 1포토레지스터 패턴을 형성하는 단계 상기 제 1포토레지스터 패턴 양측의 반도체 기판에 LDD 영역을 형성한 후에 제 1포토레지스터 패턴을 제거하는 단계 상기 반도체 기판 상에 게이트 산화막 및 제 1도전층 순차적으로 증착하고, 상기 제 1도전층을 식각하여 스페이서를 형성하는 단계 및 상기 스페이서가 형성된 반도체 기판 상부에 제 2도전층을 증착하고, 상기 제 2도전층 및 게이트 산화막을 식각하여 상기 스페이서가 게이트 영역에 양측벽 바닥면에 포함되도록 게이트 전극을 형성하는 단계를 포함한다. In order to achieve the above object, the present invention, the step of forming a first photoresist pattern for defining the LDD region on the semiconductor substrate on which the device isolation layer is formed LDD region formed on the semiconductor substrate on both sides of the first photoresist pattern Removing the first photoresist pattern later, depositing a gate oxide film and a first conductive layer on the semiconductor substrate sequentially, etching the first conductive layer to form a spacer, and forming a spacer on the semiconductor substrate on which the spacer is formed. Depositing a second conductive layer and etching the second conductive layer and the gate oxide layer to form a gate electrode such that the spacer is included in the bottom surface of both sidewalls in the gate region.

이하에서 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세히 설명하기로 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 게이트 전극 형성 과정을 도시한 공정 단면도들이다.2A to 2G are cross-sectional views illustrating a process of forming a gate electrode of a semiconductor device according to the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(100)의 소정영역에 STI(Shallow Trench Isolation) 구조를 갖는 소자 분리막(101)을 형성하며, 소자 분리막(101)을 포함한 반도체 기판(100)의 전면에LDD 영역 형성을 위한 포토레지스터를 도포한다. 이후 포토레지스터에 노광 및 현상공정을 실시하여 선택적으로 패터닝하여 제 1포토레지스터 패턴(102)을 형성하고, 제 1포토레지스터 패턴(102)을 마스크로 이용하여 반도체 기판(100)의 전면에 저농도 불순물 이온을 주입하여 제 1포토레지스터 패턴(102)의 양측면에 반도체 기판(100) 표면내에 LDD 영역(103)을 형성한 후에 제 1포토레지스터 패턴(102)을 제거한다.As shown in FIG. 2A, an isolation layer 101 having a shallow trench isolation (STI) structure is formed in a predetermined region of the semiconductor substrate 100, and is formed on the entire surface of the semiconductor substrate 100 including the isolation layer 101. A photoresist for forming the LDD region is applied. Thereafter, the photoresist is subjected to exposure and development processes to selectively pattern the first photoresist pattern 102 to form a first photoresist pattern 102. The lightly doped impurities are formed on the entire surface of the semiconductor substrate 100 using the first photoresist pattern 102 as a mask. Ions are implanted to form the LDD region 103 in the surface of the semiconductor substrate 100 on both sides of the first photoresist pattern 102, and then the first photoresist pattern 102 is removed.

여기서, 반도체 기판(100)의 전면에 도포되는 포토레지스터의 두께는 1000Å ∼2000Å이다.Here, the thickness of the photoresist applied to the entire surface of the semiconductor substrate 100 is 1000 kPa to 2000 kPa.

도 2b에 도시된 바와 같이, LDD 영역(103)이 형성된 반도체 기판(100)의 전면에 게이트 산화막(104)과 게이트 스페이서 형성을 위한 제 1도전층(105)을 증착하고, 제 1도전층(105)의 전면에 포토레지스터를 도포한 후에 노광 및 현상 공정을 진행하여 제 2포토레지스터 패턴(106)을 형성한다. 이때, 게이트 산화막(104)의 전면에 증착되는 제 1도전층(105)은 폴리실리콘, 실리콘 산화막, 실리콘 질화막 또는 BPSG막으로 이루어져 있으며, 그 두께는 반도체 소자에서 요구되는 게이트 스페이서의 두께이며, 그 예로서 1000Å을 들 수 있다.As shown in FIG. 2B, a gate oxide layer 104 and a first conductive layer 105 for forming a gate spacer are deposited on the entire surface of the semiconductor substrate 100 on which the LDD region 103 is formed, and the first conductive layer ( After the photoresist is coated on the entire surface of the substrate 105, the exposure and development processes are performed to form the second photoresist pattern 106. At this time, the first conductive layer 105 deposited on the entire surface of the gate oxide film 104 is made of polysilicon, silicon oxide film, silicon nitride film or BPSG film, the thickness of which is the thickness of the gate spacer required in the semiconductor device, As an example, 1000 microseconds is mentioned.

도 2c에 도시된 바와 같이, 제 2포토레지스터 패턴(106)에 맞추어서 제 1도전층(105)을 식각하여 게이트 스페이서(105a)를 형성한다.As illustrated in FIG. 2C, the first conductive layer 105 is etched to conform to the second photoresist pattern 106 to form the gate spacer 105a.

이후 도 2d에 도시된 바와 같이, 게이트 스페이서(105a)가 형성된 반도체 기판(100) 전면에 게이트 전극 형성을 위한 제 2도전층(107)을 형성하고, 결과물의 상부에 포토레지스터를 도포한 후에 노광 및 현상 공정을 통해 제 3포토레지스터 패턴(107)을 형성한다. 이때 제 2도전층(107)으로는 폴리실리콘 또는 금속을 사용한다.After that, as shown in FIG. 2D, the second conductive layer 107 is formed on the entire surface of the semiconductor substrate 100 on which the gate spacers 105a are formed, and then the photoresist is applied on the resultant. And a third photoresist pattern 107 through a developing process. In this case, polysilicon or a metal is used as the second conductive layer 107.

도 2e에 도시된 바와 같이, 제 3포토레지스터 패턴(107)에 맞추어서 제 2도전층(107) 및 게이트 산화막(103)을 식각하여 게이트 전극(107a)을 형성한 후에 제 3포토레지스터 패턴(108)을 제거한다. 이때 게이트 전극(107a)에는 바닥면 일부분에 형성된 게이트 스페이서(105a)를 포함한다.As illustrated in FIG. 2E, the second conductive layer 107 and the gate oxide layer 103 are etched to form the gate electrode 107a in accordance with the third photoresist pattern 107, and then the third photoresist pattern 108 is formed. ). In this case, the gate electrode 107a includes a gate spacer 105a formed at a portion of the bottom surface.

상기와 같은 방법으로 게이트 전극을 형성함으로서 게이트 전극의 영역에 게이트 스페이서를 형성할 수 있어 게이트 전극의 측면에 실리사이드가 형성될 경우에 게이트 전극의 면적이 넓어져 저항을 낮출 수 있고, 소오스/드레인 불순물 확산 영역간의 콘택 마진을 확보할 수 있다.By forming the gate electrode as described above, the gate spacer can be formed in the region of the gate electrode. When silicide is formed on the side surface of the gate electrode, the area of the gate electrode can be increased to lower the resistance, and source / drain impurities can be reduced. The contact margin between the diffusion regions can be secured.

도 2f에 도시된 바와 같이, 게이트 스페이서(105a)를 포함한 게이트 전극(107a)을 마스크로 이용하여 반도체 기판(100)의 전면에 소오스/드레인용 불순물 이온을 주입하여 게이트 전극(107a) 양측의 반도체 기판(100) 표면내에 LDD 영역(103)과 연결되는 소오스/드레인 불순물 확산 영역(108)을 형성한다.As shown in FIG. 2F, source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 100 using the gate electrode 107a including the gate spacer 105a as a mask, thereby providing semiconductors on both sides of the gate electrode 107a. A source / drain impurity diffusion region 108 is formed in the surface of the substrate 100 to be connected to the LDD region 103.

도 2g에 도시된 바와 같이, 게이트 전극(105a)을 포함한 반도체 기판(100)의 전면에 절연막을 형성하고, 사진 및 식각 공정을 실시하여 이후 실리사이드가 형성되지 않을 영역을 덮도록 패터닝한다. 이어서, 절연막을 포함한 반도체 기판(100) 전면에 고융점 금속을 형성한 후 전면에 열처리 공정을 실시하여 절연막이 덮혀있지 않은 반도체 기판(100) 및 게이트 전극(107a)의 표면에 고융점 실리사이드 막(109)을 형성한다. As illustrated in FIG. 2G, an insulating film is formed on the entire surface of the semiconductor substrate 100 including the gate electrode 105a, and a photolithography and etching process are performed to pattern a region in which silicide is not formed. Subsequently, a high melting point metal is formed on the entire surface of the semiconductor substrate 100 including the insulating film, and then a heat treatment is performed on the entire surface of the semiconductor substrate 100 to cover the surface of the semiconductor substrate 100 and the gate electrode 107a where the insulating film is not covered. 109).

이후, 반도체 기판(100) 및 게이트 전극(107a)과 반응하지 않은 고융점 금속을 습식 식각으로 제거한다.Thereafter, the high melting point metal not reacted with the semiconductor substrate 100 and the gate electrode 107a is removed by wet etching.

이상 설명한 바와 같이, 본 발명은 포토레지스터 패턴을 이용하여 LDD 영역을 형성한 후에 LDD 영역에 맞추어서 폴리실리콘으로 이루어진 게이트 스페이서를 형성하고, 내부에 게이트 스페이서가 포함되도록 게이트 전극을 형성함으로써, 소오스/드레인 불순물 확산영역간의 콘택 마진을 확보할 수 있다.As described above, the present invention forms a gate spacer made of polysilicon in accordance with the LDD region after forming an LDD region using a photoresist pattern, and forms a gate electrode to include the gate spacer therein, thereby providing source / drain. Contact margins between impurity diffusion regions can be secured.

또한, 본 발명은 실리사이드 공정에서 게이트 전극의 상부뿐만 아니라 측면에도 실리사이드를 형성함으로써, 실리사이드 면적이 넓어져 게이트 전극의 저항을 낮출 수 있다. In addition, in the silicide process, silicide is formed not only on the upper side of the gate electrode but also on the side surface thereof, thereby increasing the silicide area and lowering the resistance of the gate electrode.

본 발명은 게이트 스페이서를 포토레지스터 패턴을 이용함으로써, 게이트스페이서의 폭을 항상 일정하게 유지할 수 있다.According to the present invention, the width of the gate spacer can be kept constant by using the photoresist pattern as the gate spacer.

도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 게이트 전극 형성 과정을 도시한 공정 단면도,1A through 1C are cross-sectional views illustrating a process of forming a gate electrode of a semiconductor device according to the prior art;

도 2a 내지 2g는 본 발명에 따른 반도체 소자의 게이트 전극 형성 과정을 h시한 공정 단면도.2A to 2G are cross-sectional views illustrating a process of forming a gate electrode of a semiconductor device according to the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

100 : 반도체 기판 101 : 소자 분리막100 semiconductor substrate 101 device isolation film

102 : 제 1포토레지스터 패턴 103 : LDD 영역102: first photoresist pattern 103: LDD region

104 : 게이트 산화막 105 : 제 1도전층104: gate oxide film 105: first conductive layer

106 : 제 2포토레지스터 패턴 105a : 게이트 스페이서106: second photoresist pattern 105a: gate spacer

107 : 제 2도전층 108 : 제 3포토레지스터 패턴107: second conductive layer 108: third photoresist pattern

107a : 게이트 전극107a: gate electrode

Claims (4)

소자 분리막이 형성된 반도체 기판 상에 LDD 영역 정의를 위한 제 1포토레지스터 패턴을 형성하는 단계Forming a first photoresist pattern for defining an LDD region on a semiconductor substrate on which an isolation layer is formed 상기 제 1포토레지스터 패턴 양측의 반도체 기판에 LDD 영역을 형성한 후에 제 1포토레지스터 패턴을 제거하는 단계Removing the first photoresist pattern after forming an LDD region on the semiconductor substrate on both sides of the first photoresist pattern 상기 반도체 기판 상에 게이트 산화막 및 제 1도전층 순차적으로 증착하고, 상기 제 1도전층을 식각하여 스페이서를 형성하는 단계Sequentially depositing a gate oxide film and a first conductive layer on the semiconductor substrate, and etching the first conductive layer to form a spacer. 상기 스페이서가 형성된 반도체 기판 상부에 제 2도전층을 증착하고, 상기 제 2도전층 및 게이트 산화막을 식각하여 상기 스페이서가 게이트 영역에 양측벽 바닥면에 포함되도록 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 게이트 전극 형성 방법.Depositing a second conductive layer on the semiconductor substrate on which the spacer is formed, and etching the second conductive layer and the gate oxide layer to form a gate electrode such that the spacer is included in the bottom surface of both sidewalls in the gate region. Method for forming a gate electrode of the device. 제 1항에 있어서,The method of claim 1, 상기 제 1도전층은,The first conductive layer, 폴리실리콘, 실리콘 산화막, 실리콘 질화막 또는 BPSG막인 반도체 소자의 게이트 전극 형성 방법.A method of forming a gate electrode of a semiconductor device which is a polysilicon, silicon oxide film, silicon nitride film or BPSG film. 제 1항에 있어서,The method of claim 1, 상기 제 2도전층은,The second conductive layer, 폴리실리콘 또는 금속인 반도체 소자의 게이트 전극 형성 방법.A method for forming a gate electrode of a semiconductor device which is polysilicon or metal. 제 1항에 있어서,The method of claim 1, 상기 포토레지스터 패턴의 두께는,The thickness of the photoresist pattern, 1000∼2000Å 인 반도체 소자의 게이트 전극 형성 방법.A method for forming a gate electrode of a semiconductor device which is 1000 to 2000 kV.
KR10-2002-0067048A 2002-10-31 2002-10-31 Method for fabricating gate electrode of semiconductor KR100503379B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758131A (en) * 1993-08-13 1995-03-03 Sumitomo Electric Ind Ltd Method of manufacturing field efect transistor and its integrated circuit
JPH0794715A (en) * 1993-09-21 1995-04-07 Matsushita Electric Ind Co Ltd Manufacture of mos transistor
KR19990080172A (en) * 1998-04-14 1999-11-05 김규현 Method of forming semiconductor device of LED structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758131A (en) * 1993-08-13 1995-03-03 Sumitomo Electric Ind Ltd Method of manufacturing field efect transistor and its integrated circuit
JPH0794715A (en) * 1993-09-21 1995-04-07 Matsushita Electric Ind Co Ltd Manufacture of mos transistor
KR19990080172A (en) * 1998-04-14 1999-11-05 김규현 Method of forming semiconductor device of LED structure

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