KR100487424B1 - Hybrid switching mode liquid crystal display device and method of making the same - Google Patents
Hybrid switching mode liquid crystal display device and method of making the same Download PDFInfo
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- KR100487424B1 KR100487424B1 KR10-1998-0027587A KR19980027587A KR100487424B1 KR 100487424 B1 KR100487424 B1 KR 100487424B1 KR 19980027587 A KR19980027587 A KR 19980027587A KR 100487424 B1 KR100487424 B1 KR 100487424B1
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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Abstract
본 발명의 복합전계방식 액정표시소자는 기판과, 기판 위에 배열되어 화소영역을 정의하는 게이트배선 및 데이터배선과, 상기 게이트배선과 데이터배선의 교차부분에 형성된 박막트랜지스터와, 상기 화소영역내의 게이트전극 및 축적용량배선 과 동일층에 형성되어 기판의 표면과 평행한 전계를 인가하는 공통전극 및 데이터 전극과, 상기 박막트랜지스터, 공통전극 및 데이터전극 위의 기판 전체에 걸쳐 도포된 보호막과, 상기 보호막 위에 형성된 제1배향막과, 상기 기판과 대향하는 기판 위에 형성된 대향전극과, 상기 대향전극 위에 형성된 제2배향막으로 이루어진다.The composite field type liquid crystal display device of the present invention includes a substrate, a gate wiring and a data wiring arranged on the substrate to define a pixel region, a thin film transistor formed at an intersection of the gate wiring and the data wiring, and a gate electrode in the pixel region. And a common electrode and a data electrode formed on the same layer as the storage capacitor wiring and applying an electric field parallel to the surface of the substrate, a protective film applied over the entire substrate on the thin film transistor, the common electrode and the data electrode, and on the protective film. And a first alignment film formed, a counter electrode formed on a substrate facing the substrate, and a second alignment film formed on the counter electrode.
Description
본 발명은 액정표시소자에 관한 것으로, 특히 액정을 구동하는 한쌍의 구동 전극을 동일층에 형성하여 바람직한 전계 형성을 유도하고, 또한 반도체층과 패드 를 동시 에칭하여 축적용량배선과 데이터배선을 연결하므로써 축적용량을 형성한 복합전계방식 액정표시소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, by forming a pair of drive electrodes for driving a liquid crystal in the same layer to induce the formation of a desirable electric field, and by simultaneously etching the semiconductor layer and the pad to connect the storage capacitor wiring and the data wiring. A composite electric field type liquid crystal display device having a storage capacitor.
고화질, 저전력의 평판표시장치(flat panel display device)로서 주로 사용되는 트위스트네마틱모드(twisted nematic mode) 액정표시소자(liquid crystal display device)는 시야각이 좁다는 단점이 있다. 이것은 액정분자의 굴절율 이방성(refractive anisotropy)에 기인하는 것으로, 기판과 수평하게 배향된 액정분자가 액정패널(liquid crystal panel)에 전압이 인가될 때 기판과 거의 수직방향으로 배향되기 때문이다.The twisted nematic mode liquid crystal display device, which is mainly used as a flat panel display device of high quality and low power, has a disadvantage of having a narrow viewing angle. This is due to the refractive anisotropy of the liquid crystal molecules, because the liquid crystal molecules oriented horizontally with the substrate are oriented almost perpendicular to the substrate when a voltage is applied to the liquid crystal panel.
따라서, 최근에는 액정분자를 기판과 거의 수평한 방향으로 배향하여 시야각 문제를 해결하는 횡전계방식 액정표시소자(in plane switching mode LCD)가 활발하게 연구되고 있다.Therefore, recently, in-plane switching mode LCDs have been actively studied to solve the viewing angle problem by aligning liquid crystal molecules in a substantially horizontal direction with a substrate.
도 1(a)는 종래 횡전계방식 액정표시소자의 단위화소의 평면도, 도 1(b)는 도 1(a)의 Ⅰ-Ⅰ'선에 따른 단면도로서 도면에 나타낸 바와 같이, 투명한 제1기판(10)에는 화소영역을 정의하는 게이트배선(1) 및 데이터배선(2)이 종횡으로 배열되어 있다. 실제의 액정패널은 복수의 화소영역으로 구성되어 있지만 도면에서는 단위화소만을 나타낸다. 상기한 화소영역 내에는 게이트배선(1)과 평행한 공통배선 (16)이 배열되어 있으며, 게이트배선(1)과 데이터배선(2)의 교차점에는 박막트랜지스터(thin film transistor)가 형성되어 있다. 박막트랜지스터는 게이트전극(3), 게이트절연막(19), 소스전극(4a), 드레인전극(4b), 반도체층(12), 오믹컨택층(13)으로 구성되며, 상기한 게이트전극(3) 및 소스전극(4a)은 각각 게이트배선(1) 및 데이터배선(2)에 접속된다. 또한, 게이트절연막(12)은 기판 전체에 걸쳐서 적층되어 있다.FIG. 1 (a) is a plan view of a unit pixel of a conventional transverse electric field type liquid crystal display device, and FIG. 1 (b) is a sectional view taken along the line II ′ of FIG. 1 (a), as shown in the drawing. In (10), the gate wirings 1 and the data wirings 2 defining the pixel regions are vertically and horizontally arranged. Although the actual liquid crystal panel is composed of a plurality of pixel regions, only the unit pixels are shown in the drawing. The common wiring 16 parallel to the gate wiring 1 is arranged in the pixel area, and a thin film transistor is formed at the intersection of the gate wiring 1 and the data wiring 2. The thin film transistor includes a gate electrode 3, a gate insulating film 19, a source electrode 4a, a drain electrode 4b, a semiconductor layer 12, and an ohmic contact layer 13. The gate electrode 3 is described above. And the source electrode 4a are connected to the gate wiring 1 and the data wiring 2, respectively. The gate insulating film 12 is stacked over the entire substrate.
화소영역에는 서로 평행하게 배열되어 횡전계를 인가하는 공통전극(7) 및 데이터전극(8)이 형성되어 있다. 공통전극(7)은 제1기판(10) 위에 게이트전극(3)과 동시에 형성되어 공통배선(16)에 접속되며, 데이터전극(8)은 게이트절연막(19) 위에 소스전극(4a) 및 드레인전극(4b)과 동시에 형성되어 박막트랜지스터의 드레인전 극(4b)에 접속된다. 그리고 제1기판(10) 전체에 걸쳐서 보호막(22) 및 제1배향막 (도시하지 않음)이 도포되어 있다.In the pixel region, a common electrode 7 and a data electrode 8 arranged in parallel with each other to apply a transverse electric field are formed. The common electrode 7 is formed on the first substrate 10 at the same time as the gate electrode 3 and connected to the common wiring 16. The data electrode 8 is disposed on the gate insulating film 19 and the source electrode 4a and the drain. It is formed simultaneously with the electrode 4b and connected to the drain electrode 4b of the thin film transistor. A protective film 22 and a first alignment film (not shown) are applied over the entire first substrate 10.
제2기판(11)에는 박막트랜지스터, 게이트배선(1), 데이터배선(2) 근처로 빛이 새는 것을 방지하는 블랙매트릭스(15)와 컬러필터층(25)이 형성되어 있으며, 그 위에 제2배향막(도시하지 않음)이 도포되어 있다.On the second substrate 11, a black matrix 15 and a color filter layer 25 are formed on the second substrate 11 to prevent light from leaking near the thin film transistor, the gate wiring 1, and the data wiring 2. The second alignment film is formed thereon. (Not shown) is applied.
상기한 제1기판(10) 및 제2기판(11) 사이에는 액정층(30)이 형성된다.The liquid crystal layer 30 is formed between the first substrate 10 and the second substrate 11.
상기한 구조의 액정표시소자에서 전압이 인가되지 않는 경우에는 액정층(30)내의 액정분자가 상기 제1배향막 및 제2배향막의 배향방향에 따른 배향되지만, 공통전극(7)과 데이터전극(8) 사이에 전압이 인가되면 상기한 공통전극(7)과 데이터 전극(8) 사이에 기판(10)의 표면과 평행한 횡전계가 인가되어 액정층(30)내의 액정분자가 상기한 횡전계에 의해 상기한 공통전극(7) 및 데이터전극(8)의 연장방향으로 회전하게 된다. 즉, 초기 배향방향으로부터 두 전극 사이의 전기장의 방향을 따라 회전하게 되는 것이다. 상기한 바와 같이, 액정층(30) 내의 액정분자가 항상 동일한 평면상에서 스위칭되기 때문에, 상하방향 및 좌우방향의 시야각방향에서 계조표시(grey level)의 반전이 일어나지 않는다.When no voltage is applied to the liquid crystal display device having the above-described structure, the liquid crystal molecules in the liquid crystal layer 30 are aligned in the alignment directions of the first and second alignment layers, but the common electrode 7 and the data electrode 8 are aligned. When a voltage is applied between the common electrode 7 and the data electrode 8, a transverse electric field parallel to the surface of the substrate 10 is applied, so that the liquid crystal molecules in the liquid crystal layer 30 are applied to the transverse electric field. As a result, the common electrode 7 and the data electrode 8 rotate in the extending direction. That is, it rotates along the direction of the electric field between the two electrodes from the initial orientation direction. As described above, since the liquid crystal molecules in the liquid crystal layer 30 are always switched on the same plane, gray level inversion does not occur in the vertical and horizontal viewing angle directions.
도 2(a)는 도 1(a)에 나타낸 액정표시소자의 축적용량배선 형성부의 평면도, 도 2(b)는 도 2(a)의 Ⅱ-Ⅱ'선에 따른 단면도로서 도면에 나타내듯이, 게이트전극 (3) 및 축적용량배선(5)위에는 오픈영역(18)을 갖는 게이트절연막(19)과 반도체층 (12)이 순서대로 적층되어 있고, 상기 반도체층(12)위에는 상기 게이트절연막(19)의 오픈영역(18)을 통하여 상기 축적용량배선(5)과 접속되는 데이터배선(2)이 형성된다. 이때, 데이터배선(14)은 도 1(a)의 소스/드레인전극(4a, 4b)형성시에 함께 형성된다. 또한, 상기 데이터배선(2)위에는 보호막(22)이 기판 전체에 걸쳐 적층되어 있다.FIG. 2 (a) is a plan view of the storage capacitor wiring forming portion of the liquid crystal display device shown in FIG. 1 (a), and FIG. 2 (b) is a sectional view taken along the line II-II 'of FIG. The gate insulating film 19 having the open region 18 and the semiconductor layer 12 are sequentially stacked on the gate electrode 3 and the storage capacitor wiring 5, and the gate insulating film 19 is disposed on the semiconductor layer 12. The data wiring 2 connected to the storage capacitor wiring 5 is formed through the open region 18 of the " At this time, the data lines 14 are formed together when the source / drain electrodes 4a and 4b of FIG. 1A are formed. In addition, a protective film 22 is laminated on the data wiring 2 over the entire substrate.
상기한 구조는 이하에 설명하는 도 3의 제조공정을 따른다.The above structure follows the manufacturing process of FIG. 3 described below.
도 3은 종래 횡전계방식 액정표시소자의 제조방법을 나타내는 도면으로서, TFT영역은 Ⅰ-Ⅰ'선을 따른 단면영역을, 스토리지영역은 도 2(a)의 Ⅱ-Ⅱ'선을 따른 단면영역을 나타낸다. 도면에 나타내듯이, 종래 횡전계방식 액정표시소자의 제조는 게이트전극(3), 공통전극(7) 및 축적용량배선(5)을 패터닝하는 단계(가)와, 상기 게이트전극(3)위에 게이트절연막(19), 반도체층(12) 및 오믹컨택층(13)을 형성한 후 반도체층(12) 및 오믹컨택층(13)을 패터닝하는 단계(나)와, 축적용량배선 형성부의 게이트절연막(19)의 일부를 오픈하여 오픈영역(18)을 형성하는 단계(다)와, 상기 오믹컨택층(13) 및 게이트절연막(19)위에 소스/드레인전극(4a, 4b) 및 데이터 배선(2)을 패터닝하는 단계(라)와, 그리고 n+드라이에칭 후 보호막(22)을 형성하는 단계(마)를 포함한다.3 is a view illustrating a conventional method of manufacturing a transverse electric field type liquid crystal display device, in which a TFT area is a cross-sectional area along a line I-I 'and a storage area is a cross-sectional area along a line II-II' in FIG. 2 (a). Indicates. As shown in the drawings, a conventional transverse electric field type liquid crystal display device is fabricated by patterning a gate electrode 3, a common electrode 7, and a storage capacitor wiring 5 (a), and a gate on the gate electrode (3). After the insulating film 19, the semiconductor layer 12 and the ohmic contact layer 13 are formed, patterning the semiconductor layer 12 and the ohmic contact layer 13 (b), and the gate insulating film of the storage capacitor wiring forming portion ( Opening a portion of the portion 19 to form an open region 18 (c), and source / drain electrodes 4a and 4b and data wirings 2 on the ohmic contact layer 13 and the gate insulating film 19; Patterning (D) and forming a protective film 22 after n + dry etching.
그러나, 상기한 구조의 액정표시소자에서는 공통전극(7)이 기판(10)에 형성 되고 데이터전극(8)이 게이트절연막(19) 위에 형성되기 때문에, 양전극(7,8) 사이에 인가되는 전계가 정확하게 기판(10)의 표면과 평행하지 않게 된다. 따라서, 액정층(30) 내의 액정분자가 기판(10)의 표면과 완전히 평행하게 스위칭되지 않게 되어 상대적으로 시야각이 좁아지는 문제가 있었다. 더욱이, 공통전극(7)과 데이터전극(8) 사이의 게이트절연막(19)은 횡전계를 약화시키는 원인이 되어 액정분자의 스위칭속도, 즉 액정분자의 반응속도의 저하를 야기한다. 또한, 데이터전극(8) 위의 보호막은 상기한 두 전극(7,8)사이의 전계의 세기를 약화시키는 주요한 요인이 된다. 따라서, 액정층(30) 내의 액정분자의 반응속도가 저하되어 동화상의 구현시 화면의 끊어지는 현상이 발생하게 된다.However, in the liquid crystal display of the above structure, since the common electrode 7 is formed on the substrate 10 and the data electrode 8 is formed on the gate insulating film 19, an electric field applied between the positive electrodes 7 and 8. Is not exactly parallel to the surface of the substrate 10. Therefore, the liquid crystal molecules in the liquid crystal layer 30 do not switch completely in parallel with the surface of the substrate 10, so that there is a problem that the viewing angle is relatively narrow. In addition, the gate insulating film 19 between the common electrode 7 and the data electrode 8 causes the transverse electric field to be weakened, leading to a decrease in the switching speed of the liquid crystal molecules, that is, the reaction speed of the liquid crystal molecules. In addition, the protective film on the data electrode 8 is a major factor in weakening the strength of the electric field between the two electrodes 7, 8. Therefore, the reaction rate of the liquid crystal molecules in the liquid crystal layer 30 is lowered, causing the screen to break when the moving image is implemented.
또한, 상기한 종래 기술에서는 축적용량배선 형성시에 게이트절연막을 오픈 하여 게이트전극과 데이터배선을 연결하는 공정이 복잡하고, 이 경우 접촉저항이 크다는 단점이 있었다.In addition, the above-described conventional technique has a disadvantage in that a process of connecting the gate electrode and the data wiring by opening the gate insulating film when forming the storage capacitor wiring is complicated, and in this case, the contact resistance is large.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로, 반도체층 및 패드영역을 동시 에칭하므로써 단축된 공정으로 액정표시소자를 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and provides a liquid crystal display device in a shortened process by simultaneously etching the semiconductor layer and the pad region.
본 발명의 다른 목적은 공통전극과 데이터전극을 동일층에 형성하여 기판의 표면과 평행한 전계를 액정층에 인가함으로써, 시야각을 향상시킨 복합전계방식 액정표시소자 및 그 제조방법을 제공하는 것이다.Another object of the present invention is to provide a composite field type liquid crystal display device and a method of manufacturing the same, by forming a common electrode and a data electrode on the same layer and applying an electric field parallel to the surface of the substrate to the liquid crystal layer.
본 발명의 또 다른 목적은 공통전극 및 데이터전극이 형성되는 화소영역의 게이트절연막을 에칭하여 액정분자의 스위칭속도를 향상시킴으로써, 반응속도를 향상시키는 것이다.Another object of the present invention is to improve the reaction speed by etching the gate insulating film of the pixel region where the common electrode and the data electrode are formed to improve the switching speed of the liquid crystal molecules.
본 발명의 또 다른 목적은 단축된 공정으로 축적용량배선과 데이터배선을 직접 접속시키므로써 접촉저항을 낮추는 것이다.Another object of the present invention is to reduce the contact resistance by directly connecting the storage capacitor wiring and the data wiring in a shortened process.
상기한 목적을 달성하기 위해 본 발명에 따른 복합전계방식 액정표시소자는 제1기판 및 제2기판과, 상기한 제1기판에 종횡으로 배열되어 화소영역을 정의하는 게이트배선 및 데이터배선과, 상기한 화소영역내에 게이트배선과 대략 평행하게 배열된 공통배선과, 상기한 게이트배선과 데이터배선의 교차부분에 형성된 박막트랜지스터와, 상기한 화소내의 동일층에 형성된 공통전극, 데이터전극 및 축적용량배선과, 상기한 기판 전체에 걸쳐 적층된 보호막(박막트랜지스터영역에만 한정되어 적층될 수 있다.)과, 상기한 제1기판 전체에 걸쳐서 도포되어 배향처리된 제1배향막과, 상기한 제2기판에 형성되어 게이트배선, 데이터배선, 박막트랜지스터 근처로 빛이 새는 것을 방지하는 차광층과, 상기한 차광층 위에 형성된 컬러필터층과, 상기한 컬러필터층 위에 도포되어 배향처리된 제2배향막과, 상기한 제1기판과 제2기판 사이에 형성된 액정층으로 구성된다.In order to achieve the above object, a composite field type liquid crystal display device according to the present invention includes a gate wiring and a data wiring arranged vertically and horizontally on a first substrate and a second substrate, the first substrate to define a pixel region, and A common wiring arranged substantially parallel to the gate wiring in one pixel region, a thin film transistor formed at an intersection of the gate wiring and the data wiring, a common electrode, a data electrode, and a storage capacitor wiring formed on the same layer in the pixel; And a passivation film (limited to a thin film transistor region only) stacked over the entire substrate, a first alignment layer coated and oriented over the entire first substrate, and formed on the second substrate. And a light blocking layer for preventing light from leaking near the gate wiring, the data wiring, and the thin film transistor, a color filter layer formed on the light blocking layer, and the color filter layer. The it consists of a liquid crystal layer formed between the first substrate and the second substrate and is the alignment process a second alignment film, wherein the coating on.
본 발명의 다른 실시예에서는 상기한 제2기판위에 상기 공통전극 및 데이터 전극과 대향하는 하나 또는 그 이상의 전극을 형성하는 것도 가능하다. 이 경우 상기 데이터전극과 공통전극에 의한 횡전계 뿐만 아니라, 대향전극의 위치에 따라 수직 및 경사전계의 인가 또한 가능하다.In another embodiment of the present invention, it is also possible to form one or more electrodes on the second substrate facing the common electrode and the data electrode. In this case, not only the transverse electric field by the data electrode and the common electrode, but also vertical and inclined electric fields may be applied depending on the position of the counter electrode.
화소영역 내의 게이트절연막은 에칭되어 있기 때문에, 공통전극과 데이터전극은 제 1기판에 형성됨과 동시에 그 위에는 제1배향막만이 도포되어 있다.따라서, 기판의 표면과 평행한 전계의 세기가 종래에 비해 한층 강해진다. 박막트랜지스터 의 반도체층과 게이트절연막은 게이트배선과 공통배선을 따라 적층되어 게이트배선 과 데이터배선 사이, 공통배선과 데이터전극 사이, 게이트배선과 공통전극 및 데어터전극 사이의 단락을 방지한다.Since the gate insulating film in the pixel region is etched, the common electrode and the data electrode are formed on the first substrate and only the first alignment film is coated thereon. Thus, the intensity of the electric field parallel to the surface of the substrate is higher than that of the conventional art. It becomes stronger. The semiconductor layer and the gate insulating layer of the thin film transistor are stacked along the gate line and the common line to prevent a short circuit between the gate line and the data line, between the common line and the data electrode, and between the gate line and the common electrode and the data electrode.
상기한 복합전계방식 액정표시소자를 제조하는 방법은 제1기판 위에 금속을 적층하고 패터닝하여 게이트배선, 게이트전극, 공통배선. 공통전극 및 축적용량배선을 형성하는 단계와, 기판 전체에 걸쳐서 무기물, 비정질실리콘 및 불순물 비정질실리콘을 연속 적층한 후, 상기한 무기물, 비정질실리콘 및 불순물 비정질실리콘을 패터닝하여 게이트절연막, 반도체층 및 오믹컨택층(n+층)을 형성하는 단계와, 상기 게이트절연막, 반도체층 및 오믹컨택층 위에 금속을 적층한 후 패터닝하여 소스/드레인전극 및 데이터전극을 형성하고 상기한 소스/드레인전극을 마스크로 오믹콘택층을 패터닝하는 단계와, 유기물 또는 무기물을 적층하고 에칭하여 보호막을 형성하는 단계와, 제1기판 전체에 걸쳐서 제1배향막을 도포하고 배향처리하는 단계와, 제2기판에 차광층을 형성하는 단계와, 상기한 차광층 및 제2기판 위에 컬러필터층을 형성하는 단계와, 상기한 컬러필터층 위에 제2배향막을 도포하고 배향처리 하는 단계와, 상기한 제1기판과 제2기판 사이에 액정층을 형성하는 단계로 구성된다.The method of manufacturing the composite field type liquid crystal display device includes a gate wiring, a gate electrode, and a common wiring by stacking and patterning a metal on a first substrate. Forming a common electrode and a storage capacitor wiring, and sequentially stacking inorganic, amorphous silicon, and impurity amorphous silicon over the entire substrate, and then patterning the inorganic, amorphous silicon, and impurity amorphous silicon to form a gate insulating film, a semiconductor layer, and an ohmic. Forming a contact layer (n + layer), stacking and patterning a metal on the gate insulating layer, the semiconductor layer, and the ohmic contact layer to form a source / drain electrode and a data electrode, and using the source / drain electrode as a mask Patterning a contact layer, laminating and etching an organic or inorganic material to form a protective film, applying and orienting the first alignment film over the entire first substrate, and forming a light shielding layer on the second substrate Forming a color filter layer on the light shielding layer and the second substrate; applying a second alignment layer on the color filter layer; And forming a liquid crystal layer between the first substrate and the second substrate.
이하, 첨부한 도면을 참조하여 본 발명에 따른 액정표시소자를 상세히 설명한다.Hereinafter, a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4(a)는 본 발명의 복합전계방식 액정표시소자의 단위화소의 평면도, 도 4(b)는 도 4(a)의 Ⅲ-Ⅲ'선에 따른 단면도로서, 도면에 나타낸 바와 같이, 제1기판(110) 위에는 게이트배선(101) 및 데이터배선(102)이 종횡으로 배열되어 화소영역을 정의한다. 화소영역 내에는 상기한 게이트배선(101)과 평행한 공통배선(116)이 배열되어 있다. 게이트배선(101)과 데이터배선(102)의 교차점에는 박막트랜지스터가 형성되어, 박막트랜지스터의 게이트전극(103)이 게이트배선(101)에 접속되고 소스전극(104a)이 데이터배선(102)에 접속된다. 화소영역 내에는 대략 서로 평행한 공통전극(107)과 데이터전극(108)이 형성되는데, 공통전극(107)은 공통배선(116)에 접속되고 데이터전극(108)은 드레인전극(104b)에 접속된다.4 (a) is a plan view of a unit pixel of the composite field liquid crystal display device of the present invention, and FIG. 4 (b) is a sectional view taken along the line III-III 'of FIG. 4 (a). The gate wiring 101 and the data wiring 102 are vertically and horizontally arranged on the first substrate 110 to define the pixel area. In the pixel area, the common wiring 116 parallel to the gate wiring 101 is arranged. A thin film transistor is formed at the intersection of the gate wiring 101 and the data wiring 102, so that the gate electrode 103 of the thin film transistor is connected to the gate wiring 101 and the source electrode 104a is connected to the data wiring 102. do. The common electrode 107 and the data electrode 108 which are substantially parallel to each other are formed in the pixel area. The common electrode 107 is connected to the common wiring 116 and the data electrode 108 is connected to the drain electrode 104b. do.
본 발명에서는 게이트절연막(119)이 박막트랜지스터 영역과 스토리지영역의 공통배선(116)과 데이터전극(108)이 중첩되는 영역에 한정되어 적층되어 있고, 이 로인하여 공통전극(107)과 데이터전극(108)은 동일 평면상에 존재한다. 또한, 반도체층(112)과 게이트절연막(119)은 게이트배선(101)을 따라. 그리고 공통배선(116)과 데이터전극(108) 사이에 적층되어 상기한 게이트배선(101)과 데이터배선(102) 사이(도시하지 않음) 및 공통배선(116)과 데이터전극(108) 사이(도 4(a)의 빗금친 영역)의 단락을 방지한다.In the present invention, the gate insulating layer 119 is stacked in a region in which the common wiring 116 and the data electrode 108 overlap the thin film transistor region and the storage region, and thus, the common electrode 107 and the data electrode ( 108 is on the same plane. In addition, the semiconductor layer 112 and the gate insulating film 119 are along the gate wiring 101. The common wiring 116 and the data electrode 108 are stacked between the gate wiring 101 and the data wiring 102 (not shown) and between the common wiring 116 and the data electrode 108 (Fig. The short circuit of (hatched area of 4 (a)) is prevented.
상기한 바와 같이, 공통전극(107)과 데이터전극(108)이 동일 평면에 배치되면, 액정층(130)에는 이상적인 횡전계가 인가된다. 또한, 전체가 게이트절연막(119)을 거치지 않고 직접 액정층(130)에 인가되기 때문에, 전계의 세기가 약화되지 않게 되어 액정분자의 반응속도가 한층 빨라진다.As described above, when the common electrode 107 and the data electrode 108 are disposed on the same plane, an ideal transverse electric field is applied to the liquid crystal layer 130. In addition, since the whole is directly applied to the liquid crystal layer 130 without passing through the gate insulating film 119, the intensity of the electric field is not weakened, and the reaction rate of the liquid crystal molecules is further increased.
도면에서는 공통전극(107)과 데이터전극(108)이 제1기판(110)에 형성되어 있지만, 상기한 양전극(107, 108)이 동일한 층에 형성되는 다른 구성도 가능하다. 다시 말해서, 게이트절연막(119)이 제1기판(110) 전체에 적층되고 그 위에 양 전극 (107, 108)이 형성되는 것도 가능하다. 이때, 공통배선(116)과 공통전극(107)은 게이트절연막(119)이나 보호막(122) 위에 배열하여 서로 접속되거나 또는 게이트절연막(119)이나 보호막(122)에 형성된 홀을 통해 서로 접속될 수 있다.Although the common electrode 107 and the data electrode 108 are formed on the first substrate 110 in the drawing, other configurations in which the above-described positive electrodes 107 and 108 are formed on the same layer are possible. In other words, it is also possible for the gate insulating film 119 to be laminated on the entire first substrate 110 and both electrodes 107 and 108 formed thereon. In this case, the common wiring 116 and the common electrode 107 may be connected to each other by being arranged on the gate insulating film 119 or the protective film 122, or may be connected to each other through holes formed in the gate insulating film 119 or the protective film 122. have.
박막트랜지스터의 게이트절연막(119) 위에는 반도체층(112)이 형성되어 있다. 또한, 상기한 반도체층(112)은 게이트배선(101)과 데이터배선(102)의 교차부분 및 공통배선(116)과 데이터전극(108) 사이에 적층되어 단락을 방지한다.The semiconductor layer 112 is formed on the gate insulating layer 119 of the thin film transistor. In addition, the semiconductor layer 112 is laminated between the gate line 101 and the data line 102 and between the common line 116 and the data electrode 108 to prevent a short circuit.
그리고, 상기한 제1기판(110) 전체에 걸쳐서 제1배향막(도시하지 않음)이 도포되고 배향처리되어 배향방향이 결정된다.Then, a first alignment film (not shown) is applied and aligned on the entire first substrate 110 to determine the orientation direction.
제2기판(111)에는 게이트배선(101), 데이터배선(102), 박막트랜지스터 근처로 빛이 새는 것을 방지하는 차광층인 블랙매트릭스(115)가 형성되어 있으며, 그 위에 컬러필터층(125)이 적층되어 R,G,B가 각 화소에 반복한다. 컬러필터층(125)위에는 제2배향막(도시하지 않음)이 도포되고 배향처리되어 배향방향이 결정된다. 컬러필터층(125)과 제2배향막 사이에는 평탄성을 향상시키기 위해, 오버코트층(overcoat layer)이 형성될 수도 있다.The second substrate 111 is provided with a black matrix 115, which is a light blocking layer that prevents light leakage near the gate wiring 101, the data wiring 102, and the thin film transistor, and the color filter layer 125 is formed thereon. They are stacked and R, G, and B are repeated in each pixel. On the color filter layer 125, a second alignment film (not shown) is applied and oriented to determine the orientation direction. An overcoat layer may be formed between the color filter layer 125 and the second alignment layer to improve flatness.
상기한 바와 같이, 본 발명의 액정표시소자에서는 공통전극(107)과 데이터전극(108)이 동일 평면에 형성되기 때문에, 양전극(107,108) 사이에 전압이 인가되면, 액정내에는 기판의 표면과 거의 완전하게 평행한 전계가 인가된다. 따라서, 액정층(130)내의 액정분자가 기판의 표면과 평행하게 되어 시야각특성이 향상된다. 또한, 공통전극(107) 및 데이터전극(108) 사이에는 게이트절연막(119)이 존재하지 않으므로 액정층(130) 내에는 강한 세기의 전계가 인가된다. 그러므로, 액정층(130) 내의 액정분자의 스위칭속도가 향상된다.As described above, in the liquid crystal display device of the present invention, since the common electrode 107 and the data electrode 108 are formed on the same plane, when a voltage is applied between the positive electrodes 107 and 108, the liquid crystal display device has almost the surface of the substrate in the liquid crystal. A completely parallel electric field is applied. Therefore, the liquid crystal molecules in the liquid crystal layer 130 are parallel to the surface of the substrate, thereby improving the viewing angle characteristic. In addition, since the gate insulating layer 119 does not exist between the common electrode 107 and the data electrode 108, a strong electric field is applied to the liquid crystal layer 130. Therefore, the switching speed of the liquid crystal molecules in the liquid crystal layer 130 is improved.
비록 도면으로 나타내지는 않았지만 본 발명의 다른 실시예에서는 상기한 제2기판(111)위에 상기 공통전극(107) 및 데이터전극(108)과 대향하는 하나 또는 그 이상의 대향전극을 형성하는 것도 가능하다. 이 경우 상기 데이터전극(108)과 공통전극(107)에 의한 횡전계 뿐만 아니라, 대향전극의 위치에 따라 수직 및 경사전계의 인가 또한 가능하다. 또한, 상기한 블랙매트릭스가 대향전극의 역할을 하는 것도 가능하다.Although not shown in the drawings, it is also possible to form one or more counter electrodes on the second substrate 111 that face the common electrode 107 and the data electrode 108. In this case, not only the transverse electric field by the data electrode 108 and the common electrode 107, but also vertical and inclined electric fields may be applied depending on the position of the counter electrode. It is also possible for the black matrix to serve as a counter electrode.
도 5(a)는 도 4(a)에 나타낸 액정표시소자의 축적용량배선 형성부의 평면도,도 5(b)는 도 5(a)의 Ⅳ-Ⅳ'선에 따른 단면도로서 도면에 나타내듯이, 게이트전극(103) 및 축적용량배선(105) 위에는 접속영역(118)을 갖는 데이터배선(102)이 형성된다. 이때, 데이터배선(102)은 도 4(a)의 소스/드레인전극(104a,104b) 형성시에 함께 형성되는데, 소스/드레인전극(104a, 104b) 패턴시에 축적용량배선(105)이 노출되어 있으므로 전극과 배선은 선택비가 있는 금속이어야 한다. 예를 들면, 축적용량배선이 Al/AlTa 또는 AlNd인 경우 소스/드레인전극은 Cr이, 축적용량배선이 Cr/Al인 경우 소스/드레인전극은 Mo가 바람직하다. 또한, 상기 데이터배선(102) 위에는 보호막(122)이 기판 전체에 걸쳐 적층되어 있다. 이때, 상기 보호막(122)은 화소영역은 제외하고, 박막트랜지스터영역에만 한정되어 형성될 수 있는데, 이 경우 인가되는 전계의 세기를 한층 강화시키는 효과가 있다.FIG. 5 (a) is a plan view of the storage capacitor wiring forming portion of the liquid crystal display device shown in FIG. 4 (a), and FIG. 5 (b) is a sectional view taken along the line IV-IV 'of FIG. 5 (a). The data wiring 102 having the connection region 118 is formed over the gate electrode 103 and the storage capacitor wiring 105. At this time, the data wiring 102 is formed together when the source / drain electrodes 104a and 104b are formed in FIG. 4A, and the storage capacitor wiring 105 is exposed when the source / drain electrodes 104a and 104b are patterned. As such, the electrodes and wiring should be metal with selectivity. For example, when the storage capacitor wiring is Al / AlTa or AlNd, the source / drain electrode is preferably Cr, and when the storage capacitor wiring is Cr / Al, the source / drain electrode is preferably Mo. In addition, the passivation layer 122 is stacked over the entire substrate on the data line 102. In this case, the passivation layer 122 may be formed to be limited to the thin film transistor region except for the pixel region. In this case, the protective layer 122 may further enhance the intensity of the applied electric field.
상기한 구조는 이하에 설명하는 도 6의 제조공정을 따른다.The above structure follows the manufacturing process of FIG. 6 described below.
도 6은 본 발명에 따른 복합전계방식 액정표시소자의 제조방법을 나타내는 도면으로서, TFT영역은 도 4(a)의 Ⅲ-Ⅲ'선에 따른 단면 영역을, 스토리지영역은 도 5(a)의 Ⅳ-Ⅳ'선에 따른 단면영역을 나타내고 있다. 도면에 나타내듯이, 본 발명에 따른 복합전계방식 액정표시소자의 제조는, 우선, 제1기판(110) 위에 Ta, Cr 및 Al합금 등과 같은 금속을 스퍼터링(sputtering)방법으로 적층하고 에칭하여 게이트전극(103), 공통전극(107) 및 축적용량배선(105)을 형성한다(가). 이때, 도면에는 나타내지 않았지만, 상기한 게이트전극(103) 및 공통전극(107) 형성시 게이트 배선과 공통배선이 동시에 형성된다. 이때, 절연성의 향상을 위해 상기한 게이트전극(103)과 공통전극(107)을 양극산화하여 양극산화막(anodization layer)을 형성할 수도 있다. 그 후, SiOx나 SiNx와 같은 무기물, 비정질실리콘(a-Si), 불순물 비정질실리콘(n+a-Si)을 PECVD(Plasma Enhanced Chemical Vapor Deposition)방법으로 연속 적층한 후 상기한 무기물, a-Si alc n+a-Si을 한꺼번에 에칭하여 게이트절연막(119), 반도체층(112) 및 오믹컨택층(113)을 형성하는데, 상기한 게이트절연막(119)과 반도체층(112)은 공통배선과 데이터전극의 중첩영역 및 데이터배선과 게이트배선의 중첩영역에 단락을 방지할 목적으로 형성된다(나). 그 위에 Cr 또는 Mo와 같은 금속을 스퍼터링방법으로 적층한 후 에칭하여 소스전극(104a), 드레인전극(104b), 데이터전극(108) 및 데이터배선(102)을 형성하며, 상기한 소스전극(104a)과 드레인전극(104b)을 마스크(mask)로 사용하여 상기한 오믹컨택층(113)을 패터닝한다(다). 박막트랜지스터의 반도체층(112) 위에는 오믹컨택층(113) 에칭시 상기한 반도체층(112)이 에칭되는 것을 방지하기 위한 ES층(etching stopper layer)를 형성할 수도 있다.6 is a view showing a method of manufacturing a composite field type liquid crystal display device according to the present invention, in which the TFT area is a cross-sectional area along the line III-III 'of FIG. 4 (a), and the storage area is shown in FIG. 5 (a). The cross-sectional area along the IV-IV 'line is shown. As shown in the figure, in the manufacture of a composite field type liquid crystal display device according to the present invention, first, a metal such as Ta, Cr, Al alloy, etc. is laminated and etched on the first substrate 110 by a sputtering method to form a gate electrode. (103), the common electrode 107 and the storage capacitor wiring 105 are formed (A). At this time, although not shown in the drawing, the gate wiring and the common wiring are simultaneously formed when the gate electrode 103 and the common electrode 107 are formed. In this case, in order to improve insulation, the gate electrode 103 and the common electrode 107 may be anodized to form an anodization layer. Thereafter, inorganic materials such as SiOx or SiNx, amorphous silicon (a-Si), and impurity amorphous silicon (n + a-Si) are successively laminated by PECVD (Plasma Enhanced Chemical Vapor Deposition) method, followed by the above-described inorganic material, a-Si The alc n + a-Si is etched together to form the gate insulating film 119, the semiconductor layer 112, and the ohmic contact layer 113. The gate insulating film 119 and the semiconductor layer 112 have a common wiring and data. It is formed for the purpose of preventing a short circuit in the overlapping region of the electrode and the overlapping region of the data wiring and the gate wiring (b). A metal such as Cr or Mo is deposited thereon by a sputtering method and then etched to form a source electrode 104a, a drain electrode 104b, a data electrode 108 and a data wiring 102, and the source electrode 104a described above. ) And the ohmic contact layer 113 is patterned using the drain electrode 104b as a mask (C). An etching stopper layer may be formed on the semiconductor layer 112 of the thin film transistor to prevent the semiconductor layer 112 from being etched when the ohmic contact layer 113 is etched.
그후, SiOx나 SiNx 등과 같은 무기물 또는 BCB(benzocyclobutane)와 같은 유기물을 적층하고 에칭하여 보호막(112)을 형성한 후(라), 도면으로 나타내지는 않았지만 보호막(122)을 형성한 후 게이트 및 데이터패드를 오픈하기 위하여 1회의 masking공정이 필요하게 된다. 계속해서, 기판 전체에 걸쳐서 제1배향막을 도포한다. 배향막으로는 폴리이미드(polyimide) 폴리아미드(polyamide)계열의 물질또는 폴리실록산(polysiloxanecinnamate), 폴리비닐신아메이트(polyvinylcinnamate) 또는 셀루로즈신아메이트(cellulosecinnamate) 등의 광배향물질을 사용한다. 폴리이미드 또는 폴리아미드 계열의 물질을 배향막으로 사용하는 경우에는 배향막의 배향방향을 결정하기 위해 러빙(rubbing)과 같은 기계적인 방법이 사용되지만, 폴리실록산, 폴리비닐신아메이트 또는 셀루로즈신아메이트 등의 광배향물질을 사용하는 경우에는 자외선과 같은 광을 배향막에 조사하여 배향방향을 결정한다. 특히, 광반응성 배향막에 결정되는 배향방향은 조사되는 광의 편광방향과 같이 광의 고유한 성질에 따라 배향방향이 달라지기 때문에, 기계적인 러빙을 사용했을 때 뱅향막에 먼지나 정전기가 생기는 문제를 해결할 수 있게 된다.Thereafter, an inorganic material such as SiOx or SiNx or an organic material such as benzocyclobutane (BCB) is laminated and etched to form a protective film 112 (D), but not shown, a protective film 122 is formed and then a gate and data pad are formed. One masking process is required to open the. Subsequently, a first alignment film is applied over the entire substrate. As the alignment layer, a polyimide polyamide-based material or a photo-alignment material such as polysiloxanecinnamate, polyvinylcinnamate or cellulosecinnamate is used. When a polyimide or polyamide-based material is used as the alignment layer, a mechanical method such as rubbing is used to determine the alignment direction of the alignment layer. However, light such as polysiloxane, polyvinylcinamate, or cellulose rosincinate is used. In the case of using the alignment material, the alignment direction is determined by irradiating the alignment film with light such as ultraviolet rays. In particular, since the orientation direction determined by the photoreactive alignment layer varies depending on the intrinsic properties of the light, such as the polarization direction of the irradiated light, it is possible to solve the problem of dust or static electricity generated in the bang layer when mechanical rubbing is used. Will be.
이후, 도면으로 나타내지는 않았지만, 제2기판에 Cr이나 CrO등으로이루어진 블랙매트릭스, 컬러필터층, 제2배향막을 형성한 후, 제1기판과 제2기판 사이로 액정을 주입하여 횡전계방식 액정표시소자를 완성한다.Subsequently, although not shown in the drawings, a black matrix, a color filter layer, and a second alignment layer made of Cr, CrO, etc. are formed on the second substrate, and then a liquid crystal is injected between the first substrate and the second substrate to form a transverse electric field liquid crystal display device. To complete.
본 발명의 다른 실시예에서는 상기 공통전극 및 데이터전극과 대향하는 전극 을 제2기판에 형성하여 상하 및 경사전계를 인가하므로써 액정분자의 구동특성을 다양하게 하는 것도 가능하다.In another embodiment of the present invention, it is possible to vary the driving characteristics of the liquid crystal molecules by forming electrodes on the second substrate facing the common electrode and the data electrode to apply the vertical and gradient electric fields.
본 발명에 따르면 반도체층 및 패드영역을 동시에 에칭하는 것에 의해 액정표시소자의 제조 공정을 단축시키는 것이 가능하다.According to the present invention, it is possible to shorten the manufacturing process of the liquid crystal display element by etching the semiconductor layer and the pad region at the same time.
또한, 본 발명은 상기한 바와 같이, 공통전극과 데이터전극을 동일층에 형성하여 상기 전극들 사이에 형성되는 전계가 기판의 표면과 평행하게 하므로써 액정층 내의 액정분자가 기판의 표면과 거의 평행하게 스위칭되어 상대적으로 향상된 시야각특성를 얻을 수 있다.In addition, in the present invention, as described above, the common electrode and the data electrode are formed on the same layer so that the electric field formed between the electrodes is parallel to the surface of the substrate so that the liquid crystal molecules in the liquid crystal layer are almost parallel to the surface of the substrate. By switching, a relatively improved viewing angle characteristic can be obtained.
더욱이, 공통전극과 데이터전극 사이의 게이트절연막을 제거하므로써 액정분자의 스위층속도를 증가시켜 액정분자의 반응속도를 향상시키는 것이 가능하다.Further, by removing the gate insulating film between the common electrode and the data electrode, it is possible to increase the switching layer speed of the liquid crystal molecules to improve the reaction speed of the liquid crystal molecules.
또한, 축적용량배선 형성시에 게이트절연막이 존재하지 않으므로 스토리지전극과 데이터배선을 직접 접속시켜 접촉저항을 낮출 수 있다.In addition, since the gate insulating film does not exist when the storage capacitor wiring is formed, the contact resistance can be lowered by directly connecting the storage electrode and the data wiring.
도 1(a)는 종래 횡전계방식 액정표시소자의 단위화소의 평면도, 도 1(b)는 도 1(a)의 Ⅰ-Ⅰ'선에 따른 단면도.1A is a plan view of a unit pixel of a conventional transverse electric field type liquid crystal display device, and FIG. 1B is a sectional view taken along line II ′ of FIG. 1A.
도 2(a)는 도 1(a)에 나타낸 액정표시소자의 축적용량배선 형성부의 평면도, 도 2(b)는 도 2(a)의 Ⅱ-Ⅱ'선에 따른 단면도.Fig. 2A is a plan view of the storage capacitor wiring forming portion of the liquid crystal display element shown in Fig. 1A, and Fig. 2B is a sectional view taken along the line II-II 'of Fig. 2A.
도 3은 종래 횡전계방식 액정표시소자의 제조방법을 나타내는 도면.3 is a view showing a method of manufacturing a conventional transverse electric field type liquid crystal display device.
도 4(a)는 본 발명의 복합전계방식 액정표시소자의 단위화소의 평면도, 도 4(b)는 도 4(a)의 Ⅲ-Ⅲ'선에 따른 단면도.4 (a) is a plan view of a unit pixel of the composite field type liquid crystal display device of the present invention, and FIG. 4 (b) is a cross-sectional view taken along the line III-III 'of FIG. 4 (a).
도 5(a)는 도 4(a)에 나타낸 액정표시소자의 축적용량배선 형성부의 평면도, 도 5(b)는 도 5(a)의 Ⅳ-Ⅳ'선에 따른 단면도.Fig. 5A is a plan view of the storage capacitor wiring forming portion of the liquid crystal display element shown in Fig. 4A, and Fig. 5B is a sectional view taken along the line IV-IV 'of Fig. 5A.
도 6은 본 발명의 복합전계방식 액정표시소자의 제조방법을 나타내는 도면.6 is a view showing a method for manufacturing a composite field type liquid crystal display device of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
101 : 게이트 배선 102 : 데이터배선 101: gate wiring 102: data wiring
103 : 게이트전극 104a : 소스전극 103: gate electrode 104a: source electrode
104b : 드레인전극 107 : 공통전극 104b: drain electrode 107: common electrode
108 : 데이터전극 110 : 제1기판 108: data electrode 110: first substrate
111 : 제2기판 112 : 반도체층 111: second substrate 112: semiconductor layer
113 : 오믹컨택층 116 : 공통배선 113: ohmic contact layer 116: common wiring
119 : 게이트절연층 122 : 보호막 119: gate insulating layer 122: protective film
125 : 컬러필터층 130 : 액정층 125: color filter layer 130: liquid crystal layer
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| KR970071059A (en) * | 1996-04-04 | 1997-11-07 | 구자홍 | Liquid crystal display |
| KR980003747A (en) * | 1996-06-26 | 1998-03-30 | 김광호 | Planar drive type liquid crystal display device and manufacturing method thereof |
| JPH10301141A (en) * | 1997-04-25 | 1998-11-13 | Matsushita Electric Ind Co Ltd | Liquid crystal display element and its production |
| KR19980083765A (en) * | 1997-05-19 | 1998-12-05 | 구자홍 | Transverse electric field liquid crystal display device |
| KR19980085147A (en) * | 1997-05-28 | 1998-12-05 | 구자홍 | Transverse electric field liquid crystal display device and manufacturing method thereof |
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| KR100360355B1 (en) * | 1994-03-17 | 2003-01-15 | 가부시끼가이샤 히다치 세이사꾸쇼 | Active matrix type liquid crystal display system |
| KR970071059A (en) * | 1996-04-04 | 1997-11-07 | 구자홍 | Liquid crystal display |
| KR980003747A (en) * | 1996-06-26 | 1998-03-30 | 김광호 | Planar drive type liquid crystal display device and manufacturing method thereof |
| JPH10301141A (en) * | 1997-04-25 | 1998-11-13 | Matsushita Electric Ind Co Ltd | Liquid crystal display element and its production |
| KR19980083765A (en) * | 1997-05-19 | 1998-12-05 | 구자홍 | Transverse electric field liquid crystal display device |
| KR19980085147A (en) * | 1997-05-28 | 1998-12-05 | 구자홍 | Transverse electric field liquid crystal display device and manufacturing method thereof |
| KR20000007760A (en) * | 1998-07-07 | 2000-02-07 | 구본준, 론 위라하디락사 | Lcd using composite electric field method and manufacturing method thereof |
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