KR100467781B1 - Thin film capacitor and fabrication method thereof - Google Patents
Thin film capacitor and fabrication method thereof Download PDFInfo
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- KR100467781B1 KR100467781B1 KR10-2002-0082000A KR20020082000A KR100467781B1 KR 100467781 B1 KR100467781 B1 KR 100467781B1 KR 20020082000 A KR20020082000 A KR 20020082000A KR 100467781 B1 KR100467781 B1 KR 100467781B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 40
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 20
- 239000010410 layer Substances 0.000 claims abstract description 150
- 239000010408 film Substances 0.000 claims abstract description 112
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 229910016570 AlCu Inorganic materials 0.000 claims description 13
- 239000003292 glue Substances 0.000 claims description 13
- 239000007769 metal material Substances 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 2
- 229910052719 titanium Inorganic materials 0.000 claims 2
- 239000012212 insulator Substances 0.000 abstract description 10
- 125000005842 heteroatom Chemical group 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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Abstract
금속/ 절연체/ 금속 (MIM) 구조의 박막 커패시터 및 그 제조방법에 관한 것으로, 그 목적은 MIM 커패시터 구조에서 절연체층인 질화막을 중심으로 제1전극층과 제2전극층의 거리를 누설전류가 발생하지 않을 정도로 이격시키는 것이다. 이를 위해 본 발명에서는, 반도체 기판의 구조물 상부의 하부절연막 상에 제1전극층을 형성하는 단계; 제1전극층 상에 소정폭의 산화막을 형성하는 단계; 산화막 및 제1전극층 상에 이종막을 증착하고, 이종막을 수직식각하여 산화막의 측벽에 남김으로써 사이드월을 형성하는 단계; 산화막을 제거하여 사이드월의 내부를 통해 제1전극층을 노출시키는 단계; 사이드월을 통해 노출된 제1전극층 및 사이드월 상에 유전체층 및 제2전극층을 순차적으로 형성하는 단계; 유전체층, 제2전극층, 및 제1전극층을 포함하여 하부절연막의 상부전면에 층간절연막을 형성하는 단계; 층간절연막을 선택적으로 식각하여 제2전극층 및 제1전극층의 일부분을 노출시키는 비아를 형성하는 단계; 비아의 내부 금속물질로 매립하는 단계를 포함하여 박막 커패시터를 제조한다.The present invention relates to a thin film capacitor having a metal / insulator / metal (MIM) structure and a method of manufacturing the same. It is spaced apart. To this end, in the present invention, forming a first electrode layer on the lower insulating film on the upper structure of the semiconductor substrate; Forming an oxide film having a predetermined width on the first electrode layer; Depositing a hetero film on the oxide film and the first electrode layer, and forming a sidewall by vertically etching the hetero film to leave a sidewall of the oxide film; Removing the oxide film to expose the first electrode layer through the interior of the sidewalls; Sequentially forming a dielectric layer and a second electrode layer on the first electrode layer and the sidewall exposed through the sidewall; Forming an interlayer insulating film on an upper surface of the lower insulating film, including a dielectric layer, a second electrode layer, and a first electrode layer; Selectively etching the interlayer insulating film to form vias exposing the second electrode layer and a portion of the first electrode layer; A thin film capacitor is fabricated, including the step of burying the via metal inside the via.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속/ 절연체/ 금속 (MIM) 구조의 박막 커패시터를 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a thin film capacitor having a metal / insulator / metal (MIM) structure.
최근 고속 동작을 요구하는 아날로그 회로에서는 고용량의 커패시터를 구현하기 위한 반도체 소자 개발이 진행 중에 있다. 일반적으로, 커패시터가 다결정실리콘(polysilicon), 절연체(insulator), 및 다결정실리콘(polysilicon)이 적층된 PIP 구조일 경우에는 상부전극 및 하부전극을 도전성 다결정실리콘으로 사용하기 때문에 상,하부전극과 유전체 박막 계면에서 산화반응이 일어나 자연산화막이 형성되어 전체커패시턴스의 크기가 줄어들게 되는 단점이 있다.Recently, in an analog circuit requiring high-speed operation, development of a semiconductor device for implementing a high capacity capacitor is underway. In general, when the capacitor is a PIP structure in which polysilicon, an insulator, and polysilicon are stacked, the upper and lower electrodes and the dielectric thin film are used because the upper electrode and the lower electrode are used as conductive polycrystalline silicon. Oxidation reaction occurs at the interface to form a natural oxide film has the disadvantage of reducing the size of the total capacitance.
이를 해결하기 위해 커패시터의 구조를 금속/절연체/실리콘 (metal/insulator/silicon : MIS) 또는 금속/절연체/금속(metal/insulator/metal : MIM)으로 변경하게 되었는데, 그 중에서도 MIM 구조의 커패시터는 비저항이 작고 내부에 공핍(deplection)에 의한 기생 커패시턴스가 없기 때문에 고성능 반도체 장치에 주로 이용되고 있다.To solve this problem, the structure of the capacitor was changed to metal / insulator / silicon (MIS) or metal / insulator / metal (MIM). Because of its small size and no parasitic capacitance due to depletion inside, it is mainly used for high performance semiconductor devices.
그러면, 종래 반도체 소자 제조방법에 따라 MIM 구조의 박막 커패시터를 제조하는 방법에 대해 첨부된 도면을 참조하여 설명한다. 도 1a 내지 1d는 종래 방법에 따라 박막 커패시터를 제조하는 방법을 도시한 단면도이다.Next, a method of manufacturing a thin film capacitor having a MIM structure according to a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings. 1A to 1D are cross-sectional views illustrating a method of manufacturing a thin film capacitor according to a conventional method.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판(1)의 상부에 통상의 반도체 소자 공정을 진행하고 피에스지(PSG : phosphosilicateglass) 등의 산화막으로 이루어진 하부절연막(2)을 형성한 다음, 하부절연막(2) 상에 제1 Ti베리어층(3), Cu가 함유된 Al으로 이루어진 AlCu 하부배선(4), 제1 Ti글루층(5) 및 제1 TiN반사방지막(6)을 차례로 형성한다.First, as shown in FIG. 1A, a normal semiconductor device process is performed on an upper portion of the semiconductor substrate 1, and a lower insulating film 2 made of an oxide film such as PSG (PSG) is formed, and then a lower insulating film is formed. On (2), a first Ti barrier layer 3, an AlCu lower interconnection 4 made of Al containing Cu, a first Ti glue layer 5, and a first TiN antireflection film 6 are sequentially formed.
이 때, 제1 Ti베리어층(3), AlCu 하부배선(4), 제1 Ti글루층(5) 및 제1 TiN반사방지막(6)이 MIM 커패시터에서 제1전극층(M1)에 해당된다.In this case, the first Ti barrier layer 3, the AlCu lower interconnection 4, the first Ti glue layer 5, and the first TiN antireflection film 6 correspond to the first electrode layer M1 in the MIM capacitor.
이어서, TiN 반사방지막(6) 상에 MIM 커패시터의 절연체층에 해당하는 질화막(7)을 약 600Å 정도의 두께로 형성한다.Subsequently, a nitride film 7 corresponding to the insulator layer of the MIM capacitor is formed on the TiN antireflection film 6 to a thickness of about 600 kPa.
다음, 질화막(7) 상에 제2 Ti베리어층(8), Cu가 함유된 Al으로 이루어진 AlCu 상부배선(9), 제2 Ti글루층(10) 및 제2 TiN반사방지막(11)을 차례로 형성한다.Next, the second Ti barrier layer 8, the AlCu upper wiring 9 made of Al containing Cu, the second Ti glue layer 10, and the second TiN antireflection film 11 are sequentially formed on the nitride film 7. Form.
이 때, 제2 Ti베리어층(8), AlCu 상부배선(9), 제2 Ti글루층(10) 및 제2 TiN반사방지막(11)이 MIM 커패시터에서 제2전극층(M2)에 해당된다.In this case, the second Ti barrier layer 8, the AlCu upper wiring 9, the second Ti glue layer 10, and the second TiN antireflection film 11 correspond to the second electrode layer M2 in the MIM capacitor.
다음, 도 1b에 도시된 바와 같이, 제2 TiN반사방지막(11), 제2 Ti글루층(10), AlCu 상부배선(9), 및 제2 Ti베리어층(8)을 선택적으로 식각하여 패터닝한다.Next, as shown in FIG. 1B, the second TiN antireflection film 11, the second Ti glue layer 10, the AlCu upper wiring 9, and the second Ti barrier layer 8 are selectively etched and patterned. do.
다음, 도 1c에 도시된 바와 같이, 이웃하는 금속배선 간 갭을 매립하도록 층간절연막(12)을 20000Å 정도로 두껍게 증착하고 화학기계적 연마하여 제2 TiN반사방지막(11) 상부로 층간절연막(12)이 3000Å 정도 남도록 하여 상면을 평탄화한 후, 평탄화된 층간절연막(12)의 상면에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 영역을 노출시키는 감광막 패턴(미도시)을 형성한다.Next, as shown in FIG. 1C, the interlayer insulating film 12 is deposited to a thickness of about 20000 Å so as to fill the gap between neighboring metal wirings, and chemically mechanically polished so that the interlayer insulating film 12 is placed over the second TiN antireflection film 11. After the top surface is planarized to leave about 3000 GPa, a photoresist film is applied to the top surface of the planarized interlayer insulating film 12, exposed to light, and developed to form a photoresist pattern (not shown) exposing a predetermined region to the via.
이어서, 감광막 패턴을 마스크로 하여 상면이 노출된 층간절연막(12)을 건식식각하여 제2 TiN반사방지막(11) 및 제1 TiN반사방지막(6)의 표면을 개방하는 소정폭의 비아홀(100)을 형성한 다음, 제2감광막 패턴을 제거하고 세정공정을 수행한다.Subsequently, a via hole 100 having a predetermined width opening the surface of the second TiN antireflection film 11 and the first TiN antireflection film 6 by dry etching the interlayer insulating film 12 having the upper surface exposed using the photoresist pattern as a mask. After the formation, the second photoresist pattern is removed and a cleaning process is performed.
다음, 도 1d에 도시된 바와 같이, 비아홀(100)의 내벽을 포함하여 층간절연막(12)의 상부 전면에 베리어금속막(13)을 증착한 후, 베리어금속막(13) 상에 텅스텐(14)을 증착하여 비아홀(100)의 내부를 완전히 매립한다.Next, as shown in FIG. 1D, the barrier metal film 13 is deposited on the entire upper surface of the interlayer insulating film 12 including the inner wall of the via hole 100, and then tungsten 14 is deposited on the barrier metal film 13. ) To completely fill the inside of the via hole 100.
이어서, 층간절연막(12)의 상면이 노출될 때까지 화학기계적 연마하여 상면을 평탄화시킨다.Subsequently, the upper surface is planarized by chemical mechanical polishing until the upper surface of the interlayer insulating film 12 is exposed.
상기한 바와 같이, 종래의 MIM 커패시터 구조에서는 절연체층인 얇은질화막(7)을 중심으로 제1전극층(M1)과 제2전극층(M2)의 거리가 가까워서 피뢰침 효과 등에 의한 누설전류가 발생하는 문제점이 있었다.As described above, in the conventional MIM capacitor structure, the distance between the first electrode layer M1 and the second electrode layer M2 is close to the thin nitride film 7 serving as the insulator layer, so that a leakage current may occur due to the lightning rod effect. there was.
이러한 누설전류는 소자의 오동작을 유발하고, 심할 경우 소자를 파괴시키는 문제점이 있었다.This leakage current causes a malfunction of the device and, in severe cases, there is a problem of destroying the device.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 MIM 커패시터 구조에서 절연체층인 질화막을 중심으로 제1전극층과 제2전극층의 거리를 누설전류가 발생하지 않을 정도로 이격시키는 것이다.The present invention is to solve the above problems, the object is to space the distance between the first electrode layer and the second electrode layer around the nitride film as the insulator layer in the MIM capacitor structure to the extent that no leakage current occurs.
도 1a 내지 1d는 종래 방법에 따른 박막 커패시터 제조 방법을 도시한 단면도이고,1A to 1D are cross-sectional views illustrating a method of manufacturing a thin film capacitor according to a conventional method,
도 2a 내지 도 2e는 본 발명에 따른 박막 커패시터 제조 방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film capacitor according to the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 제1전극층 상에 소정폭의 산화막을 형성하고, 그 위에 실리콘나이트라이드를 증착한 후 수직식각하여 산화막의 측벽에 실리콘나이트라이드 사이드월을 형성하며, 산화막을 제거한 후 사이드월의 내부를 통해 노출된 제1전극층 및 사이드월 상에 유전체층 및 제2전극층을 순차적으로 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, an oxide film having a predetermined width is formed on the first electrode layer, silicon nitride is deposited thereon, and the silicon nitride sidewall is formed on the sidewall of the oxide film by vertical etching. After removing the oxide film, the dielectric layer and the second electrode layer are sequentially formed on the first electrode layer and the sidewall exposed through the inside of the sidewall.
즉, 본 발명에 따른 박막 커패시터 제조 방법은, 반도체 기판의 구조물 상부의 하부절연막 상에 제1전극층을 형성하는 단계; 제1전극층 상에 소정폭의 산화막을 형성하는 단계; 산화막 및 제1전극층 상에 이종막을 증착하고, 이종막을 수직식각하여 산화막의 측벽에 남김으로써 사이드월을 형성하는 단계; 산화막을 제거하여 사이드월의 내부를 통해 제1전극층을 노출시키는 단계; 사이드월을 통해 노출된 제1전극층 및 사이드월 상에 유전체층 및 제2전극층을 순차적으로 형성하는 단계;유전체층, 제2전극층, 및 제1전극층을 포함하여 하부절연막의 상부전면에 층간절연막을 형성하는 단계; 층간절연막을 선택적으로 식각하여 제2전극층 및 제1전극층의 일부분을 노출시키는 비아를 형성하는 단계; 비아의 내부 금속물질로 매립하는 단계를 포함하여 이루어진다.That is, the method of manufacturing a thin film capacitor according to the present invention includes forming a first electrode layer on a lower insulating layer on an upper portion of a structure of a semiconductor substrate; Forming an oxide film having a predetermined width on the first electrode layer; Depositing a hetero film on the oxide film and the first electrode layer, and forming a sidewall by vertically etching the hetero film to leave a sidewall of the oxide film; Removing the oxide film to expose the first electrode layer through the interior of the sidewalls; Sequentially forming a dielectric layer and a second electrode layer on the first electrode layer and the sidewall exposed through the sidewall; including an dielectric layer, a second electrode layer, and a first electrode layer to form an interlayer insulating layer on an upper surface of the lower insulating layer. step; Selectively etching the interlayer insulating film to form vias exposing the second electrode layer and a portion of the first electrode layer; Filling the inner metal material of the via.
여기서, 제1전극층 및 제2전극층으로는 각각, 하부Ti베리어층, AlCu 배선, Ti글루층 및 TiN반사방지막을 순차적으로 형성한다.Here, the lower Ti barrier layer, the AlCu wiring, the Ti glue layer, and the TiN antireflection film are sequentially formed as the first electrode layer and the second electrode layer, respectively.
산화막은 500-900Å의 두께로 형성하는 것이 바람직하다.The oxide film is preferably formed to a thickness of 500-900 kPa.
사이드월을 형성할 때에는, 산화막을 포함하여 제1전극층의 상부 전면에 실리콘나이트라이드막을 800-1200Å의 두께로 형성한 후, 실리콘나이트라이드막을 수직식각하여 산화막의 측벽에만 실리콘나이트라이드막을 남김으로써 사이드월을 형성하는 것이 바람직하다.In forming the sidewalls, the silicon nitride film is formed on the entire upper surface of the first electrode layer including the oxide film in a thickness of 800-1200 kPa, and the silicon nitride film is vertically etched to leave the silicon nitride film only on the sidewall of the oxide film. It is preferable to form the month.
이하, 본 발명의 일 실시예에 따른 박막 커패시터 및 그 제조 방법에 대해 상세히 설명한다.Hereinafter, a thin film capacitor and a method of manufacturing the same according to an embodiment of the present invention will be described in detail.
본 발명의 일 실시예에 따라 제조된 박막 커패시터는 도 2e에 도시되어 있으며, 이에 도시된 바와 같이, 박막 커패시터는 개별 소자가 형성된 반도체 기판의 구조물(51) 상에 형성되는데, 반도체 기판의 구조물(51)의 상에는 하부절연막(52)이 형성되어 있다.A thin film capacitor manufactured according to an embodiment of the present invention is shown in FIG. 2E, and as shown therein, the thin film capacitor is formed on the structure 51 of the semiconductor substrate on which the individual elements are formed. A lower insulating film 52 is formed on 51.
하부절연막(52) 상에는 MIM 커패시터 구조에서의 제1전극층(M1)이 형성되어 있고, 제1전극층(M1)의 상면에는 사이드월(58)이 형성되어 있으며, 사이드월(58)의 내부를 통해서는 소정폭의 제1전극층(M1)이 노출되어 있다.The first electrode layer M1 having the MIM capacitor structure is formed on the lower insulating layer 52, and sidewalls 58 are formed on the upper surface of the first electrode layer M1, and are formed through the interior of the sidewalls 58. The first electrode layer M1 having a predetermined width is exposed.
여기서, 제1전극층(M1)은 다층구조로 되어 있는데, 일 예로서는 도 2e에 도시된 바와 같이, 제1 Ti베리어층(53), Cu가 함유된 Al으로 이루어진 제1 AlCu하부배선(54), 제1 Ti글루층(55) 및 제1 TiN반사방지막(56)으로 이루어질 수 있다.Here, the first electrode layer M1 has a multi-layer structure. As an example, as shown in FIG. 2E, the first Ti barrier layer 53, the first AlCu lower wiring 54 made of Al containing Cu, The first Ti glue layer 55 and the first TiN antireflection film 56 may be formed.
이 경우 사이드월(58)의 내부를 통해서는 제1 TiN반사방지막(56)이 노출되어 있다.In this case, the first TiN antireflection film 56 is exposed through the interior of the sidewall 58.
사이드월(58)의 내부를 통해 노출된 제1 TiN반사방지막(56) 및 사이드월(58) 상에는 유전체층(59)이 소정폭으로 형성되어 있다. 이 때 유전체층(59)은 MIM 커패시터 구조에서 절연체층에 해당한다.A dielectric layer 59 is formed to a predetermined width on the first TiN antireflection film 56 and the sidewall 58 exposed through the sidewall 58. At this time, the dielectric layer 59 corresponds to an insulator layer in the MIM capacitor structure.
사이드월(58) 및 유전체층(59)은 실리콘나이트라이드로 이루어질 수 있다.Sidewall 58 and dielectric layer 59 may be formed of silicon nitride.
유전체층(59) 상에는 MIM 구조의 커패시터에서의 제2전극층(M2)이 유전체층(59)과 동일한 소정폭으로 형성되어 있다.On the dielectric layer 59, the second electrode layer M2 in the capacitor of the MIM structure is formed with the same predetermined width as the dielectric layer 59.
여기서 제2전극층(M2)은 제1전극층(M1)과 마찬가지로 다층구조로 되어 있는데, 일 예로서는 도 2e에 도시된 바와 같이, 제2 Ti베리어층(60), Cu가 함유된 Al으로 이루어진 AlCu 상부배선(61), 제2 Ti글루층(62) 및 제2 TiN반사방지막(63)으로 이루어질 수 있다.Here, the second electrode layer M2 has a multi-layered structure similar to the first electrode layer M1. For example, as shown in FIG. 2E, the second Ti barrier layer 60 is formed of Al containing Cu containing Al. The wiring 61, the second Ti glue layer 62, and the second TiN antireflection film 63 may be formed.
그러면, 상기한 바와 같은 본 발명의 박막 커패시터를 제조하는 방법에 대해 상세히 설명한다.Then, a method of manufacturing the thin film capacitor of the present invention as described above will be described in detail.
도 2a 내지 도 2e는 본 발명에 따른 박막 커패시터 제조 방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film capacitor according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판의 상부에 통상의 반도체 소자공정을 진행하여 개별 소자가 형성된 반도체 기판의 구조물(51)을 형성하고, 반도체 기판의 구조물(51) 상에 피에스지(PSG) 등의 산화막으로 이루어진 하부절연막(52)을 형성한다.First, as shown in FIG. 2A, a semiconductor device process is performed on an upper portion of a semiconductor substrate to form a structure 51 of a semiconductor substrate on which individual elements are formed. A lower insulating film 52 made of an oxide film such as PSG) is formed.
이어서, 하부절연막(52) 상에 제1 Ti베리어층(53), Cu가 함유된 Al으로 이루어진 AlCu하부배선(54), 제1 Ti글루층(55) 및 제1 TiN반사방지막(56)을 차례로 형성하여 MIM 커패시터 구조에서의 제1전극층(M1)을 형성한다.Subsequently, the first Ti barrier layer 53, the AlCu lower wiring 54 made of Al containing Cu, the first Ti glue layer 55, and the first TiN antireflection film 56 are disposed on the lower insulating layer 52. The first electrode layer M1 in the MIM capacitor structure is formed sequentially.
이 때 하부배선(54)은 반드시 AlCu로 형성할 필요는 없으며 Al을 형성할 수도 있다.In this case, the lower wiring 54 does not necessarily need to be formed of AlCu, but may also form Al.
이어서, 제1 TiN반사방지막(56) 상에 산화막(57)을 500-900Å의 두께로 증착한 후 커패시터로 예정된 영역만큼을 남기도록 선택적 식각하여 소정폭으로 남긴다.Subsequently, an oxide film 57 is deposited on the first TiN antireflection film 56 to a thickness of 500 to 900 Å, and then selectively etched to leave only a predetermined region as a capacitor, thereby leaving a predetermined width.
다음, 도 2b에 도시된 바와 같이, 산화막(57)을 포함하여 제1 TiN반사방지막(56)의 상부 전면에 실리콘나이트라이드막을 800-1200Å 두께로 증착한 후, 이를 별도의 포토리소그래피 공정없이 수직식각하여, 실리콘나이트라이드를 산화막(57)의 측벽에만 남김으로써 사이드월(58)을 형성한다.Next, as shown in FIG. 2B, after depositing a silicon nitride film 800-1200 mm thick on the entire upper surface of the first TiN antireflection film 56 including the oxide film 57, it is vertical without a separate photolithography process. By etching, the silicon nitride is left only on the sidewall of the oxide film 57 to form the sidewalls 58.
다음, 산화막과 질화막의 식각비를 이용하여 습식식각으로 산화막(57)을 제거하여 도 2c에 도시된 바와 같이 실리콘나이트라이드 사이드월(58)만을 남긴다.Next, the oxide film 57 is removed by wet etching using the etch ratio between the oxide film and the nitride film, leaving only the silicon nitride sidewall 58 as shown in FIG. 2C.
다음, 도 2d에 도시된 바와 같이, 사이드월(58)을 포함하여 제1 TiN반사방지막(56)의 상부 전면에 실리콘나이트라이드 유전체층(59)을 400-800Å의 두께로 형성한다. 이 때 실리콘나이트라이드 유전체층(59)은 MIM 커패시터 구조에서 절연체층에 해당한다.Next, as shown in FIG. 2D, the silicon nitride dielectric layer 59 is formed to a thickness of 400-800 에 on the entire upper surface of the first TiN antireflection film 56 including the sidewalls 58. At this time, the silicon nitride dielectric layer 59 corresponds to an insulator layer in the MIM capacitor structure.
이어서 실리콘나이트라이드 유전체층(59) 상에 제2 Ti베리어층(60), Cu가 함유된 Al으로 이루어진 AlCu 상부배선(61), 제2 Ti글루층(62) 및 제2 TiN반사방지막(63)을 차례로 형성하여 MIM 커패시터 구조에서의 제2전극층(M2)을 형성한다.Subsequently, a second Ti barrier layer 60, an AlCu upper interconnection 61 made of Al containing Cu, a second Ti glue layer 62, and a second TiN antireflection film 63 are formed on the silicon nitride dielectric layer 59. Are sequentially formed to form the second electrode layer M2 in the MIM capacitor structure.
다음, 도 2d에 도시된 바와 같이, 제2 TiN반사방지막(62) 상에 감광막을 도포하고 노광 및 현상하여 사이드월(58) 및 그 내부 상의 제2전극층(M2)을 노출시키는 감광막 패턴(미도시)을 형성한 후, 이를 마스크로 하여 상면이 노출된 제2 TiN반사방지막(63) 및 그 하부의 제2 Ti글루층(62), AlCu 상부배선(61), 제2 Ti베리어층(60)을 식각한다. 이어서 감광막 패턴을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2D, a photoresist film is coated on the second TiN antireflection film 62, exposed, and developed to expose the sidewall 58 and the second electrode layer M2 therein (not shown). After the formation of the Si), the second TiN antireflection film 63 having an upper surface exposed thereon as a mask, the second Ti glue layer 62 below, the AlCu upper wiring 61, and the second Ti barrier layer 60 are formed. Etch). Subsequently, the photoresist pattern is removed and a cleaning process is performed.
이후에는, 층간절연막 형성 공정, 비아 형성 공정, 비아 매립 공정 등의 통상적인 반도체 소자 제조 공정을 수행한다.Thereafter, a conventional semiconductor device manufacturing process such as an interlayer insulating film forming process, a via forming process, a via filling process, and the like are performed.
즉, 제2전극층(M2) 및 제1전극층(M1)을 포함하여 하부절연막(52)의 상부 전면에 층간절연막을 두껍게 형성하여 금속배선 간 갭을 완전히 매립한 후, 화학기계적 연마하여 상면을 평탄화한다.That is, a thick interlayer insulating film is formed on the entire upper surface of the lower insulating film 52 including the second electrode layer M2 and the first electrode layer M1 to completely fill the gap between metal wirings, and then chemically mechanically polish the top surface. do.
이어서, 평탄화된 층간절연막의 상면에 감광막을 도포하고 노광 및 현상하여 제2전극층(M2) 및 제1전극층(M1) 상부에 위치하는 층간절연막의 소정영역을 각각 노출시키는 감광막 패턴(미도시)을 형성한 후, 감광막 패턴을 마스크로 하여 상면이 노출된 층간절연막을 건식식각함으로써, 제2전극층(M2) 및 제1전극층(M1)의 상면을 개방하는 소정폭의 비아를 형성한 다음, 감광막 패턴을 제거하고 세정공정을수행한다.Subsequently, a photoresist film is coated on the top surface of the planarized interlayer insulation film, and the photoresist pattern (not shown) exposing and developing the photoresist film to expose predetermined regions of the interlayer insulation film positioned on the second electrode layer M2 and the first electrode layer M1, respectively. After forming, dry etching the interlayer insulating film having the upper surface exposed using the photosensitive film pattern as a mask to form vias having a predetermined width to open the upper surfaces of the second electrode layer M2 and the first electrode layer M1, and then the photosensitive film pattern. Is removed and the cleaning process is performed.
이어서, 비아의 내벽을 포함하여 층간절연막의 상부 전면에 베리어금속막을 증착하고, 베리어금속막 상에 텅스텐을 증착하여 비아의 내부를 완전히 매립한 다음, 층간절연막의 상면이 노출될 때까지 화학기계적 연마하여 상면을 평탄화시킨다.Subsequently, a barrier metal film is deposited on the entire upper surface of the interlayer insulating film including the inner wall of the via, and tungsten is deposited on the barrier metal film to completely fill the inside of the via, and then chemical mechanical polishing until the top surface of the interlayer insulating film is exposed. To flatten the top surface.
이 때, 베리어금속막(31)으로는 대략 200Å 두께의 Ti막과 대략 100Å 두께의 TiN막을 차례로 형성할 수 있다.At this time, the barrier metal film 31 can be formed with a Ti film having a thickness of approximately 200 ms and a TiN film having a thickness of approximately 100 ms.
상술한 바와 같이, 본 발명에서는 MIM 커패시터 구조의 제1전극층 상에 소정폭의 산화막을 형성하고, 그 위에 실리콘나이트라이드를 증착한 후 수직식각하여 산화막의 측벽에 실리콘나이트라이드 사이드월을 형성하며, 산화막을 제거한 후 사이드월의 내부를 통해 노출된 제1전극층 및 사이드월 상에 유전체층 및 제2전극층을 순차적으로 형성함으로써, 결과적으로 유전체층을 중심으로 하여 제1전극층과 제2전극층의 거리를 원하는 정도로 이격시킬 수 있으며, 따라서 누설전류를 방지하는 효과가 있다.As described above, in the present invention, an oxide film having a predetermined width is formed on the first electrode layer of the MIM capacitor structure, silicon nitride is deposited thereon, and the silicon nitride sidewall is formed on the sidewall of the oxide film by vertical etching. After the oxide film is removed, the dielectric layer and the second electrode layer are sequentially formed on the first electrode layer and the sidewall exposed through the inside of the sidewall. As a result, the distance between the first electrode layer and the second electrode layer centering on the dielectric layer is desired. It can be spaced apart, thereby preventing the leakage current.
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