KR100447729B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100447729B1 KR100447729B1 KR10-2002-0024396A KR20020024396A KR100447729B1 KR 100447729 B1 KR100447729 B1 KR 100447729B1 KR 20020024396 A KR20020024396 A KR 20020024396A KR 100447729 B1 KR100447729 B1 KR 100447729B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 고주파 회로영역의 MIM(Metal Insulator Metal) 커패시터 형성시 로직영역의 게이트 전극을 동시에 형성시킴으로써 공정을 단순화하고 고온의 다양한 열처리공정을 실시하여 커패시터의 누설전류를 줄일 수 있는 반도체 장치의 제조 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In the formation of a metal insulator metal (MIM) capacitor in a high frequency circuit region, the gate electrode of a logic region is simultaneously formed to simplify the process and perform various heat treatment processes at a high temperature, thereby preventing leakage of the capacitor It provides a method for manufacturing a semiconductor device that can be reduced.
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 특히 SoC(System on Chip)소자의 MOS 캐패시터와 금속 절연물 금속구조의(Metal Insulator Metal; 이하 'MIM'이라함) 캐패시터를 동시에 형성할 수 있는 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of simultaneously forming a MOS capacitor of a SoC (System on Chip) device and a capacitor of a metal insulator metal (hereinafter, referred to as 'MIM'). It relates to a method for producing.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 장치의 제조 방법을 설명하기 위한 단면도들 이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1a를 참조하면, 소정의 구조가 형성된 하지층(10) 상에 제 1 금속층(20)과 제 1 층간 절연막(30)을 순차적으로 증착하고 듀얼 다마신(Dual damascene) 공정을 이용하여 비아홀을 형성한 후 TiN, TaN 및 Ta를 이용한 얇은 두께의 배리어(Barrier)용 제 2 금속층(40)을 형성한다.Referring to FIG. 1A, a first metal layer 20 and a first interlayer insulating layer 30 are sequentially deposited on a base layer 10 on which a predetermined structure is formed, and a via hole is formed using a dual damascene process. After the formation, the second metal layer 40 for barrier having a thin thickness using TiN, TaN, and Ta is formed.
도 1b를 참조하면, 상술한 공정이 진행된 전체 구조 상부에 제 3 금속층(50)을 형성한 후 상기 배리어용 제 2 금속층(40)을 식각정지층으로 하는 화학적 기계적 연마(Chemical Mechanical Polishing; CMP)를 이용한 평탄화 공정을 실시한다. 다음으로, 그 상부에 배리어용 제 4 금속층(60)을 형성한다. 제 3 금속층(50)으로는 구리(Cu)를 비아홀이 매립될 정도의 두께로 증착하고, 배리어 제 4 금속층(60)으로는 TiN, Ta 및 TaN을 이용한다.Referring to FIG. 1B, after the third metal layer 50 is formed on the entire structure in which the above-described process is performed, chemical mechanical polishing (CMP) using the barrier second metal layer 40 as an etch stop layer. The planarization process using the following is performed. Next, the fourth metal layer 60 for barrier is formed on the upper side. As the third metal layer 50, copper (Cu) is deposited to a thickness such that a via hole is filled, and as the barrier fourth metal layer 60, TiN, Ta, and TaN are used.
도 1c 및 도 1d를 참조하면, 전체 구조 상부에 유전체(dielectric)막(70)과상부 전극(electrode)으로 사용될 제 5 금속층(80)을 형성한 후 MIM마스크를 이용한 패터닝공정을 실시하여 제 5 금속층(80)과 유전체막(70)을 순차적으로 패터닝한다. 이때 유전체막(70)으로는 유전상수가 높은 Ta2O5또는 HfO5를 사용하고, 상부 전극용 제 5 금속층(80)으로는 TiN, Ta 및 TaN을 사용한다. 그 상부에 제 2 층간 절연막(90)을 형성한 후 상기의 층간 절연막(90)을 패터닝하여 콘택홀(contact hole)을 형성하고, 층간 절연막(90) 상에 제 6 금속층(100) 패턴을 형성하여 MIM 캐패시터를 형성한다.1C and 1D, a fifth metal layer 80 to be used as a dielectric film 70 and an upper electrode is formed on the entire structure, and then a patterning process using a MIM mask is performed to form a fifth metal layer 80. The metal layer 80 and the dielectric film 70 are sequentially patterned. In this case, Ta 2 O 5 or HfO 5 having a high dielectric constant is used as the dielectric film 70, and TiN, Ta, and TaN are used as the fifth metal layer 80 for the upper electrode. After forming the second interlayer insulating film 90 thereon, the interlayer insulating film 90 is patterned to form contact holes, and a sixth metal layer 100 pattern is formed on the interlayer insulating film 90. To form a MIM capacitor.
종래의 기술을 이용하여 MIM 캐패시터를 형성하기 위해서는 메탈라인 형성 후, MIM 유전체막를 증착하게 된다. 그런데, 통상의 MIM 유전체막 증착시에는 약 500 내지 800℃의 열처리 공정이 수행됨으로, 메탈라인이 구리를 이용하여 형성되는 경우에는 열에 의한 구리의 확산계수가 크기 때문에 500℃이상의 고온열처리 공정을 실시하게 되면 메탈라인이 열에 의한 손상을 받게됨으로써 다양한 열처리를 할 수 없는 문제점이 있다.In order to form a MIM capacitor using a conventional technique, after forming a metal line, a MIM dielectric film is deposited. However, when the MIM dielectric film is deposited, a heat treatment process of about 500 to 800 ° C. is performed. When the metal line is formed using copper, a high temperature heat treatment process of 500 ° C. or higher is performed because the diffusion coefficient of copper by heat is large. If the metal line is damaged by heat, there is a problem that can not be various heat treatment.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 메탈라인 형성전에 MIM 캐패시터를 제조하게됨으로써 다양한 열처리 공정을 수행하여 누설전류 특성을 향상시킬 수 있는 반도체 장치의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving leakage current characteristics by performing various heat treatment processes by manufacturing a MIM capacitor before forming a metal line in order to solve the above problems.
또한, MIM의 하부 전극을 형성한 후 게이트 유전체막과 MIM의 유전체막 그리고 게이트 전극과 MIM 상부전극을 동시에 형성함으로써 공정의 단순화를 가져올 수 있는 반도체 장치의 제조 방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying a process by forming a gate dielectric film, a MIM dielectric film, and a gate electrode and a MIM upper electrode at the same time after forming the bottom electrode of the MIM.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 장치의 제조 방법을 설명하기 위한 단면도들 이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 및 도 2d는 본 발명에 따른 반도체 장치의 제조 방법을 설명하기 위한 단면도들 이다.2A and 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 하지층 30, 90, 220 : 절연막10: base layer 30, 90, 220: insulating film
70, 290, 292 : 유전체막 210, 230 : 실리콘층70, 290, 292: dielectric film 210, 230: silicon layer
240 : SOI 웨이퍼 250 : 소자분리막240: SOI wafer 250: device isolation film
246, 248 : 트랜치 260 : 패드 산화막246, 248: trench 260: pad oxide film
270 : 질화막 294 : 게이트 산화막270: nitride film 294: gate oxide film
20, 40, 50, 60, 80, 100, 280, 300, 302 : 금속층20, 40, 50, 60, 80, 100, 280, 300, 302: metal layer
304 : 게이트 전극 306 : MIM 커패시터304: gate electrode 306: MIM capacitor
상술한 기술적 과제를 달성하기 위하여 본 발명은 반도체 기판상에 패드 산화막 및 질화막을 순차적으로 형성하는 단계와, 상기 반도체 기판을 로직영역과 고주파 회로영역으로 구분하는 소자 분리막을 형성하는 단계와, 상기 로직영역 및 고주파 회로영역 상부의 상기 질화막을 제거하는 단계와, 상기 로직영역 상부의 상기 패드 산화막을 제거하는 단계와, 상기 고주파 회로영역에 잔류하는 상기 패드 산화막 상에 하부전극을 형성하는 단계와, 전체구조 상부에 유전체막 및 도전막을 순차적으로 형성하는 단계, 및 패터닝 공정을 실시하여 상기 로직영역에는 게이트 전극을 형성하고, 상기 고주파 회로영역에는 상부전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of sequentially forming a pad oxide film and a nitride film on a semiconductor substrate, forming a device isolation layer that divides the semiconductor substrate into a logic region and a high frequency circuit region, and the logic. Removing the nitride film over the region and the high frequency circuit region, removing the pad oxide film over the logic region, forming a lower electrode on the pad oxide film remaining in the high frequency circuit region, and And sequentially forming a dielectric film and a conductive film on the structure, and performing a patterning process to form a gate electrode in the logic region and an upper electrode in the high frequency circuit region. It provides a method for producing.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 더욱 상세히 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.
도 2a 및 도 2d는 본 발명에 따른 반도체 장치의 제조 방법을 설명하기 위한단면도들 이다.2A and 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 2a를 참조하면, 반도체 기판으로 실리콘(Si)웨이퍼, 게르마늄(Ge)웨이퍼, 실리콘 게르마늄(SiGe)웨이퍼 및 실리콘 온 인술레이터(Silicon On Insulator; SOI)웨이퍼중 적어도 어느 하나인 것을 특징으로 하며, 특별히 한정되지 않고 반도체 소자를 제조할 수 있는 모든 기판을 포함한다. 특히 본 실시예에서는 제 1 실리콘(210), 절연막(220)과 제 2 실리콘(230)이 적층형으로 구성된 SOI 웨이퍼(240)를 사용하여 후술되는 고주파 회로영역(B)에서 발생하는 기생전류로 인해 로직영역(A)의 특성이 변화되는 것을 최대한 방지한다. 상술한 SOI 웨이퍼(240) 상에 패드 산화막(Oxide; 260)과 질화막(Nitride; 270)을 순차적으로 증착한다. 다음으로 소자 분리막을 형성하여 SOI 웨이퍼(240)를 활성영역과 필드영역으로 정의하고 또한 로직(Logic)영역(A)과 고주파(Radio Frequency) 회로영역(B)으로 정의한다.Referring to FIG. 2A, the semiconductor substrate may include at least one of a silicon (Si) wafer, a germanium (Ge) wafer, a silicon germanium (SiGe) wafer, and a silicon on insulator (SOI) wafer. It does not specifically limit, All the board | substrates which can manufacture a semiconductor element are included. In particular, in the present embodiment, due to the parasitic current generated in the high frequency circuit region B to be described later using the SOI wafer 240 having the first silicon 210, the insulating film 220, and the second silicon 230 stacked therein, The characteristics of the logic area A are prevented from changing as much as possible. The pad oxide layer 260 and the nitride layer 270 are sequentially deposited on the above-described SOI wafer 240. Next, an SOI wafer 240 is defined as an active region and a field region by forming an isolation layer, and defined as a logic region A and a radio frequency circuit region B. FIG.
구체적으로 이를 설명하면, STI(Shallow Trench Isolation)구조의 트랜치(246)와 DTI(Deep Trench Isolation)구조의 트랜치(248)를 동시에 형성하기 위하여, 질화막(270)과 패드 산화막(260)의 일부를 제거하여 소자 분리막(250)이 형성될 영역의 SOI 웨이퍼(240)를 노출시킨다. 상기 질화막(270)을 식각 마스크로 하는 식각공정을 실시하여 상기의 노출된 SOI 웨이퍼(240)의 일부를 제거하여 STI구조의 트랜치(246)를 형성함으로써 소자들을 분리한다. DTI 구조의 트랜치(248)가 형성될 영역을 제외한 모든 영역의 STI구조의 트랜치(246)를 포토레지스트(도시되지 않음)를 이용하여 블럭킹(Blocking)한다. DTI 구조의 트랜치가 형성될 영역 상의 질화막(270)을 식각마스크로 하는 식각공정을 실시하여 STI구조의 트랜치(246)를 과도 식각함으로써 DTI 구조의 트랜치(248)를 형성하고, 이로써 SOI 웨이퍼(240)를 로직영역(A)과 고주파 회로영역(B)으로 정의한다. 다음으로, 상기의 포토레지스트를 제거한다. 이때 DTI 구조의 트래치 형성시 SOI 웨이퍼(240)내의 절연막(270)을 노출시킴으로써 고주파 회로영역(B)의 누설전류를 완전히 차단한다.Specifically, in order to simultaneously form a trench 246 having a shallow trench isolation (STI) structure and a trench 248 having a deep trench isolation (DTI) structure, a portion of the nitride layer 270 and the pad oxide layer 260 are formed. By removing, the SOI wafer 240 in the region where the device isolation layer 250 is to be formed is exposed. An etching process using the nitride layer 270 as an etching mask is performed to remove portions of the exposed SOI wafer 240 to form trenches 246 having an STI structure, thereby separating the devices. The trenches 246 of all regions of the STI structure except for the region where the trenches 248 of the DTI structure are to be formed are blocked using photoresist (not shown). The trench 248 of the DTI structure is formed by over-etching the trench 246 of the STI structure by performing an etching process using the nitride film 270 on the region where the trench of the DTI structure is to be formed as an etch mask, thereby forming the SOI wafer 240. ) Is defined as a logic region A and a high frequency circuit region B. Next, the photoresist is removed. At this time, when forming the DTI structure, the leakage current of the high frequency circuit region B is completely blocked by exposing the insulating film 270 in the SOI wafer 240.
도 2b를 참조하면, 산화공정을 실시하여 상술한 트랜치들(246 및 248)을 산화막으로 매립함으로써 소자 분리막(250)을 형성한다. 다음으로, 식각공정을 실시하여 로직영역(A) 및 고주파 회로영역(B)상의 질화막(270)을 제거한다. 고주파회로영역(B)을 포토레지스트(도시되지 않음)를 이용하여 블러킹한 다음 식각공정을 실시하여 로직영역(A) 상부의 패드 산화막(260)을 제거하고 고주파 회로영역(B)의 패드 산화막을 잔류시킨 다음 상기의 포토레지스트를 제거한다. 이때 고주파 회로영역(B) 상부에 패드 산화막(260)을 잔류시킴으로써 SOI 웨이퍼(240)와 MIM 캐패시터의 하부전극(280)을 절연시키는 절연막으로 사용한다.Referring to FIG. 2B, an isolation process 250 is formed by filling the trenches 246 and 248 with an oxide film by performing an oxidation process. Next, an etching process is performed to remove the nitride film 270 on the logic region A and the high frequency circuit region B. FIG. The high frequency circuit region B is blocked using a photoresist (not shown), and then an etching process is performed to remove the pad oxide layer 260 over the logic region A and to remove the pad oxide layer in the high frequency circuit region B. After remaining, the photoresist is removed. In this case, the pad oxide layer 260 is left on the high frequency circuit region B so that the SOI wafer 240 is insulated from the lower electrode 280 of the MIM capacitor.
전체구조 상부에 제 1 도전막(도시되지 않음)을 증착한 후 패터닝공정을 실시하여 로직영역(A) 상의 제 1 도전막을 제거하고, 고주파 회로영역(B) 상에 MIM 하부전극(280)을 형성한다. 이때 제 1 도전막으로는 TiN, Ti 또는 TaN 중 적어도 어느 하나 이상을 사용하여 증착하되 특별히 한정되지 않고 높은 전도성을 갖는 물질을 사용한다.After depositing a first conductive layer (not shown) on the entire structure, a patterning process is performed to remove the first conductive layer on the logic region A, and the MIM lower electrode 280 is disposed on the high frequency circuit region B. Form. In this case, as the first conductive film, at least one of TiN, Ti, and TaN is deposited using a material having high conductivity without being particularly limited.
도 2c를 참조하면, 전처리 세정공정을 실시한 후 전체구조 상부에 유전체막(290)을 증착한다. 유전체막(290)은 HfO2, Al2O3, Ta2O5또는 AlZrO 중 적어도 어느 하나 이상으로 구성하지만 특별히 한정되지 않고 높은 유전율을 가진 게이트 전극용 유전물질을 사용하여 형성한다. 본 실시예에서는 HfO2, Al2O3, Ta2O5또는 AlZrO 중 적어도 어느 하나를 이용하여 2 내지 6층으로 구성된 적층형의 유전체막(290)을 형성한다. 또한 유전체막(290)의 두께는 로직영역(A)상에 형성될 게이트 전극(304)과 고주파 회로영역(B)에 형성될 MIM커패시터(306)의 특성 및 기능을 고려하여 형성한다. 이때 RTO(Rapid Thermal Oxidation) 또는 RTN(Rapid Thermal Nitridation)방법을 이용하여 유전체 막을 형성하고, 400 내지 1000℃의 온도와 O2, N2, Ar 및 He 가스 분위기 하에서 열처리 공정을 실시한다.Referring to FIG. 2C, after the pretreatment cleaning process, a dielectric film 290 is deposited on the entire structure. The dielectric film 290 is formed of at least one of HfO 2 , Al 2 O 3 , Ta 2 O 5, or AlZrO, but is not particularly limited, and is formed using a dielectric material for a gate electrode having a high dielectric constant. In this embodiment, a laminated dielectric film 290 composed of 2 to 6 layers is formed using at least one of HfO 2 , Al 2 O 3 , Ta 2 O 5, or AlZrO. In addition, the thickness of the dielectric film 290 is formed in consideration of the characteristics and functions of the gate electrode 304 to be formed on the logic region A and the MIM capacitor 306 to be formed in the high frequency circuit region B. At this time, a dielectric film is formed by using a Rapid Thermal Oxidation (RTO) or Rapid Thermal Nitridation (RTN) method, and heat treatment is performed under a temperature of 400 to 1000 ° C. and O 2 , N 2 , Ar, and He gas atmospheres.
상술한 공정을 실시하여 유전체막(290)을 형성한후 O2또는 NH3를 이용한 프라즈마 처리를 실시하여 누설전류를 감소시킨다. 즉, 유전체막(290) 내의 빈 공간을 O2또는 NH3를 이용하여 매립함으로써 절연특성을 향상시킨다.After the dielectric film 290 is formed by the above-described process, plasma treatment using O 2 or NH 3 is performed to reduce the leakage current. That is, the insulating property is improved by filling the empty space in the dielectric film 290 with O 2 or NH 3 .
상기와 같이 로직영역(A) 및 고주파 회로영역(B)에 유전체막(290)을 동시에 증착하여 로직영역(A)에서는 상기의 유전체막(290)을 게이트 산화막(294)으로 사용하고, 고주파 회로영역(B)에서는 유전체막(290)을 MIM 커패시터의 유전체막(292)으로 사용한다. 즉, 게이트 산화막(294)과 유전체막(292)을 동시에 형성함으로써 공정의 단순화를 할 수 있다.As described above, the dielectric film 290 is simultaneously deposited in the logic region A and the high frequency circuit region B. In the logic region A, the dielectric film 290 is used as the gate oxide film 294. In the region B, the dielectric film 290 is used as the dielectric film 292 of the MIM capacitor. That is, the process can be simplified by simultaneously forming the gate oxide film 294 and the dielectric film 292.
도 2d를 참조하면, 전체구조 상부에 제 2 도전막(도시되지 않음)을 증착한 다음 패터닝공정을 실시하여 로직영역(A)에는 게이트전극용 도전막(302)과 유전체막(290)을 패터닝함으로써 게이트전극(304)을 형성하고, 고주파 회로영역(B)에는MIM 캐패시터의 상부전극(300)을 패터닝함으로써 MIM 커패시터(306)를 형성한다. 이때 제 2 도전막으로는 TiN, Ti 또는 TaN 중 적어도 어느 하나 이상을 사용하여 증착하되 특별히 한정되지 않고 높은 전도성을 갖는 물질을 사용한다. 또한 제 2 도전막의 두께는 로직영역(A)상에 형성될 게이트 전극(304)과 고주파 회로영역(B)에 형성될 MIM 커패시터(306)의 특성 및 기능을 고려하여 형성한다. 상술한 바와 같이 게이트 전극용 도전막(302)과 MIM 커패시터용 상부전극(300)을 동시에 형성함으로써 공정의 단순화를 할 수 있다.Referring to FIG. 2D, a second conductive film (not shown) is deposited on the entire structure, and then a patterning process is performed to pattern the gate electrode conductive film 302 and the dielectric film 290 in the logic region A. FIG. The gate electrode 304 is formed, and the MIM capacitor 306 is formed in the high frequency circuit region B by patterning the upper electrode 300 of the MIM capacitor. In this case, as the second conductive film, at least one of TiN, Ti, and TaN is deposited, and a material having high conductivity is not particularly limited. In addition, the thickness of the second conductive layer is formed in consideration of the characteristics and functions of the gate electrode 304 to be formed on the logic region A and the MIM capacitor 306 to be formed in the high frequency circuit region B. FIG. As described above, the process can be simplified by simultaneously forming the gate electrode conductive film 302 and the MIM capacitor upper electrode 300.
전체 구조 상부에 층간절연막(도시되지 않음)을 증착한 다음 후속공정을 실시하여 게이트 전극(304)과 MIM 커패시터(306) 각각을 전기적 연결을 위한 메탈라인(도시되지 않음)에 연결한다.An interlayer insulating film (not shown) is deposited on the entire structure, and then a subsequent process is performed to connect each of the gate electrode 304 and the MIM capacitor 306 to a metal line (not shown) for electrical connection.
상술한 바와 같이, 본 발명은 고주파 회로영역의 MIM 캐패시터 유전체막을 로직영역의 게이트 산화막과 동시에 형성하고 고주파 회로영역의 MIM 캐패시터 상부전극을 로직영역의 게이트전극용 도전막과 동시에 형성함으로써 공정의 단순화 및 비용을 절감할 수 있다.As described above, the present invention simplifies the process by forming the MIM capacitor dielectric film of the high frequency circuit region simultaneously with the gate oxide film of the logic region and simultaneously forming the MIM capacitor upper electrode of the high frequency circuit region with the conductive film for the gate electrode of the logic region. You can save money.
또한 메탈라인 형성 전에 고주파 회로영역의 MIM 캐패시터를 형성함으로써 누설 전류를 줄일 수 있는 다양한 열처리 공정을 실시할 수 있다.In addition, by forming a MIM capacitor in the high frequency circuit region before forming the metal line, various heat treatment processes for reducing leakage current may be performed.
Claims (6)
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| JPS6122664A (en) * | 1984-07-11 | 1986-01-31 | Hitachi Ltd | Semiconductor storage device and its manufacture |
| JPH1074914A (en) * | 1996-08-29 | 1998-03-17 | Nec Corp | Method for manufacturing non-volatile semiconductor storage device |
| US6303455B1 (en) * | 2000-03-31 | 2001-10-16 | United Microelectronics Corp. | Method for manufacturing capacitor |
| US6309925B1 (en) * | 2000-08-22 | 2001-10-30 | United Microelectronics Corp. | Method for manufacturing capacitor |
| JP2001308192A (en) * | 1992-06-15 | 2001-11-02 | Asahi Kasei Microsystems Kk | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122664A (en) * | 1984-07-11 | 1986-01-31 | Hitachi Ltd | Semiconductor storage device and its manufacture |
| JP2001308192A (en) * | 1992-06-15 | 2001-11-02 | Asahi Kasei Microsystems Kk | Semiconductor device |
| JPH1074914A (en) * | 1996-08-29 | 1998-03-17 | Nec Corp | Method for manufacturing non-volatile semiconductor storage device |
| US6303455B1 (en) * | 2000-03-31 | 2001-10-16 | United Microelectronics Corp. | Method for manufacturing capacitor |
| US6309925B1 (en) * | 2000-08-22 | 2001-10-30 | United Microelectronics Corp. | Method for manufacturing capacitor |
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