KR100445407B1 - Method for fabricating a gate insulator of a CMOS - Google Patents
Method for fabricating a gate insulator of a CMOS Download PDFInfo
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- KR100445407B1 KR100445407B1 KR10-2001-0088296A KR20010088296A KR100445407B1 KR 100445407 B1 KR100445407 B1 KR 100445407B1 KR 20010088296 A KR20010088296 A KR 20010088296A KR 100445407 B1 KR100445407 B1 KR 100445407B1
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Abstract
본 발명은 CMOS 의 게이트절연막 제조방법에 관한 것으로, 반도체소자의 소집적화에 의한 게이트산화막의 두께 감소로 인하여 트랜지스터의 특성이 열화되는 현상을 억제할 수 있도록 하기 위하여, 종래의 게이트산화막 상에 고유전상수를 갖는 다중구조의 비정질 고용체 산화막을 형성하되, 막질이 우수하고 반도체기판을 손상시키지 않아 CMOS 트랜지스터의 GOI ( Gate Oxide Integrity ) 및 TDDB ( Time Dependent Dielectric Breakdown ) 특성을 향상시킬 수 있으므로 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate insulating film of CMOS, and to suppress a phenomenon in which transistor characteristics deteriorate due to a decrease in the thickness of the gate oxide film due to the integration of semiconductor devices, a high dielectric constant on a conventional gate oxide film A high-density semiconductor device can be formed by forming an amorphous solid solution oxide film having a multi-layer structure, but having excellent film quality and not damaging the semiconductor substrate, thereby improving GOI (Gate Oxide Integrity) and TDDB (Time Dependent Dielectric Breakdown) characteristics of CMOS transistors. It is a technology that makes it possible.
Description
본 발명은 CMOS 의 게이트절연막 제조 방법에 관한 것으로서, 보다 상세하게는 플라즈마 이온 충격의 혼합 효과로써 CMOS의 비정질 Hf-Al-O 혼합 게이트 산화막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a gate insulating film of CMOS, and more particularly, to a method of manufacturing an amorphous Hf-Al-O mixed gate oxide film of CMOS as a mixing effect of plasma ion bombardment.
최근 반도체 소자가 미세화됨에 따라 30Å 이하의 낮은 두께를 갖는 게이트 산화막이 요구되고 있다.Recently, as semiconductor devices have been miniaturized, a gate oxide film having a low thickness of 30 mW or less is required.
이러한 요구로 인해, 로직 CMOS 트랜지스터의 게이트 산화막을 HfO2또는 Hf-실리케이트, Hf-나노라미네이트 등의 고유전 게이트 다이일렉트릭(dielectric)을 적용하기 위한 노력이 활발히 이루어지고 있다.Due to these demands, efforts are being actively made to apply high-k gate electrics such as HfO 2 , Hf-silicate, and Hf-nano laminate to the gate oxide film of the logic CMOS transistor.
그러나, HfO2나 Hf-나노라미네이트는 낮은 온도에서도 결정화되어그레인(grain)을 형성하는 문제, Hf-실리케이트는 유전율이 낮은 문제 등이 있다.However, HfO 2 and Hf-nano laminates crystallize even at low temperatures to form grains, and Hf-silicates have low dielectric constants.
따라서, 최근에는 Hf-Al-O 혼합 옥사이드를 고유전 게이트 다이일렉트릭으로 사용하고자 하는 연구가 진행 중이다.Therefore, recently, a research into using Hf-Al-O mixed oxide as a high-k gate gate electric is underway.
그러나, Hf-Al-O의 경우도 아주 미세한 결정상이 존재할 경우, 고온에서 쉽게 상분리(phase seperation)가 일어나 더욱 결정이 커지거나 증착시 균일하고 조성이 고른 박막을 만들기가 힘든 단점이 있다.However, even in the case of Hf-Al-O, when a very fine crystal phase is present, phase seperation occurs easily at a high temperature, so that the crystal becomes larger or difficult to form a uniform and uniform thin film during deposition.
본 발명은 종래기술의 단점을 극복하기 위하여, 디커플드 플라즈마 처리 공정이나 저에너지 이온빔 처리 공정을 실시하여 게이트절연막의 막질을 향상시키고, GOI 및 TDDB 의 특성 열화를 억제할 수 있는 CMOS 의 게이트절연막 제조 방법을 제공하는데 그 목적이 있다.In order to overcome the drawbacks of the prior art, the present invention provides a gate insulating film of CMOS which can improve the film quality of the gate insulating film by performing a decoupled plasma treatment process or a low energy ion beam treatment process and can suppress the deterioration of characteristics of GOI and TDDB. The purpose is to provide a method.
도 1 내지 도 6은 본 발명에 따른 CMOS 의 게이트절연막 제조 방법의 바람직한 실시예를 설명하는 공정도1 to 6 are process charts illustrating a preferred embodiment of a method for manufacturing a gate insulating film of CMOS according to the present invention.
이상의 목적을 달성하기 위해 본 발명에 따른 CMOS 의 게이트절연막 제조 방법은,액티브 영역 상에 게이트 산화막을 형성하는 제 1 공정;상기 게이트 산화막 상에 다중박막을 형성하는 제 2 공정;상기 다중 박막을 실온 내지 600 ℃ 의 온도에서 비정질 고용체 산화막으로 변환시키는 제 3 공정;상기 비정질 고용체 산화막을 어닐링하는 제 4 공정; 및상기 비정질 고용체 산화막 상부에 폴리실리콘, 실리사이드, 메탈 및 이들의 조합으로 이루어지는 군에서 선택된 한가지로 게이트전극용 도전층을 형성하는 제 5 공정을 포함하는 것과,상기 제 2 공정의 다중박막은 Hf, Zr, Ta, La, Y, Ce, Th, Pr, Dy, Gd, Ti, Si 및 Al 로 이루어지는 군에서 선택된 하나 이상의 물질로 구비되는 것과,상기 제 2 공정은 단원자 레이어 증착 방법을 이용하여 실시하는 것과상기 제 3 공정은 불활성 기체인 Ar, Ne, Kr, Xe 및 이들의 조합으로 이루어지는 군에서 한가지를 이용하는 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 3 공정은 N 을 포함하는 N2, NO, N2O 및 NH3으로 이루어지는 군에서 선택된 한가지를 이용하여 디커플드 플라즈마 처리되는 것과,상기 제 3 공정은 Ar, Ne, Kr 및 Xe 등의 불활성 기체와, N을 포함하는 N2, NO, N2O 및 NH3가 적어도 하나 이상 혼합되는 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 3 공정은 기체의 유량이 10 내지 1000 sccm 인 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 3 공정은 5 - 200 Torr 진공의 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 3 공정은 RF 플라즈마 파워를 100 내지 2000 W 로 하는 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 3 공정은 100 W 이하의 바이어스 파워의 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 3 공정은 10 내지 300 초 동안 디커플드 플라즈마 처리공정으로 실시되는 것과,상기 제 4 공정의 어닐링은 O2, N2, NO, N2O 또는 진공 중에서 어느 하나의 분위기로 진행됨과,상기 제 4 공정의 어닐링은 100 내지 800 ℃ 의 온도 환경에서 수행됨과,상기 제 4 공정의 어닐링은 10 내지 1800 초 동안 실시되는 것과,상기 제 5 공정의 폴리실리콘은 4.1 내지 4.2 eV 의 워크 펑션(work function)을 갖는 n+ 폴리실리콘으로 형성되는 것과,상기 제 5 공정의 메탈은 N 포함하는 TaNx, TaSixNy, TaAlxNy, TiNx, TiAlxNy, TiSixNy, RuTaxNy및 WNx로 이루어지는 군에서 선택되는 한가지가 사용되는 것과,상기 제 5 공정의 게이트전극용 도전층이 폴리실리콘과 메탈의 적층구조 형성되는 경우는 10 - 2000 Å 의 두께로 형성되는 것과,상기 제 5 공정의 게이트전극용 도전층 상부에 텅스텐을 더 형성하는 것과,상기 제 3 공정의 비정질 고용체 산화막은 Hf-Al-O, Hf-Zr-O, Ta-Zr-O, Zr-Al-O, Al-Ti-O, Hf-Si-O 및 Zr-Si-O 로 이루어지는 군에서 선택된 한가지인 것과,상기 제 3 공정은 500 내지 3000 eV 의 이온빔으로 실시되는 것을 특징으로 한다.이하, 본 발명에 따른 CMOS 의 게이트절연막 제조방법의 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.In order to achieve the above object, a method of manufacturing a gate insulating film of a CMOS according to the present invention includes: a first step of forming a gate oxide film on an active region; a second step of forming a multiple thin film on the gate oxide film; A third step of converting the amorphous solid solution oxide film at a temperature of from about 600 ° C .; a fourth step of annealing the amorphous solid solution oxide film; And a fifth step of forming a conductive layer for the gate electrode on the amorphous solid oxide layer, the conductive layer for the gate electrode being one selected from the group consisting of polysilicon, silicide, metal, and combinations thereof. Zr, Ta, La, Y, Ce, Th, Pr, Dy, Gd, Ti, Si and Al is provided with one or more materials selected from the group, The second process is carried out using a monoatomic layer deposition method And the third step is performed by a decoupled plasma treatment step using one of the group consisting of Ar, Ne, Kr, Xe and combinations thereof, which are inert gases, and the third step is N 2 including N. , Decoupled plasma treatment using one selected from the group consisting of NO, N 2 O, and NH 3 , and the third process includes an inert gas such as Ar, Ne, Kr, and Xe, and N 2 including N. , NO, The decoupled plasma treatment step of mixing at least one N 2 O and NH 3 , The third step is carried out by a decoupled plasma treatment step of the flow rate of the gas 10 to 1000 sccm, The third step is carried out by a decoupled plasma treatment step of 5-200 Torr vacuum, the third step is carried out by a decoupled plasma treatment step of setting the RF plasma power 100 to 2000 W, the third step Is a decoupled plasma treatment process having a bias power of 100 W or less, the third process is performed by a decoupled plasma treatment process for 10 to 300 seconds, and the annealing of the fourth process is performed at O 2 ,. The process of any one of N 2 , NO, N 2 O or vacuum, the annealing of the fourth process is performed in a temperature environment of 100 to 800 ℃, the annealing of the fourth process is 10 to 1800 seconds, the polysilicon of the fifth process is formed of n + polysilicon having a work function of 4.1 to 4.2 eV, the metal of the fifth process is TaN x containing N , One selected from the group consisting of TaSi x N y , TaAl x N y , TiN x , TiAl x N y , TiSi x N y , RuTa x N y and WN x is used, and the gate electrode of the fifth process When the conductive layer is formed of a polysilicon and metal laminate structure, the thickness is 10 to 2000 Å, the further forming tungsten on the conductive layer for the gate electrode of the fifth process, and the third process The amorphous solid oxide layer is selected from the group consisting of Hf-Al-O, Hf-Zr-O, Ta-Zr-O, Zr-Al-O, Al-Ti-O, Hf-Si-O and Zr-Si-O In one embodiment, the third process is performed with an ion beam of 500 to 3000 eV. Preferred embodiments of the t insulating film production method will be described in detail with reference to the accompanying drawings.
고밀도 이온을 중에너지 또는 저에너지로 다중박막 구조에 주입할 경우, 높은 에너지를 박막에 전달해 순간적으로 1000℃ 이상으로 가열하는 효과가 있다.When high-density ions are injected into the multi-layer structure with medium energy or low energy, high energy is transferred to the thin film, and there is an effect of instantaneously heating to 1000 ° C. or more.
또한, 상대적으로 이온이 도달하는 박막 중심 위치에만 국부적으로 가열되고, 다른 부분에는 열 전달이 거의 없기 때문에 급속한 냉각이 이루어진다.In addition, it is locally heated only at the thin film center position where the ions reach, and rapid cooling occurs because there is little heat transfer at other parts.
이는 래피드 서멀 어닐(rapid thermal anneal), 레이저 서멀 어닐(laser thermal anneal), 또는 스파크 어닐(spike anneal) 보다 훨씬 급속 가열 및 급속 냉각의 효과가 있기 때문에 순간 높은 온도에서 비정질 고용체가 된 박막이 급속 냉각에 의해 상온에서도 높은 온도에서의 구조를 그대로 유지하는 장점이 있다.This has the effect of much faster heating and rapid cooling than rapid thermal anneal, laser thermal anneal, or spike anneal. This has the advantage of maintaining the structure at a high temperature even at room temperature.
따라서, 수십 내지 수백 Å 정도의 두께를 갖는 HfO2-Al2O3다중 박막을 비정질 완전 고용체의 Hf-Al-O로 만들수 있다.Therefore, HfO 2 -Al 2 O 3 multiple thin films having a thickness of several tens to several hundred micrometers can be made into Hf-Al-O of amorphous solid solution.
3keV 이상의 이온 주입 방식을 사용하면, 실리콘 기판까지 손상을 주므로, 3keV 이하의 저에너지 이온주입, 고밀도 플라즈마 침입(high density plasmaimmersion), 또는 바이어스를 인가하지 않는 방식의 디커플드 플라즈마 침입(decoupled plasma immersion)을 이용하여 100Å 미만의 Hf-Al-O의 비정질화가 가능하다. 특히 디커플드 플라즈마 침입 처리의 경우 수십 Å 깊이 내에만 이온이 주입되기 때문에 하부 기판에 전혀 영향을 주지 않는다.The ion implantation method of 3 keV or more damages the silicon substrate, so low energy ion implantation below 3 keV, high density plasma immersion, or decoupled plasma immersion without bias is applied. By using Hf-Al-O of less than 100 kHz it is possible to amorphous. In particular, the decoupled plasma penetration process does not affect the underlying substrate at all because ions are implanted only within a few tens of micrometer depths.
상술한 방법을 활용하여 CMOS Hf-Al-O 혼합 옥사이드 게이트 산화막 제조 방법을 도1 내지 도 6을 참조하여 설명한다.A method of manufacturing a CMOS Hf-Al-O mixed oxide gate oxide film using the above-described method will be described with reference to FIGS. 1 to 6.
도 1과 같이 소자 분리막(12) 사이의 액티브 영역(10) 상에 매우 얇은 실리콘 게이트 산화막(14)을 형성한다.As shown in FIG. 1, a very thin silicon gate oxide film 14 is formed on the active region 10 between the device isolation layers 12.
여기에서 실리콘 게이트 산화막(14)은 SiO2또는 SiOxNy로 선택될 수 있고, 그 두께는 7-20Å 정도로 형성될 수 있다.Here, the silicon gate oxide film 14 may be selected from SiO 2 or SiO x N y , and the thickness thereof may be formed about 7-20 μm.
그 후, 게이트 산화막(14)의 상부에 HfO2와 Al2O3를 교대로 일정 두께 증착하여 HfO2-Al2O3다중 박막(16)을 도 2와 같이 형성한다.Thereafter, HfO 2 and Al 2 O 3 are alternately deposited on the gate oxide film 14 to form a HfO 2 —Al 2 O 3 multilayer thin film 16 as shown in FIG. 2.
이때 증착은 단원자 레이어 증착(atomic layer deposition) 방법을 이용할 수 있으며, 각각의 두께는 1-20Å 정도로 형성한다.At this time, the deposition may use an atomic layer deposition (atomic layer deposition) method, each thickness is formed about 1-20Å.
상기 다중 박막(16)은 도 3과 같이 디커플드 플라즈마 처리에 의하여 Hf-Al-O 가 혼합된 비정질 고용체 산화막으로 변환된다.The multilayer thin film 16 is converted into an amorphous solid solution oxide mixed with Hf-Al-O by a decoupled plasma treatment as shown in FIG. 3.
디커플드 플라즈마 처리할 때 기판은 0 - 600 ℃ 의 온도, 바람직하게는 실온 - 600 ℃ 의 온도를 갖도록 조절될 수 있으며, 디커플드 플라즈마 처리에 Ar, Ne, Kr, Xe 등의 불활성 기체가 이용될 수 있으며, 불활성 기체 대신 N을 포함하는 N2, NO, N2O, NH3가 이용될 수 있고, 불활성 기체와 이들이 혼합되어 사용될 수 있다.When the decoupled plasma treatment is performed, the substrate may be adjusted to have a temperature of 0 to 600 ° C., preferably room temperature to 600 ° C., and inert gases such as Ar, Ne, Kr, and Xe may be added to the decoupled plasma treatment. N 2 , NO, N 2 O, NH 3 containing N may be used instead of the inert gas, and these may be used in combination with the inert gas.
그리고, 디커플드 플라즈마 처리를 위하여 공급되는 기체의 유량은 10sccm-1000sccm 정도로 정해질 수 있으며, 챔버 내부의 진공도는 5-200 Torr 정도로 정해질 수 있고, RF 플라즈마 파워는 100-2000 W로 설정될 수 있다.In addition, the flow rate of the gas supplied for the decoupled plasma treatment may be set at about 10 sccm-1000 sccm, the degree of vacuum inside the chamber may be set at about 5-200 Torr, and the RF plasma power may be set at 100-2000 W. Can be.
그리고, 디커플드 플라즈마를 위하여 바이어스 파워가 100W 이하로 설정될 수 있으며, 10-300초 정도로 플라즈마 처리 시간이 결정될 수 있다.In addition, the bias power may be set to 100 W or less for the decoupled plasma, and the plasma processing time may be determined as about 10 to 300 seconds.
또한, 상기한 디커플드 플라즈마 처리 대신 500-3000eV의 저에너지 이온빔을 이용하여 HfO2-Al2O3를 혼합할 수 있다.In addition, HfO 2 -Al 2 O 3 may be mixed using a low energy ion beam of 500-3000 eV instead of the decoupled plasma treatment described above.
이렇게 변환된 Hf-Al-O 산화막은 도 4와 같이 어닐링으로 플라즈마에 의한 손상을 복구와 밀도 조절을 수행하고, 그 후 도 5와 같이 불순물이 도핑된 폴리실리콘(18)과 저저항성 메탈(20)을 일정한 두께(50-2000Å)로 차례로 증착시킨다.The Hf-Al-O oxide film thus converted is subjected to annealing as shown in FIG. 4 to recover damage and density control by plasma, and then to the polysilicon 18 and the low resistance metal 20 doped with impurities as shown in FIG. ) Is deposited one after the other at a constant thickness (50-2000 mm 3).
상기한 어닐은 O2, N2, NO, N2O 또는 진공 분위기에서 진행될 수 있으며, 온도는 100-800℃로 설정될 수 있으며, 어닐 공정 시간은 10-1800 sec로 설정될 수 있다.The annealing may be performed in O 2 , N 2 , NO, N 2 O or in a vacuum atmosphere, the temperature may be set to 100-800 ℃, the annealing process time may be set to 10-1800 sec.
그리고, 도 5에서 증착되는 폴리실리콘(18)은 4.1-4.2 eV 정도의 워크 펑션(work function)을 갖는 n+ 폴리실리콘을 사용할 수 있으며, 폴리실리콘(18) 상부에는 N을 포함하는 TaNx, TaSixNy, TaAlxNy, TiNx, TiAlxNy, TiSixNy, RuTaxNy, WNx등의 질화 금속을 메탈(20)로 증착할 수 있다.In addition, polysilicon 18 deposited in FIG. 5 may use n + polysilicon having a work function of about 4.1-4.2 eV, and TaN x , TaSi including N on the polysilicon 18. Metal nitrides such as x N y , TaAl x N y , TiN x , TiAl x N y , TiSi x N y , RuTa x N y , WN x, and the like may be deposited as the metal 20.
이와 다르게 폴리 실리콘(18)의 증착없이 게이트 산화막(14)의 상부에 N을 포함하는 TaNx, TaSixNy, TaAlxNy, TiNx, TiAlxNy, TiSixNy, RuTaxNy, WNx등의 질화 금속을 메탈(20)로 바로 증착할 수 있다.Alternatively, TaN x , TaSi x N y , TaAl x N y , TiN x , TiAl x N y , TiSi x N y , RuTa x containing N on the gate oxide film 14 without deposition of polysilicon 18. Metal nitrides such as N y and WN x may be directly deposited onto the metal 20.
여기에서 폴리실리콘(18)과 메탈(20)은 10-2000Å의 두께로 형성될 수 있다.Here, the polysilicon 18 and the metal 20 may be formed to a thickness of 10-2000Å.
그리고, 메탈(20) 상부에는 도면에 도시되지 않았지만 게이트 저항을 낮추기 위하여 실리사이드 또는 텅스텐을 증착할 수 있으며, 이때 실리사이드 또는 텅스턴은 50-2000Å의 두께로 형성될 수 있다.Although not shown in the drawing, silicide or tungsten may be deposited on the metal 20 to reduce the gate resistance, and the silicide or tungsten may be formed to a thickness of 50-2000 μs.
그후 마스크 및 식각 공정을 진행하여 도 6과 같이 게이트를 형성한다.Thereafter, a mask and an etching process are performed to form a gate as shown in FIG. 6.
본 발명에 따른 실시예로 Hf-Al-O 산화막이 제시되었으나, 이에 국한되지 않고 본 발명은 Hf-Zr-O, Zr-Al-O, Ta-Zr-O, Al-Ti-O, Hf-Si-O, Zr-Si-O 등 Hf, Zr, Ta, La, Y, Ce, Th, Pr, Dy, Gd, Ti Si 등을 포함하는 혼합 산화막에 적용될 수 있다.Although an Hf-Al-O oxide film has been presented as an embodiment according to the present invention, the present invention is not limited thereto, and the present invention is Hf-Zr-O, Zr-Al-O, Ta-Zr-O, Al-Ti-O, Hf- Si-O, Zr-Si-O and the like may be applied to a mixed oxide film including Hf, Zr, Ta, La, Y, Ce, Th, Pr, Dy, Gd, Ti Si, and the like.
상기한 바와 같이 본 발명에 따른 CMOS 의 게이트절연막 제조방법은, 다중 박막을 실온 내지 600 ℃ 의 온도에서 나노라미네이트인 비정질 고용체 산화막으로 변환시키는 공정시 박막의 특성 열화를 억제할 수 있도록 하여 CMOS 의 GOI 및 TDDB 의 특성을 향상시킬 수 있는 효과를 제공한다.As described above, the method for manufacturing a gate insulating film of the CMOS according to the present invention can suppress the deterioration of characteristics of the thin film during the process of converting the multiple thin film into an amorphous solid oxide oxide film which is a nanolaminate at a temperature from room temperature to 600 ° C. And it provides an effect that can improve the characteristics of the TDDB.
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US5923056A (en) * | 1996-10-10 | 1999-07-13 | Lucent Technologies Inc. | Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials |
WO2000001008A1 (en) * | 1998-06-30 | 2000-01-06 | Lam Research Corporation | Ulsi mos with high dielectric constant gate insulator |
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KR20010060567A (en) * | 1999-12-27 | 2001-07-07 | 박종섭 | Method of forming a gate dielectric film in a semiconductor device |
KR20010063733A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | Method of manufacturing a semiconductor device utilizing a gate dielelctric |
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US5923056A (en) * | 1996-10-10 | 1999-07-13 | Lucent Technologies Inc. | Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials |
US6014310A (en) * | 1997-01-16 | 2000-01-11 | International Business Machines Corporation | High dielectric TiO2 -SiN composite films for memory applications |
WO2000001008A1 (en) * | 1998-06-30 | 2000-01-06 | Lam Research Corporation | Ulsi mos with high dielectric constant gate insulator |
KR20010063733A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | Method of manufacturing a semiconductor device utilizing a gate dielelctric |
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