KR100437541B1 - Method for forming isolation layer of semiconductor device using two-step gap filling processes - Google Patents

Method for forming isolation layer of semiconductor device using two-step gap filling processes Download PDF

Info

Publication number
KR100437541B1
KR100437541B1 KR1019970014431A KR19970014431A KR100437541B1 KR 100437541 B1 KR100437541 B1 KR 100437541B1 KR 1019970014431 A KR1019970014431 A KR 1019970014431A KR 19970014431 A KR19970014431 A KR 19970014431A KR 100437541 B1 KR100437541 B1 KR 100437541B1
Authority
KR
South Korea
Prior art keywords
oxide film
sih
trench
forming
semiconductor device
Prior art date
Application number
KR1019970014431A
Other languages
Korean (ko)
Other versions
KR19980077335A (en
Inventor
이승무
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019970014431A priority Critical patent/KR100437541B1/en
Publication of KR19980077335A publication Critical patent/KR19980077335A/en
Application granted granted Critical
Publication of KR100437541B1 publication Critical patent/KR100437541B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to remove moisture and prevent voids in a trench by using two-step gap filling processes of a SiH4-H2O2 oxide layer. CONSTITUTION: A trench is formed in a semiconductor substrate. A first thermal oxide layer is formed on the trench and removed. A second thermal oxide layer is formed on the trench and treated by hydrophilicity. A first SiH4-H2O2 layer is partially filled in the trench. A first capping layer is deposited on the first SiH4-H2O2 layer. The resultant structure is firstly annealed. A second SiH4-H2O2 layer is entirely filled in the trench and secondly annealed. A second capping layer(19) is deposited on the second SiH4-H2O2 layer.

Description

반도체소자의 소자분리절연막 형성방법Device isolation insulating film formation method of semiconductor device

본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 SiH4- H2O2산화막으로 미세한 트렌치를 매립하고 열처리공정을 실시하여 막질을 치밀화 함으로써 소자의 분리 특성을 향상시켜 반도체소자의 고집적화를 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and in particular, by filling a fine trench with a SiH 4 -H 2 O 2 oxide film and performing a heat treatment process to densify the film quality, thereby improving the isolation characteristics of the device, thereby increasing integration of the semiconductor device. To improve the technology.

고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.

일반적으로 소자분리 기술에서 디자인 롤이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as device roll technology reduces design rolls, smaller buzz lengths and larger volume ratios are required.

그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.

또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워질 것이다.In addition, the trench isolation process also becomes difficult to bury the trench region as the design rule decreases as well as the complexity of the process, and when the design rule approaches 0.1 μm, it will be difficult to apply the trench isolation process.

일반적인 반도체소자의 얕은 트렌치 소자분리 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a shallow trench isolation of a semiconductor device will be described.

먼저, 반도체기판 상부에 패드절연막을 형성한다. 이때, 상기 패드절연막은 산화막/질화막의 적층구조이다.First, a pad insulating film is formed on the semiconductor substrate. At this time, the pad insulating film is a laminated structure of an oxide film / nitride film.

그 다음에, 상기 패드절연막은 노광 및 식각공정을 실시하여 트렌치 소자분리 패턴을 형성한다.Next, the pad insulating layer is exposed to and etched to form a trench isolation pattern.

그리고, 제1차 열산화공정을 실시하여 제1열산화막을 성장시킨 후 습식식각을 통해 상기 제1열산화막을 제거함으로써 상기 트렌치 형성공정시 발생된 상기 트렌치 표면의 결함을 제거한다.After the first thermal oxidation process is performed to grow the first thermal oxide layer, the first thermal oxide layer is removed by wet etching to remove defects on the trench surface generated during the trench formation process.

그 후, 제2차 열산화공정으로 제2열산화막을 성장시켜 표면을 친수화되게 한 다음 SiH4- H2O2산화막을 평탄하게 증착한다.Thereafter, the second thermal oxidation film is grown by the second thermal oxidation process to make the surface hydrophilic, and then a SiH 4 -H 2 O 2 oxide film is deposited evenly.

그리고, 후속 열처리공정을 실시하여 상기 SiH4- H2O2산화막을 치밀화시킨 다음, CMP 공정을 실시하여 두껍게 증착된 산화막을 제거하여 평탄화시킨다.Subsequently, a subsequent heat treatment process is performed to densify the SiH 4 -H 2 O 2 oxide film, and then a CMP process is performed to remove the planarized oxide film.

그러나, 상기한 바와 같은 얕은 트렌치 소자분리막 형성방법은 SiH4- H2O2산화막의 치밀화를 위한 열처리공정시 아래와 같은 문제점이 발생한다.However, the shallow trench isolation layer formation method as described above causes the following problems in the heat treatment process for densification of the SiH 4 -H 2 O 2 oxide film.

먼저, 한번에 많은 양의 SiH4- H2O2산화막을 트렌치에 매립하여 열처리공정시 트렌치 바닥부분은 열처리 효과가 나타나지 않는다. 그리고, 트렌치에 매립된 산화막이 열처리공정시 트렌치의 위 부분으로 끌려 올라가 트렌치에 보이드(void)가 발생됨으로써 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 한다.First, a large amount of SiH 4 -H 2 O 2 oxide film at a time is buried in the trench, the bottom portion of the trench during the heat treatment process does not exhibit a heat treatment effect. In addition, the oxide film embedded in the trench is pulled up to the upper portion of the trench during the heat treatment process to generate voids in the trench, thereby degrading the characteristics and reliability of the semiconductor device and consequently making the semiconductor device highly integrated.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치 매립공정시 단차피복성이 우수한 SiH4- H2O2산화막을 사용하여 두 번에 걸친 매립공정과 두 번에 걸친 열처리공정을 실시하여 트렌치를 완벽하게 채우고 효과적인 열처리공정으로 상기 SiH4- H2O2산화막의 막질을 치밀하게 함으로써 평탄화 특성을 향상시키고 후속공정을 용이하게 실시할 수 있는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by using the SiH 4 -H 2 O 2 oxide film excellent in the step coverage during the trench filling process by performing two filling processes and two heat treatment processes Provided is a method of forming a device isolation insulating film of a semiconductor device that can improve the planarization characteristics and easily follow-up process by densifying the film quality of the SiH 4 -H 2 O 2 oxide film in a fully filled trench and effective heat treatment process. There is a purpose.

도 1a 내지 도 1f 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.

◆ 도면의 주요부분에 대한 부호의 설명◆ Explanation of symbols for main parts of drawing

11 : 반도체기판 13 : 패드절연막11 semiconductor substrate 13 pad insulating film

14 : 질화막 15 : 트렌치14 nitride film 15 trench

16 : 제1 SiH4-H2O2산화막 17 : 제1캐핑레이어16: first SiH 4 -H 2 O 2 oxide film 17: first capping layer

18 : 제2 SiH4-H2O2산화막 19 : 제2캐핑레이어18: second SiH 4 -H 2 O 2 oxide film 19: second capping layer

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,Method for forming a device isolation insulating film of a semiconductor device according to the present invention for achieving the above object,

반도체기판 상부에 패드절연막을 형성하는 공정과,Forming a pad insulating film on the semiconductor substrate;

상기 패드절연막을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the pad insulating layer;

상기 트렌치 표면에 제1열산화막을 형성하는 공정과,Forming a first thermal oxide film on the trench surface;

상기 제1열산화막을 제거하는 공정과,Removing the first thermal oxide film;

상기 트렌치 표면에 제2열산화막을 형성하는 공정과,Forming a second thermal oxide film on the trench surface;

상기 제2열산화막 상부에 제1 SiH4- H2O2산화막을 증착하는 공정과,Depositing a first SiH 4 -H 2 O 2 oxide film on the second thermal oxide film;

상기 제1 SiH4- H2O2산화막 상부에 제1캐핑레이어를 증착하는 공정과,Depositing a first capping layer on the first SiH 4 -H 2 O 2 oxide layer;

전체표면을 제1차 열처리하는 공정과,First heat treating the entire surface,

상기 제1 캐핑레이어 상부에 제2 SiH4- H2O2산화막을 증착하는 공정과,Depositing a second SiH 4 -H 2 O 2 oxide film on the first capping layer;

전체표면을 제2차 열처리하는 공정과,Secondary heat treatment of the entire surface,

상기 제2 SiH4- H2O2산화막 상부에 제2캐핑레이어를 증착하는 공정과,Depositing a second capping layer on the second SiH 4 -H 2 O 2 oxide layer;

전체표면을 CMP 하는 공정을 포함하는 것을 특징으로 한다.It is characterized by including the process of CMP the whole surface.

한편, 이상의 목적을 달성하기위한 본 발명의 원리는, 얕은(shallow) 트렌치 소자분리공정을 실시하는데 있어서, 반도체기판에 트렌치를 형성하고 상기 트렌치 매립공정시 트렌치에 SiH4- H2O2산화막을 증착한 다음 캐핑레이어를 증착하여 후속 열처리공정시 막이 갈라지는 것을 방지하고, SiH4- H2O2산화막과 캐핑레이어를 한번 더 형성하고 열처리공정을 반복하여 실시함으로써 막 내부의 수분제거와 막질을 치밀화하고 보이드가 발생하는 것을 방지하여 공정 균일도 및 소자의 특성을 향상시키고 반도체 소자의 고집적화를 가능하게 하는 것이다.On the other hand, the principle of the present invention for achieving the above object, in performing a shallow trench device isolation process, forming a trench in the semiconductor substrate and a SiH 4 -H 2 O 2 oxide film in the trench during the trench filling process After the deposition, the capping layer is deposited to prevent the film from cracking during the subsequent heat treatment process, and the SiH 4 -H 2 O 2 oxide film and the capping layer are formed once more, and the heat treatment process is repeated to increase moisture removal and film quality in the film. By preventing voids from occurring, process uniformity and device characteristics can be improved, and semiconductor devices can be highly integrated.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1f 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성공정을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a device isolation insulating film forming process of a semiconductor device according to an embodiment of the present invention.

먼저, 반도체기판(11) 상부에 제1절연막(13)인 패드산화막을 형성한다. 이때, 상기 패드산화막(13)은 열산화공정으로 형성하되, 100 ∼ 200 Å 두께로 형성된 것이다.First, a pad oxide film, which is the first insulating film 13, is formed on the semiconductor substrate 11. At this time, the pad oxide film 13 is formed by a thermal oxidation process, it is formed to a thickness of 100 ~ 200Å.

그리고, 전체표면상부에 제2절연막(14)인 질화막을 일정두께로 형성한다.A nitride film, which is the second insulating film 14, is formed on the entire surface at a constant thickness.

이때, 상기 질화막(14)은 화학기상증착방법으로 1500 ~ 2500 Å 정도의 두께로 형성한다. (도 1a)At this time, the nitride film 14 is formed to a thickness of about 1500 ~ 2500Å by chemical vapor deposition method. (FIG. 1A)

그 다음에, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(11)에 트렌치(15)를 형성한다. (도 1b)Next, a trench 15 is formed in the semiconductor substrate 11 by an etching process using an element isolation mask (not shown). (FIG. 1B)

상기 트렌치(15) 표면에 제3절연막(도시안됨)인 제1열산화막을 형성하는 제1차 산화공정을 실시한다. 이때, 상기 제1열산화막(도시안됨)은 100 ~ 200 Å 정도의 두께로 형성한다.A first oxidation process is performed to form a first thermal oxide film, which is a third insulating film (not shown), on the surface of the trench 15. In this case, the first thermal oxide film (not shown) is formed to a thickness of about 100 ~ 200 Å.

그리고, 상기 제1열산화막(도시안됨)을 습식식각으로 제거한다.The first thermal oxide layer (not shown) is removed by wet etching.

이때, 제1차 산화공정과 이로인한 제1열산화막(도시안됨)의 제거공정은 상기 트렌치(15)형성공정시 발생된 트렌치(15) 표면의 결함을 제거한다.At this time, the primary oxidation process and the removal process of the first thermal oxide film (not shown) thereby removes defects on the surface of the trench 15 generated during the trench 15 formation process.

그리고, 제2차 산화공정으로 트렌치(15) 표면에 제4절연막(도시안됨)인 제2열산화막을 100 ∼ 200 Å 정도의 두께로 형성한다.In the second oxidation process, a second thermal oxide film, which is a fourth insulating film (not shown), is formed on the surface of the trench 15 to a thickness of about 100 to about 200 GPa.

그 다음에, 상기 제2열산화막(도시안됨)의 표면을 친수화시켜 SiH4- H2O2산화막이 평탄하게 증착되도록 한다.Then, the surface of the second thermal oxide film (not shown) is made hydrophilic so that the SiH 4 -H 2 O 2 oxide film is deposited evenly.

이때, 상기 제2열산화막의 친수화공정은 SC-1, 피라나 또는 NH4OH 용액을 사용하여 제2열산화막(도시안됨) 표면의 친수화를 실시한다.At this time, the hydrophilization step of the second thermal oxide film is subjected to hydrophilization of the surface of the second thermal oxide film (not shown) by using SC-1, Pirana or NH 4 OH solution.

여기서, 상기 제2열산화막(도시안됨)을 친수화하는 것은 제1 SiH4- H2O2산화막(16)에 플라즈마를 인가하지 않기 때문에 표면상태에 따라 증착특성이 변화하기 때문이다.The hydrophilization of the second thermal oxide film (not shown) is because the deposition characteristics change depending on the surface state since no plasma is applied to the first SiH 4 -H 2 O 2 oxide film 16.

그 다음, 전체표면에 2000 내지 3000 Å 정도의 두께로 제1 SiH4- H2O2산화막(16)을 증착한다. 이때, 상기 제1 SiH4- H2O2산화막(16)의 증착조건은 SiH480∼ 120 sccm, H2O20.5~1.0 g/min 를 0.5 ∼ 1.0 torr 정도의 압력 및 -10 ∼ 20 ℃ 정도의 온도에서 실시하는 것으로 한다. (도 1c)Then, the first SiH 4 -H 2 O 2 oxide film 16 is deposited on the entire surface with a thickness of about 2000 to 3000 Pa. At this time, the deposition conditions of the first SiH 4 -H 2 O 2 oxide film 16 is SiH 4 80 ~ 120 sccm, H 2 O 2 0.5 ~ 1.0 g / min pressure of about 0.5 to 1.0 torr and -10 to 20 It shall be performed at the temperature of about degreeC. (FIG. 1C)

그 다음에, 상기 제1 SiH4- H2O2산화막(16) 상부에 제1캐핑레이어(17)를 증착한다. 이때, 상기 제1캐핑레이어(17)는 상기 제1 SiH4- H2O2산화막(16) 증착후 후속 열처리공정시 크랙(crack)발생을 방지하기 위하여 플라즈마화학기상증착 산화막으로 500 내지 1000 Å 정도의 두께 증착한다. 이때, 상기 플라즈마화학기상증착 산화막 증착공정은 멀티챔버 내의 다른 챔버에서 실시한다.Next, a first capping layer 17 is deposited on the first SiH 4 —H 2 O 2 oxide layer 16. In this case, the first capping layer 17 is 500 to 1000 kPa as a plasma chemical vapor deposition oxide film to prevent cracking during subsequent heat treatment after deposition of the first SiH 4 -H 2 O 2 oxide film 16. Depth of thickness is deposited. At this time, the plasma chemical vapor deposition oxide film deposition process is carried out in another chamber in the multi-chamber.

여기서, 상기 제1캐핑레이어(17)를 증착하지 않을 경우에는 상기 제 1 SiH4- H2O2산화막(16)을 1000 ~ 2000 Å 정도의 두께로 증착한다. (도 1d)In this case, when the first capping layer 17 is not deposited, the first SiH 4 -H 2 O 2 oxide film 16 is deposited to a thickness of about 1000 to 2000 kPa. (FIG. 1D)

그 다음, 제1차 열처리공정을 실시하여 상기 제1 SiH4- H2O2산화막(16) 내의 수분을 제거한다.Subsequently, a first heat treatment process is performed to remove moisture in the first SiH 4 -H 2 O 2 oxide film 16.

여기서, 상기 제1차 열처리공정은 진공분위기에서 400 내지 650 ℃ 정도의 온도 및 100 내지 500 mTorr 정도의 압력인 조건으로 30 내지 60분간 실시한다.Here, the first heat treatment process is carried out in a vacuum atmosphere for 30 to 60 minutes at a temperature of about 400 to 650 ℃ and a pressure of about 100 to 500 mTorr.

그 후, 상기 제1캐핑레이어(17) 상부에 제2 SiH4- H2O2산화막(18)을 증착한다. 이때, 상기 제2 SiH4- H2O2산화막(18)은 4000 내지 5000 Å 정도의 두께로 증착하여 전체표면의 평탄도를 향상시킨다.Thereafter, a second SiH 4 -H 2 O 2 oxide film 18 is deposited on the first capping layer 17. At this time, the second SiH 4 -H 2 O 2 oxide film 18 is deposited to a thickness of about 4000 to 5000 kPa to improve the flatness of the entire surface.

그리고, 상기 제2 SiH4- H2O2산화막(18) 상부에 제2캐핑레이어(19)를 증착하여 후속 열처리공정시 크랙발생을 방지한다. 이때, 상기 제2 캐핑레이어(19)는 멀티챔버내의 다른 챔버에서 950 내지 1100 ℃ 정도의 온도로 30 내지 60 분동안 실시한다. (도 1e)In addition, a second capping layer 19 is deposited on the second SiH 4 -H 2 O 2 oxide layer 18 to prevent cracking during subsequent heat treatment. At this time, the second capping layer 19 is carried out for 30 to 60 minutes at a temperature of about 950 to 1100 ℃ in another chamber in the multichamber. (FIG. 1E)

그 후, 전체표면은 제2차 열처리공정을 실시한다. 이때, 상기 제2차 열처리공정은 상기 제1차 열처리공정과 같은 조건으로 제2 SiH4- H2O2산화막(18) 내의 수분제거하기 위해 열처리를 한 후 5 ~ 10 ℃/min 의 승온속도로 로(furnace)의 온도를 950 ∼ 1100 ℃ 정도로 증가시켜 30 ∼ 60 분정도 동안 막질 치밀화를 위한 열처리공정을 실시한다.Thereafter, the entire surface is subjected to a second heat treatment step. At this time, the second heat treatment step is a temperature increase rate of 5 ~ 10 ℃ / min after the heat treatment to remove the moisture in the second SiH 4 -H 2 O 2 oxide film 18 under the same conditions as the first heat treatment process Furnace (furnace) temperature is increased to about 950 ~ 1100 ℃ to perform a heat treatment process for densification of the film for about 30 to 60 minutes.

그 다음에, 후속 CMP 공정을 실시하여 평탄화시키고, 고온의 인산 용액으로 패드질화막을 제거하여 얕은 트렌치 소자분리막 형성공정을 완료한다. (도 1f)Subsequently, a subsequent CMP process is performed to planarize and the pad nitride film is removed with a hot phosphoric acid solution to complete the shallow trench isolation film formation process. (FIG. 1F)

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, SiH4- H2O2산화막으로 트렌치를 두번에 걸쳐 매립시켜 트렌치 내부의 수분을 제거하고 보이드의 발생을 방지함으로써 미세한 트렌치를 완벽하게 매립하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, in the method of forming a device isolation insulating film of a semiconductor device according to the present invention, a trench is formed by filling a trench twice with an SiH 4 -H 2 O 2 oxide film to remove moisture in the trench and to prevent generation of voids. Is completely embedded in the semiconductor device, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.

Claims (9)

반도체기판에 트렌치를 형성하는 공정과,Forming a trench in the semiconductor substrate; 상기 트렌치 표면에 제1열산화막을 형성하고 제거하는 공정과,Forming and removing a first thermal oxide film on the trench surface; 상기 트렌치 표면에 제2열산화막을 형성하는 공정과,Forming a second thermal oxide film on the trench surface; 상기 제2열산화막 표면을 친수화처리하는 공정과,Hydrophilizing the surface of the second thermal oxide film; 상기 트렌치를 매립하는 제1 SiH4- H2O2산화막을 증착하는 공정과,Depositing a first SiH 4 -H 2 O 2 oxide film filling the trench; 상기 SiH4- H2O2산화막 상부에 제1캐핑레이어를 증착하는 공정과,Depositing a first capping layer on the SiH 4 -H 2 O 2 oxide layer; 전체표면을 제1차 열처리하는 공정과,First heat treating the entire surface, 상기 제1캐핑레이어 상부에 제2 SiH4- H2O2산화막을 증착하는 공정과,Depositing a second SiH 4 -H 2 O 2 oxide film on the first capping layer; 전체표면을 제2차 열처리하는 공정과,Secondary heat treatment of the entire surface, 상기 제2 SiH4- H2O2산화막 상부에 제2캐핑레이어를 증착하는 공정과,Depositing a second capping layer on the second SiH 4 -H 2 O 2 oxide layer; 전체표면을 CMP 하는 공정을 포함하는 반도체소자의 소자분리절연막 형성방법.A method of forming a device isolation insulating film for a semiconductor device comprising the step of CMP the entire surface. 청구항 1 에 있어서,The method according to claim 1, 상기 제1,2열산화막은 100∼200Å의 두께로 형성하는 것을 특징으로하는 반도체소자의 소자분리절연막 형성방법.And the first and second thermal oxide films are formed to a thickness of 100 to 200 Å. 청구항 1 에 있어서,The method according to claim 1, 상기 친수화 처리 공정은 SC-1, 피라나 및 NH4OH 용액을 사용하여 실시하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The method of forming a device isolation insulating film of a semiconductor device, characterized in that the hydrophilization treatment step is performed using SC-1, Pirana and NH 4 OH solution. 청구항 1 에 있어서,The method according to claim 1, 상기 제1 SiH4- H2O2산화막은 SiH4100 ∼ 200 sccm과 H2O20.5 ∼ 1.0 g/min 를 -10 ∼ 020 ℃ 의 온도 및 0.5 ~ 1.0 torr 의 압력에서 2000 ~ 3000 Å의 두께로 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The first SiH 4 -H 2 O 2 oxide film of SiH 4 100 ~ 200 sccm and H 2 O 2 0.5 ~ 1.0 g / min at a temperature of -10 ~ 020 ℃ and a pressure of 0.5 ~ 1.0 torr of 2000 ~ 3000 Pa A method of forming a device isolation insulating film of a semiconductor device, characterized in that the deposition to a thickness. 청구항 1 에 있어서,The method according to claim 1, 상기 제1차 열처리공정은 400 ~ 650 ℃ 의 온도 및 100 ~ 500 mTorr 의 압력에서 30 ∼ 60 분간 실시하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The first heat treatment process is a device isolation insulating film forming method of a semiconductor device, characterized in that performed for 30 to 60 minutes at a temperature of 400 ~ 650 ℃ and a pressure of 100 ~ 500 mTorr. 청구항 1 에 있어서,The method according to claim 1, 상기 제2 SiH4- H2O2산화막은 SiH4100 ∼ 200 sccm과 H2O20.5 ∼ 1.0 g/min 를 -10 ∼ 020 ℃ 의 온도 및 0.5 ~ 1.0 torr 의 압력에서 4000 ~ 5000 Å 의 두께로 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The second SiH 4 -H 2 O 2 oxide film has a SiH 4 100-200 sccm and H 2 O 2 0.5-1.0 g / min at a temperature of -10-020 ° C. and a pressure of 0.5-1.0 torr of 4000-5000 Pa. A method of forming a device isolation insulating film of a semiconductor device, characterized in that the deposition to a thickness. 청구항 1 에 있어서,The method according to claim 1, 상기 캐핑레이어는 PECVD 산화막으로 500 ∼ 1000 Å 의 두께로 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The capping layer is a PECVD oxide film is deposited to a thickness of 500 ~ 1000 Å in the device isolation insulating film forming method of a semiconductor device. 청구항 1 에 있어서,The method according to claim 1, 상기 캐핑레이어를 미증착시 상기 제1 SiH4- H2O2산화막은 1000 ~ 2000 Å의 두께로 증착하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.When the capping layer is not deposited, the first SiH 4 -H 2 O 2 oxide film is deposited to a thickness of 1000 ~ 2000 Å. 청구항 1 에 있어서,The method according to claim 1, 상기 제2차 열처리공정은 400 ~ 650 ℃의 온도 및 100 ~ 500 mTorr 의 압력에서 30 ~ 60 분간 수분제거를 위한 열처리 단계와 5 ~ 10 ℃/min 의 승온속도로 로(furnace)의 온도를 증가시켜 950 ~ 1100 ℃ 의 온도에서 30 ~ 60 분 동안 막질을 치밀화시키는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The second heat treatment process is a heat treatment step for removing water for 30 to 60 minutes at a temperature of 400 ~ 650 ℃ and a pressure of 100 ~ 500 mTorr and increase the temperature of the furnace (furnace) at a temperature increase rate of 5 ~ 10 ℃ / min To densify the film for 30 to 60 minutes at a temperature of 950 to 1100 ℃.
KR1019970014431A 1997-04-18 1997-04-18 Method for forming isolation layer of semiconductor device using two-step gap filling processes KR100437541B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970014431A KR100437541B1 (en) 1997-04-18 1997-04-18 Method for forming isolation layer of semiconductor device using two-step gap filling processes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970014431A KR100437541B1 (en) 1997-04-18 1997-04-18 Method for forming isolation layer of semiconductor device using two-step gap filling processes

Publications (2)

Publication Number Publication Date
KR19980077335A KR19980077335A (en) 1998-11-16
KR100437541B1 true KR100437541B1 (en) 2004-10-08

Family

ID=37348919

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970014431A KR100437541B1 (en) 1997-04-18 1997-04-18 Method for forming isolation layer of semiconductor device using two-step gap filling processes

Country Status (1)

Country Link
KR (1) KR100437541B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030057606A (en) * 2001-12-29 2003-07-07 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Also Published As

Publication number Publication date
KR19980077335A (en) 1998-11-16

Similar Documents

Publication Publication Date Title
KR100280106B1 (en) How to form trench isolation
KR0151051B1 (en) Method of forming insulation film for semiconductor device
KR100505419B1 (en) Method for manufacturing isolation layer in semiconductor device
KR20010058498A (en) Method of forming trench type isolation layer in semiconductor device
KR100567022B1 (en) Method for forming isolation layer of semiconductor device using trench technology
US20040169005A1 (en) Methods for forming a thin film on an integrated circuit including soft baking a silicon glass film
KR20050067445A (en) Shallow trench isolation method in semiconductor device
KR20060083249A (en) Method of forming field oxide in flash memory device
KR100437541B1 (en) Method for forming isolation layer of semiconductor device using two-step gap filling processes
KR100422959B1 (en) Method for forming isolation layer of semiconductor device
KR100448232B1 (en) Method for forming isolation layer of semiconductor device using two-step gap-filling processes
KR100492790B1 (en) Device isolation insulating film formation method of semiconductor device
KR20040036858A (en) Method for forming isolation layer in semiconductor device
KR100257764B1 (en) Semiconductor device and manufacturing method
KR19990025197A (en) Trench element isolation
KR20110024513A (en) Method for fabricating semiconductor device
KR100623595B1 (en) Method for planarize dielectric layer in semiconductor device
KR20020060910A (en) Method for forming a trench isolation of semiconductor devices
KR20010010919A (en) A method for forming interlayer dielectric layer
KR20020066842A (en) Method of forming trench isolation and trench isolation using the same
KR19990006018A (en) Method of forming device isolation film of semiconductor device
KR100517351B1 (en) Method for manufacturing device isolation barrier of semiconductor device
KR20010045420A (en) Method for forming interlayer insulating layer of semiconductor device
KR20040001874A (en) Method for forming trench type isolation layer in semiconductor device
KR20080062560A (en) Method for forming isolation to semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee