KR100422960B1 - Method for forming isolation layer of semiconductor device - Google Patents

Method for forming isolation layer of semiconductor device Download PDF

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KR100422960B1
KR100422960B1 KR1019970028733A KR19970028733A KR100422960B1 KR 100422960 B1 KR100422960 B1 KR 100422960B1 KR 1019970028733 A KR1019970028733 A KR 1019970028733A KR 19970028733 A KR19970028733 A KR 19970028733A KR 100422960 B1 KR100422960 B1 KR 100422960B1
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silicon nitride
semiconductor substrate
nitride film
spacer
forming
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KR1019970028733A
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KR19990004606A (en
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조성학
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to minimize a leakage current and decrease the size of a bird's beak by performing an etch process twice on the upper part of a semiconductor substrate to be an isolation region for forming an isolation layer and by growing the isolation layer. CONSTITUTION: A pad oxide layer pattern and the first silicon nitride layer pattern are formed to expose an isolation region of a semiconductor substrate. The second silicon nitride layer spacer is formed on the sidewall of the pad oxide layer pattern and the first silicon nitride layer pattern. A predetermined thickness of the substrate is etched by using the first silicon nitride layer pattern and the second silicon nitride layer spacer as an etch mask. The second silicon nitride layer spacer and a predetermined thickness of the substrate are etched by using a mask exposing a predetermined thickness of the second nitride layer spacer. The exposed semiconductor substrate is thermally oxidized to form an isolation layer.

Description

반도체소자의 소자분리절연막 형성방법Device isolation insulating film formation method of semiconductor device

본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 고집적 반도체소자의 소자분리막 형성시 반도체기판을 계단형으로 식각해준 후, 소자분리절연막을 형성함으로써 상기 반도체기판과 소자분리절연막간의 단차를 줄이고, 소자들을 안정되게 분리시켜 소자간에 누설전류가 발생되는 것을 방지하여 수율 향상 및 비용을 감소시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and in particular, by forming a device isolation insulating film after etching the semiconductor substrate in a step shape when forming a device isolation film of a highly integrated semiconductor device, a step between the semiconductor substrate and the device isolation insulating film is formed. The present invention relates to a technology for reducing the yield and stably separating devices to prevent leakage currents from occurring between the devices, thereby improving yield and reducing costs, and thereby enabling high integration of semiconductor devices.

일반적으로 반도체소자는 트랜지스터나 커패시터 등과 같은 소자들이 형성되는 활성영역과, 상기 소자들의 동작이 서로 방해되지 않도록 활성 영역들을 분리하는 소자분리 영역으로 구성되어 있다.In general, a semiconductor device is composed of an active region in which devices such as a transistor or a capacitor are formed, and an isolation region separating the active regions so that the operation of the devices does not interfere with each other.

최근 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지 하는 소자분리 영역의 면적을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, due to the trend toward higher integration of semiconductor devices, efforts have been made to reduce the area of device isolation regions, which occupy a large area in semiconductor devices.

이러한 소자분리 영역의 제조방법으로는 질화막 패턴을 마스크로 하여 반도체기판을 열산화시키는 통상의 로코스(local oxidation of silicon : 이하 LOCOS 라 함) 방법이나 반도체기판에 트렌치를 형성하고 이를 절연물질로 매립하는 트렌치분리 등의 방법이 사용되고 있으며, 그 중 LOCOS 방법은 비교적 공정이 간단하여 널리 사용되지만 소자분리 면적이 크고, 경계면에 버즈빅이 생성되어 기판 스트레스(stress)에 의한 격자 결함이 발생되는 단점이 있다.As a method of manufacturing the device isolation region, a conventional local oxidation of silicon (hereinafter referred to as LOCOS) method of thermally oxidizing a semiconductor substrate using a nitride film pattern as a mask, or a trench is formed in a semiconductor substrate and embedded in an insulating material. The trench separation method is used. Among them, the LOCOS method is widely used because of its relatively simple process, but the device separation area is large and buzz is generated at the interface, so that lattice defects are generated due to stress on the substrate. have.

상기 LOCOS 필드산화막의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of the LOCOS field oxide film as follows.

먼저, 반도체기판의 표면을 열산화시켜 패드산화막을 형성하고 상기 패드산화막 상부에 질화막을 형성한 다음, 상기 반도체기판의 소자분리 영역으로 예정된 부분을 노출시키는 질화막 패턴을 형성한 후, 상기 질화막 패턴을 열산화 마스크로 하여 반도체기판을 소정 두께 열산화시켜 필드산화막을 형성한다.First, the surface of the semiconductor substrate is thermally oxidized to form a pad oxide film, a nitride film is formed on the pad oxide film, and a nitride film pattern is formed to expose a predetermined portion to the device isolation region of the semiconductor substrate. The field oxide film is formed by thermally oxidizing a semiconductor substrate to a predetermined thickness using a thermal oxidation mask.

이러한 종래의 LOCOS 필드산화막은 활성영역과 필드산화막 사이의 반도체기판 경계부분에 산소가 측면 침투하여 버즈빅이라는 경사면이 형성된다.In the conventional LOCOS field oxide film, oxygen penetrates into the semiconductor substrate boundary portion between the active region and the field oxide film to form an inclined surface called Buzzvik.

상기 버즈빅에 의해 반도체기판에 스트레스가 인가되어 격자 결함이 발생되므로 누설전류가 증가되어 소자동작의 신뢰성이 떨어지고, 활성영역의 면적이 감소되어 소자의 고집적화가 어려워지는 문제점이 있다.Since the stress is applied to the semiconductor substrate by the Burjvik, lattice defects are generated, so that leakage current is increased and reliability of the device is decreased, and the area of the active area is reduced, making it difficult to integrate the device.

상기와 같은 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 소자분리 산화막의 단차가 반도체기판 상부로 돌출되어 후속 노광공정시 심각한 영향을 미치고, 소자의 고집적화로 인한 활성영역의 축소때문에 버즈 빅이 상대적으로 크게 되어 원하는 크기의 활성영역을 확보하는데에 문제점이 있다.In the method of forming a device isolation film of a semiconductor device according to the prior art as described above, the step of the device isolation oxide film protrudes above the semiconductor substrate and has a serious effect in the subsequent exposure process, and due to the reduction of the active area due to the high integration of the device, There is a problem in securing the active area of the desired size is relatively large.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소자분리 절연막 형성시 발생되는 소자간의 누설전류를 최소화시키고, 상기 소자분리절연막이 활성 영역 내로 들어가 발생되는 소자의 특성 저하를 억제하는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, to minimize the leakage current between the devices generated when forming the device isolation insulating film, and to prevent the deterioration of the characteristics of the device generated by the device isolation insulating film into the active region It is an object of the present invention to provide a method for forming an element isolation insulating film.

도 1 내지 도 9 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1 to 9 are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>

11 : 반도체기판 13 : 패드산화막11 semiconductor substrate 13 pad oxide film

15 : 제1실리콘 질화막 19 : 제2실리콘 질화막15: first silicon nitride film 19: second silicon nitride film

20 : 제2실리콘 질화막 스페이서 23 : 감광막 패턴20 second silicon nitride film spacer 23 photosensitive film pattern

25 : 소자분리 산화막25: device isolation oxide film

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,Method for forming a device isolation insulating film of a semiconductor device according to the present invention for achieving the above object,

반도체기판의 소자분리영역을 노출시키는 패드산화막 패턴과 제1실리콘 질화막 패턴을 형성하는 공정과,Forming a pad oxide film pattern and a first silicon nitride film pattern exposing the device isolation region of the semiconductor substrate;

상기 패드산화막 패턴과 제1실리콘 질화막 패턴 측벽에 제2실리콘 질화막 스페이서를 형성하는 공정과,Forming a second silicon nitride film spacer on sidewalls of the pad oxide film pattern and the first silicon nitride film pattern;

상기 제1실리콘 질화막 패턴과 제2실리콘 질화막 스페이서를 식각 마스크로 사용하여 상기 반도체기판을 일정 두께 식각하는 공정과,Etching the semiconductor substrate by a predetermined thickness using the first silicon nitride film pattern and the second silicon nitride film spacer as an etching mask;

상기 제2질회막 스페이서를 일정 두께 노출시키는 마스크를 이용하여, 상기제2실리콘 질화막 스페이서 및 일정 두께의 반도체기판을 식각하는 공정과,Etching the second silicon nitride film spacer and the semiconductor substrate having a predetermined thickness by using a mask that exposes the second film membrane spacer to a predetermined thickness;

상기 노출된 반도체기판을 열산화시켜 소자분리막을 형성하는 공정을 포함하는 것을 특징으로 한다.And thermally oxidizing the exposed semiconductor substrate to form an isolation layer.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 9 는 본 발명에 의한 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.1 to 9 are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.

먼저, 반도체기판(11) 상부에 패드산화막(13)을 형성한다.First, a pad oxide film 13 is formed on the semiconductor substrate 11.

이때, 상기 패드산화막(13)은 질소성분이 함유되어 있는 것이다.In this case, the pad oxide film 13 contains a nitrogen component.

그리고, 상기 패드산화막(13) 상부에 제1실리콘 질화막(15)을 충분히 두껍게 형성한다. (도 1)In addition, the first silicon nitride layer 15 is sufficiently thickly formed on the pad oxide layer 13. (Figure 1)

그 다음에, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(11)이 드러날 때까지 상기 제1실리콘 질화막(15) 및 패드산화막(13)을 식각한다. (도 2)Next, the first silicon nitride film 15 and the pad oxide film 13 are etched until the semiconductor substrate 11 is exposed by an etching process using an element isolation mask (not shown). (Figure 2)

이어서, 상기 구조 전표면에 제2실리콘 질화막(19)을 증착한다. (도 3)Subsequently, a second silicon nitride film 19 is deposited on the entire surface of the structure. (Figure 3)

다음, 상기 제2실리콘 질화막(19)을 상기 반도체기판(11)이 노출될때까지 전면식각하여 상기 제1실리콘 질화막(15)및 패드산화막(13)의 식각면에 제2실리콘 질화막 스페이서(20)를 형성한다. (도 4)Next, the second silicon nitride layer 19 is etched to the entire surface until the semiconductor substrate 11 is exposed, so that the second silicon nitride layer spacer 20 is etched on the etching surfaces of the first silicon nitride layer 15 and the pad oxide layer 13. To form. (Figure 4)

그 다음, 상기 제2실리콘 질화막 스페이서(20)를 식각마스크로 사용하여 상기 식각공정시 노출된 반도체기판(11)을 일정 두께 식각한다.Subsequently, the semiconductor substrate 11 exposed during the etching process is etched by a predetermined thickness by using the second silicon nitride film spacer 20 as an etching mask.

이때, 상기 제2실리콘 질화막 스페이서(20)도 소정 두께 식각이 되며, 후속공정으로 상기 반도체기판(11)을 식각하는 공정이 있으므로 적은 양의 반도체기판 (11)을 식각한다. (도 5)In this case, the second silicon nitride film spacer 20 is also etched to a predetermined thickness, and since a subsequent process of etching the semiconductor substrate 11, a small amount of the semiconductor substrate 11 is etched. (Figure 5)

그리고, 상기 구조의 전표면에 감광막(도시안됨)을 도포한다.Then, a photosensitive film (not shown) is applied to the entire surface of the structure.

그 후, 상기 제2실리콘 질화막 스페이서(20)의 양측벽 이 노출되도록 감광막 패턴(23)을 형성한다.Thereafter, the photosensitive film pattern 23 is formed to expose both sidewalls of the second silicon nitride film spacer 20.

다음, 상기 감광막 패턴(23)을 식각마스크로 하여 상기 반도체기판(11)이 드러날 때까지 상기 제2실리콘 질화막 스페이서(20)의 양측벽을 식각한다. (도 6)Next, both sidewalls of the second silicon nitride film spacer 20 are etched using the photoresist pattern 23 as an etching mask until the semiconductor substrate 11 is exposed. (Figure 6)

그 다음, 상기 감광막 패턴(23)을 제거한다.Next, the photoresist pattern 23 is removed.

그리고, 상기 양측벽이 식각된 제2실리콘 질화막 스페이서(20)를 식각마스크로 사용하여 상기 반도체기판(11)이 계단형이 되도록 식각한다.The semiconductor substrate 11 is etched so that the semiconductor substrate 11 may be stepped by using the second silicon nitride film spacer 20 etched from both sidewalls as an etching mask.

이때, 상기 제1실리콘 질화막(15)도 소정 두께 식각이 되고, 상기 반도체기판(11) 식각공정 후, 남아있는 질화막을 제거하기 위해 약간의 실리콘질화막을 식각한다. (도 7)In this case, the first silicon nitride film 15 is also etched to a predetermined thickness, and after the etching process of the semiconductor substrate 11, some silicon nitride film is etched to remove the remaining nitride film. (Figure 7)

다음, 상기 구조에 소자분리 산화막(25)을 성장시킨다.Next, a device isolation oxide film 25 is grown on the structure.

이때, 상기 제1실리콘 질화막(15)을 충분히 두껍게 형성시켰기 때문에 상기 소자분리 산화막(25)이 측면의 활성영역으로 치고 들어가는 버즈 빅의 크기가 감소된다.At this time, since the first silicon nitride film 15 is sufficiently thick, the size of the buzz big that the device isolation oxide film 25 hits the active region of the side surface is reduced.

또한, 두번에 걸쳐 상기 반도체기판(11)을 식각했기 때문에 상기 소자분리 산화막(25)이 상기 반도체기판(11)의 내부로 깊이 들어가서 소자와 소자간의 누설전류를 최소화시킨다. (도 8)In addition, since the semiconductor substrate 11 is etched twice, the device isolation oxide layer 25 deeply penetrates into the semiconductor substrate 11 to minimize leakage current between the device and the device. (Figure 8)

그 다음, 상기 소자분리 산화막(25)을 제외한 모든층을 제거한다.Then, all layers except for the device isolation oxide layer 25 are removed.

여기서, 상기 소자분리 산화막(25)이 상기 반도체기판(11)의 표면 상부로 높게 형성되지 않고, 버즈 빅의 크기도 작게 형성되어 활성영역을 넓게 확보할 수 있다. (도 9)In this case, the device isolation oxide layer 25 is not formed high on the surface of the semiconductor substrate 11, and the size of the buzz big is also reduced to secure a wide active area. (Figure 9)

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리 절연막 형성방법은, 소자분리 절연막을 형성하기 위해 소자분리 영역으로 되는 반도체기판 상부를 두번에 걸쳐 식각을 한 다음에 소자분리 절연막을 성장시킴으로써 상기 소자분리 절연막이 반도체기판 내부에 깊이 형성되어 소자와 소자간의 누설전류를 최소화시켜주고, 버즈 빅의 크기가 작게 형성되어 그에 따른 고집적화를 가능하게 하는 이점 이 있다.As described above, the method of forming a device isolation insulating film of a semiconductor device according to the present invention includes etching the upper portion of a semiconductor substrate serving as the device isolation region twice to form a device isolation insulating film, and then growing the device isolation insulating film. The device isolation insulating layer is deeply formed in the semiconductor substrate to minimize leakage current between the device and the device, so that the size of the buzz big is reduced, thereby enabling high integration.

Claims (3)

반도체기판의 소자분리영역을 노출시키는 패드산화막 패턴과 제1실리콘 질화막 패턴을 형성하는 공정과,Forming a pad oxide film pattern and a first silicon nitride film pattern exposing the device isolation region of the semiconductor substrate; 상기 패드산화막 패턴과 제1실리콘 질화막 패턴 측벽에 제2실리콘 질화막 스페이서를 형성하는 공정과,Forming a second silicon nitride film spacer on sidewalls of the pad oxide film pattern and the first silicon nitride film pattern; 상기 제1실리콘 질화막 패턴과 제2실리콘 질화막 스페이서를 식각 마스크로 사용하여 상기 반도체기판을 일정 두께 식각하는 공정과,Etching the semiconductor substrate by a predetermined thickness using the first silicon nitride film pattern and the second silicon nitride film spacer as an etching mask; 상기 제2질화막 스페이서를 일정 두께 노출시키는 마스크를 이용하여, 상기 제2실리콘 질화막 스페이서 및 일정 두께의 반도체기판을 식각하는 공정과,Etching the second silicon nitride film spacer and the semiconductor substrate having a predetermined thickness by using a mask that exposes the second nitride film spacer to a predetermined thickness; 상기 노출된 반도체기판을 열산화시켜 소자분리막을 형성하는 공정을 포함하는 반도체소자의 소자분리절연막 형성방법.Forming a device isolation film by thermally oxidizing the exposed semiconductor substrate. 청구항 1 에 있어서,The method according to claim 1, 상기 패드산화막은 질소성분이 함유되어 있는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.And the pad oxide film contains a nitrogen component. 청구항 1 에 있어서,The method according to claim 1, 상기 제2실리콘 질화막 스페이서는 질화막 또는 산화막으로 형성되는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.And the second silicon nitride film spacer is formed of a nitride film or an oxide film.
KR1019970028733A 1997-06-28 1997-06-28 Method for forming isolation layer of semiconductor device KR100422960B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173444A (en) * 1990-09-18 1992-12-22 Sharp Kabushiki Kaisha Method for forming a semiconductor device isolation region
JPH0817907A (en) * 1994-06-27 1996-01-19 Nec Corp Manufacture of semiconductor device
KR960026608A (en) * 1994-12-30 1996-07-22 김주용 Field oxide film formation method of semiconductor device
KR960026566A (en) * 1994-12-27 1996-07-22 김주용 Field oxide film formation method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173444A (en) * 1990-09-18 1992-12-22 Sharp Kabushiki Kaisha Method for forming a semiconductor device isolation region
JPH0817907A (en) * 1994-06-27 1996-01-19 Nec Corp Manufacture of semiconductor device
KR960026566A (en) * 1994-12-27 1996-07-22 김주용 Field oxide film formation method of semiconductor device
KR960026608A (en) * 1994-12-30 1996-07-22 김주용 Field oxide film formation method of semiconductor device

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